TW558811B - A method to integrate the fabrication process of integrated circuit (IC) devices and the fabrication process of a sacrificial layer - Google Patents

Abstract

A method to integrate the fabrication process of integrated circuit (IC) devices and the fabrication process of micro electro-mechanical systems (MEMS) elements. At first, a sacrificial layer is deposited on a semiconductor substrate having IC devices, and then a first pattern is etched on the sacrificial layer. Next, a structural layer is deposited, then a second pattern is etched on the structural layer. Next, a dielectric layer is deposited and vias are etched to expose contacts of the IC devices and MEMS elements. Finally, a metal layer is deposited to fill the vias and thus form conductive transmission lines. According the present invention, there are common dielectric layers and metal layers in the IC devices and MEMS elements, and we can simultaneously etch all vias on the same layer in the IC device and MEMS elements and fill in the vias with metal. Therefore, the process will reduce repetitional steps in IC devices and MEMS elements fabrication processes.

Description

558811

A process for integrating integrated circuit elements and MEMS sacrificial layers, and is particularly relevant for integrating semiconductor processes and microcomputers by using an insulating layer material suitable for enriching parts of electromechanical sacrificial layers. Micro-electromechanical and integrated circuit manufacturing plants are separate manufacturers that separate integrated-circuit devices and micro-electro-mechanical components into two separate manufacturing processes. Therefore, it is usually after the integrated circuit manufacturing plant completes all the integrated circuit manufacturing processes. Then it is sent to the micro-electro-mechanical system manufacturing plant for the micro-electro-mechanical component manufacturing process. _ However, in the manufacturing process of integrated circuit devices and micro-electro-mechanical components, the same thin-film manufacturing processes as metal deposition, dielectric layers, and etching of vias are often used, which results in repeated increases in production costs and waste. In view of this, the present invention provides a method for integrating an integrated circuit and a micro-electro-mechanical device process, including the following steps: providing a semiconductor substrate, wherein the semiconductor substrate is divided into an integrated circuit area and a micro-electro-mechanical device area, and the integrated body An integrated circuit device is formed in the circuit region; an insulating layer is deposited on the integrated circuit region and the micro-electro-mechanical element region; the insulating layer is etched to separate the insulating layer on the integrated circuit region and the micro-electro-mechanical element region ' The insulation layer on the integrated circuit area is used as an inner dielectric layer, and the insulation layer on the MEMS device area is used as a sacrificial layer; a structural layer is deposited on the MEMS device area; A dielectric layer on the structural layer and the inner dielectric layer; forming a plurality of via holes in the dielectric layer to expose a contact area between the integrated circuit area and the microelectromechanical device area; and on the Deposit a metal layer on the dielectric layer and fill in the dielectric layers

0389-7928twf (n); IDF200203029; P910148; rita.ptd page 6 558811 5. Description of the invention (2) Hole. The sacrificial layer can be formed of borophosphosilicate glass (BPSG) which has dielectric properties and is easy to etch. The invention is an integrated process, which uses the characteristics of the BPSG to form the integrated circuit dielectric layer and the MEMS sacrificial layer at the same time. The MEMS process is introduced into the general 1C process without the integrated circuit process and the MEMS component. The manufacturing process is completely divided into two independent manufacturing processes. The invention enables the integrated circuit and the micro-electromechanical component to have a common BPSG layer and a metal layer, and can simultaneously etch the interlayer holes required by the integrated circuit device and the micro-electromechanical component in the same dielectric layer and fill the same with the metal "Plugs" significantly reduce the repetitive steps of the conventional technology resulting from the integration of integrated circuits and MEMS components into two separate manufacturing processes. According to the present invention, the integrated circuit and the micro-electro-mechanical device have a common dielectric layer and a metal layer, and the dielectric layer holes required by the integrated circuit device and the micro-electro-mechanical device can be etched and filled simultaneously in the same dielectric layer. The metal plug greatly reduces the repetitive steps of the conventional technology caused by dividing the integrated circuit and the micro-electromechanical component into two independent manufacturing processes. In order to make the above and other objects, features, and comprehensibility of the present invention, a preferred embodiment will be given below, which will be described in detail in conjunction with the accompanying drawings, and will be described in detail with reference to the drawings. . The embodiment is based on the fabrication of a microcomputer, and the semiconductor substrate 10 on the right is an integrated circuit. As shown in FIG. 1, for clarity, please refer to FIG. 5 at the same time. Part 20 of the device, part 30 of the microelectromechanical element on the left. First, a semiconductor substrate 10 is provided, wherein the semiconductor substrate 10 may have an integrated circuit device 20 (for example, CMOS).

558811 V. Description of the invention (3). The material of the semiconductor substrate 10 is, for example, a silicon wafer or a GaAs substrate, and any desired semiconductor element such as a CMOS transistor, a resistor, a logic element, etc. can be formed above it, but in order to simplify the diagram here, Only a flat substrate with CMOS transistors on it is shown. An insulating layer 11 is deposited on the aforementioned semiconductor substrate 10, which can be borophosphosilicate glass (BPSG). The thickness of this insulating layer 110 ranges from about 6500 to 1 1 000 A. Among them, the BPSG can be in Si, PH3, B2 & In an environment, formed using atmospheric pressure chemical vapor deposition (APCVD), and then planarized by chemical mechanical polishing, and annealed the insulating layer 11 formed by BPSG using rapid thermal process (RTP), In order to densify the insulating layer 110. The insulation layer 110 is further defined and its shape is etched. As shown in FIG. 2, 'the insulation layer 110a separating the above-mentioned insulation layer 110 as the integrated circuit device 20' is also used as the micro-electromechanical element 30. Sacrifice layer. Next, a structure layer 12 |) and a thermal resistance heater layer 160 are sequentially deposited on top of the dielectric layer 110a and the sacrificial layer 110b. The structure layer 丨 2 can be a gasified stone (S "& its thickness is about 1 00 〇A, can be used low pressure chemical gas 'phase deposition method (LPCVD)' with two gas stone fired (SiClgH2) and Ammonia (Njj3) is a reaction gas that is deposited at an operating temperature of 250 ~ 40 0 ° C; and the thermal resistance heater layer 160 may be titanium nitride (TiN), and its thickness is about 14000 ~ 28 〇 ^ A 'Can be metal dry' Using anti-deer gas mixed with rat gas and nitrogen to form a titanium nitride layer by reactive sputtering. "Next, the general standard integrated circuit photolithography etching process The shapes of the thermal resistance heater layer 160 and the structure layer 120 are sequentially defined, as shown in FIG. 3.

558811 V. Description of the invention (4) A '-again' As shown in FIG. 4, an intermetal dielectric layer 130 is formed over the semiconductor substrate 10. The material of the intermetal dielectric layer 13 may further include: , Containing silicon oxide, low dielectric constant spin-on glass, tetraethoxy silicate glass, gasification, phosphorus-doped silicon oxide, fluorinated silicon oxide (F-Si〇2), oxynitride, fluorite Breaking glass (FSG), phosphosilicate glass (PSG), undoped silica glass (HDP-USG) deposited by high-density plasma, and oxidized stone deposited by high-density plasma

Oidp-sio2), oxidized silica deposited by sub-pressure chemical vapor deposition (SACVD), and oxidized silica deposited by ozone-tetraethoxysilane (〇3-TEOS). Next, as shown in FIG. 5, the interlayer hole 131 of the MEMS region is etched through the intermetal dielectric layer 130 or through the intermetal dielectric layer 13 and the BPSG layer 11 to expose the integrated circuit device and The contact area of the micro-electromechanical device is 131 °. Finally, a metal layer 140 is deposited on the intermetal dielectric layer 130, and the metal of the metal layer fills the interlayer hole 1 3 1 and the shape of the metal layer is etched as a metal. The metal layer 140 is formed by depositing copper in a physical vapor deposition (pVD) manner. In summary, in this embodiment, the same insulating layer, such as BPSG, is used as both the dielectric layer of the integrated circuit and the sacrificial layer of the micro-electromechanical device. That is to say, in the process after the integrated circuit, part of the micro-electro-mechanical process is introduced, and at the same time, some of the process steps of the micro-electro-mechanical element are completed. Next, as shown in FIG. 6, a protective layer 150 may be deposited, which may be polycrystalline silicon. Referring to US Pat. No. 0621 3589, the substrate 10 is etched on the back surface to form an opening of the substrate 10 to remove the sacrificial layer 11. 0 b, a micro-electromechanical nozzle with cavity 1 3 can be completed; this step can be achieved by wet etching

〇389-7928twf (n); IDF200203029; P910148; rita.ptd

558811 Fifth, the description of the invention (5) __, the appropriate selection of the sacrificial layer 110b and the low dielectric constant material

Li: A very high etching selection ratio can be achieved. At present, the two types of wet etching are immersion etching (lmmersion etchi type) (spray etching), which can be applied to this process. The process described above will be used to process some micro-electromechanical components and human circuit components. In order to reduce the repetition of two different processes, the insulation layer and the metal layer are deposited on the integrated body. Then, the micro-electromechanical element is, for example, formed by etching away the insulating layer in the integrated circuit manufacturing process. The nozzle with a cavity can also be used in the manufacturing process of integrated circuit components for the suspension armature switch of the present invention. In the same way, although the present invention has been disclosed in the preferred embodiment as above; it is lacking in the present invention. 'Anyone who is familiar with this skill, no; within a certain range, can make some changes and decoration, because the spirit and encirclement of 2 will be defined by the scope of the attached patent application. The protection scope of the month 0389 -7928twf (n); IDF200203029; P910148; rita.ptd Page 10

Claims (1)

558811 丄 · A method for integrating integrated circuit and micro-electro-mechanical device manufacturing process, including the following steps: a) Provide a semiconductor substrate, wherein the semiconductor substrate is divided into a product area and a micro-electro-mechanical device area, and the integrated circuit area Forming an integrated circuit device; b) depositing an insulating layer on the integrated circuit area and the micro-electromechanical element area; a c) engraving the insulating layer to separate the integrated circuit area and the micro-electromechanical component area The insulating layer on the integrated circuit area is used as an inner dielectric layer, and the insulating layer on the micro-electro-mechanical device area is used as a sacrificial layer; d) a structure layer is deposited on the micro On the electromechanical element area; e) depositing a dielectric layer on the structural layer and the inner dielectric layer; and forming a plurality of via holes in the dielectric layer to expose the integrated circuit area and the micro A contact area of the electromechanical element area; and g) depositing a metal layer on the dielectric layer and filling the dielectric hole. 2. The method of integrating integrated circuit and microcomputer electrical component manufacturing process as described in item 1 of the scope of patent application, wherein the integrated circuit device includes a CMOS electrical crystal, a resistor or a logic element. 3. The method of integrating integrated circuit and microcomputer electrical component manufacturing process as described in item 1 of the scope of patent application, wherein the insulating layer material is boron-doped phosphosUicate glass (BPSG). 4 · The method for integrating integrated circuit and microcomputer electrical component manufacturing process as described in item 3 of the scope of patent application, which further includes rapid thermal processing of the borophospho glass 0389-7928twf (n); IDF200203029; P910148; rita.ptd Page 12 558811 VI. Patent application process (RTP, rapid thermal process) for annealing. 5 · The method of integrating integrated circuit and micro-electro-mechanical device manufacturing process as described in item 1 of the scope of patent application, wherein the thickness of the insulating layer is about 6500 ~ 1000 A 〇6 · The integration as described in item 1 of the scope of patent application A method for manufacturing integrated circuits and micro-electro-mechanical components, wherein the micro-electro-mechanical components include micro-electro-mechanical nozzles or micro-electro-mechanical switches. 7. The method for manufacturing integrated circuits and microcomputer electrical components as described in the first item of the patent application, wherein the material of the structural layer is silicon nitride (Si3N4), and the thickness is about 10,000 A. 8. The method of integrating integrated circuit and micro-electro-mechanical device manufacturing process as described in item 1 of the application scope, further comprising removing a portion of the insulation layer located on the micro-electro-mechanical device to release the micro-electro-mechanical device portion. 9. A method for integrating integrated circuit and micro-electro-mechanical device manufacturing process, including the following steps: a) providing a semiconductor substrate, wherein the semiconductor substrate is divided into an integrated circuit area and a micro-electro-mechanical device area, and the integrated circuit area is formed; There is an integrated circuit device; b) a borophospho glass layer is deposited on the integrated circuit area and the MEMS component area; c) the borophospho glass layer is etched to separate the integrated circuit area and the MEMS The insulating layer on the device area, wherein the borophospho glass layer on the integrated circuit area is used as an inner dielectric layer, and the borophospho glass layer on the MEMS area is used as a sacrificial layer; 558811 6. Scope of patent application d) depositing a structure layer on the MEMS element area; e) depositing a dielectric layer on the boron-filled glass layer; 〇 forming a plurality of interlayer holes in the dielectric layer To expose the contact area between the integrated circuit region and the MEMS element region; g) depositing a metal layer on the dielectric layer and filling the interlayer holes; and h) removing the MEMS element region Boron-filled glass layer. 10. The method of integrating integrated circuit and micro-electro-mechanical device manufacturing process as described in item 9 of the application scope, wherein the integrated circuit device includes CMOS. 12 Micro-Electro-Mechanical 6 5 0 0 ~ 1 丄 u u u a. 11 · The method of integrating integrated circuit and microcomputer electrical component manufacturing process as described in item 9 of the scope of patent application ', which further includes annealing the rotten phosphor glass by a rapid thermal process (RTP). Circuit and 1 00 00 A 〇3. The method of integrating integrated circuit and micro-electro-mechanical component manufacturing process as described in item 9 of the scope of patent application 'wherein the micro-electro-mechanical component includes a nozzle or 14. The method of integrating integrated circuit and electrical component manufacturing process described above, wherein the material of the structural layer is called 0389-7928twf (n); IDF200203029; P910148; rita.ptd page 14