TW557557B - Wafer level burn-in board and method for forming the same - Google Patents

Abstract

A wafer level burn-in board is used for electrically connecting to a wafer under test. The wafer level burn-in board includes a substrate and a plurality of needle electrodes. The needle electrodes are formed on a surface of the substrate with a plurality of contact pads. Each needle electrodes comprises a strip metal layer and a strip support layer. The strip metal layers are combined on the corresponding contact pads and extend to the corresponding strip support layers. Each strip support layer is formed at a side surface of the corresponding strip metal layer, so as to provide a good elastic support for the strip metal layers. While the needle electrodes contact test electrodes of a wafer under test, the needle electrodes elastically absorbing the thermal stress and fully contact with the wafer.

Description

557557 V. Description of the invention (1) [Field of invention] Kind of ί :::: 关:-Kind of wafer-level burn-in board 'is particularly related to — ⑽; 2 Λ is in full contact with the wafer to be tested (w1 contact ) Japan-Japanese yen burn-in board and its forming method. [Preliminary technology] It is known that semiconductor devices need to undergo burn-in test (b — one type = aging test, aging test) with the QFP, BGA * Flip Chip probability. The so-called “burn-in test” is = latitude test, which is a semiconductor device Combined with a burn-in board. ', (Bua-ln board) to make it in a preset environment, such as temperature: first ΐ i: f and other test conditions, to accelerate early failures, and then divide = test It is oriented towards the manufacturing process integrated into the wafer, which is about to be pre-burned. There is no need to pre-burn individual wafers. The collapsed card "wafer level is universal, which includes-collapsed furnace interface card and-collapsed right furnace interface card-the end system is connected to the collapsed furnace, and several other-electrodes, this first touch card One end has a complex point, and the chip should be electrically connected to the corresponding chip on the contact card-the wafer to be tested; the electric r is used to face the second electrodes respectively: there are multiple Welding process, the process, the temperature during the collapse of the "pre-burning" process, room temperature page 6 557557 V. Description of the invention (2) 1 should be connected to 25 C to the left card right heart life π ^ day ® thermal expansion The coefficients do not match. Therefore, the bump should contact the technician Tian I ai between the Kaxing wafers and the bump should contact the card: the second thermal stress (the thermal stress), the tin bump, the first-the electrode system is a bump electrode ( bumps) (If soldering h is not elastic and cannot effectively absorb the heat of the bonding interface, it is also necessary to maintain full electrical contact with the solder pads of the wafer under test. [Objective and summary of the invention] The main purpose of Yuanyou A wafer-level burn-in board is provided. The wafer :: pre-burner board has a plurality of needle electrodes, each needle electrode It contains your metal layer and-strip-shaped support |, these strip-shaped branch floors are related to these: Hai this needle-shaped: f for a good elastic support, j wafer burn-in board can be used μ twenty The shaped electrode absorbs thermal stress and ensures complete contact with the wafer to be tested. This, and the second purpose is to provide a wafer-level burn-in board formation, which first forms a sacrificial photoresist on the substrate, and then forms a Thick photoresist .: The 2 photoresist layer pattern ① is formed on the supporting surface of the sacrificial photoresist with a metal covering the supporting layer, and then the sacrificial light is removed. Therefore, a plurality of Needle-shaped electrodes supported elastically for full electrical contact with a test electrode of a wafer to be tested. ^ The wafer-level burn-in board of the present invention is composed of a substrate and a plurality of needle-shaped electrodes. The electrode system is formed on one surface of the substrate, and the surface of the 1 U.S. plate is formed with a plurality of connection ridges. Each needle electrode system has a / two-shaped metal layer and a strip-shaped branch floor. Among these strip-shaped metal layers ^, Combined with the corresponding connection pad, the other end is extended to the bar-shaped support lure, and The strip-shaped support layers are formed on the _side & surface of the corresponding strip-shaped metal layer,

557557

To support the strip metal layers. The method for forming a wafer-level burn-in board according to the invention includes the steps of providing a substrate such as a Shixi substrate, a printed circuit board, or a ceramic substrate, and a plurality of connection pads are formed on one surface of the substrate; b) forming a plurality of sacrificial photoresist on the surface of the substrate, the sacrificial photoresist does not cover the connection pads ^ and each sacrificial photoresist has a supporting surface; c) forming a thick photoresist layer on the substrate The surface is covered with a sacrificial photoresist, the thickness of which is between 2 5 ~ 2 5 0 // m, d) the thick photoresist layer is patterned to form a plurality of supporting layers, which are formed on the sacrificial photoresist E) forming a plurality of metal layers, the metal layers are bonded to the connection pads on the surface of the substrate and cover the corresponding supporting layers; and f) removing the sacrificial photoresist, so that the supporting layers support the Some metal layers. [Detailed description of the invention] Please refer to the attached drawings. The present invention will be described in the following embodiments. In a specific embodiment of the present invention, FIGS. 1 to 5 are a wafer-level burn-in board 100 ( wafer level burn-in board). First, as shown in FIG. 1, a substrate 11 is provided, such as a silicon substrate, a printed circuit board (PCB), or a ceramic substrate, etc. In this embodiment, 'The substrate 1 1 0 is a printed circuit board made of polyimide (p ο 1 yimide) or glass fiber reinforced resin. One surface 111 of the substrate 1 1 0 is formed with a plurality of connection pads 112 (contact pads). , Such as copper pad (Cu pad) or Ming pad (A1 pad), etc., these connections

Page 8 557557 V. Description of the invention (4) The arrangement corresponds to the test electrode 411 of the wafer under test 400 (as shown in FIG. 6), such as a grid array, a central arrangement or a peripheral arrangement, and a screen version Screen printing or photolithography (including exposure, development, and other processes) and other methods' A plurality of sacrificial photoresists 200 (sacrificial photoresist) are formed on the surface 111 of the substrate 110, and these sacrifices The photoresist 200 does not cover the connection pads 112 and has a supporting surface 210. Preferably, the side branch 2 10 and the surface of the substrate 11 0 are in a non-vertical relationship, such as a slope or a curved surface. In order to facilitate the formation of the needle electrode 20, and make it have better elasticity. Afterwards, as shown in FIG. 2, a thick photoresist layer 300 is formed on the surface 111 of the substrate 110 by spin coating, printing, or spray coating, and the like. The layer system covers the sacrificial photoresist 2000. In this embodiment, the material of the thick photoresist layer 3000 is selected from Micro-Chem, and the product model is 讥 -8 2000. The thick photoresist The thickness of the layer 300 is between 25 and 250 // m (the conventional photoresist thickness is between 0.5 and 10 // m), which is a negative photoresist and contains a high dielectric constant. High molecular polymers (such as polyimide, benzylcyclobutene or others) and light-sensitive substances. As shown in FIG. 3, the lithographic imaging technology is used to pattern the thick photoresist layer 3 0 to form a plurality of supporting layers 1 2 2, which are formed on the corresponding sacrificial photoresist 2 0 0 support. The surface 2 1 0, preferably, one end 124 of the supporting layer 1 2 2 is bonded to the surface of the substrate 110 丨! The non-electrode part (that is, the part where the connection pad 1 12 is not formed).

Page 557557 5. Description of the invention (5) Then, as shown in FIG. 4, a plurality of metal layers 121 are formed by means of plating, evaporation, sputtering, or etching. The metal layers 121 are metals such as nickel, gold, silver, copper, or palladium, which are bonded to the connection pads 112 ′ of the substrate and cover the support layers 122, and the metal layers 121 are Extend diagonally. Finally, as shown in FIG. 5, the sacrificial photoresist 200 is removed to form a wafer-level burn-in board 100. The wafer-level burn-in board 100 includes a substrate 110 and A plurality of needle electrodes 1 2 0, each needle electrode 1 2 0 has a metal layer 121 and a support layer 122, wherein the metal layers 121 and the support layers 1 2 2 are in a strip shape, the metal layer One end of 1 2 1 is electrically connected to the corresponding connection pad 112, and the other end is extended to the supporting layer 122, and the supporting layers 1 to 22 support the corresponding metal layer 2 to provide good elastic support. Therefore, by sacrificing the support surface 21 (such as an inclined surface or a curved surface) of the photoresist 20, a needle electrode extending obliquely or curvedly can easily be formed, and the support layer 122 formed by the thick photoresist layer 300 It can also be supported on one side surface 123 of the metal layer 121. In addition, in the process of forming a wafer-level burn-in board 10 (), the sacrificial photoresist 200 can also be flexible such as polyimide or phenylcyclobutene Polymer polymer is substituted, and the step of forming a thick photoresist layer 300 is skipped, and the metal layer 121 ′ is directly formed in a manner such as ^, and then partially etched with polyimide or: butadiene to form a support layer 122, and support the good elasticity. % 「Also as shown in Fig. 6, a wafer under test 400 is electrically connected.

# The wafer-level burn-in board 1 0 0 of the present invention is used for contacting ’to perform wafer-level burn-in (w a f e r

557557 V. Description of the invention (6) level burn-in), where the wafer under test 400 is a wafer of a memory, a micro processor or a microcontroller, etc., which has a plurality of wafers 410, each wafer 410 has an active surface 411 (active surface) and a non-active surface 412 (passive surface). The power electrode of the integrated circuit of each chip 4 1 0 on the active surface 4 1 1 is connected to a plurality of test electrodes 41 3 ( test electrodes), the test electrodes 413 may be formed on the active surface 4 1 1 corresponding to the wafer 410, or may be formed on the cutting path or the periphery of the wafer 4 00 (not shown in the figure), during the burn-in process, The needle electrodes 120 of the wafer-level burn-in board 1000 correspond to the test electrodes 413 for electrical contact with the wafer-level burn-in board 100, and the wafer to be tested is not The active surface 41 2 is carried and fixed by a wafer carrier 420. As shown in FIG. 7, the needle electrode 120 of the wafer-level burn-in board 100 is electrically contacted with the wafer 400 to be tested. Electrode 41 3, the side surface 1 2 3 of each metal layer 1 21 of the needle electrode 1 2 0 is formed with a support layer 1 2 2 ′ to provide good The elastic support makes these needle-shaped electrodes 丨 2 〇 have better elasticity 'When the temperature is heated up (about 25 ℃ to 丨 25 ℃), the joint interface between the substrate 11 and the wafer 400 is thermally expanded. The thermal stress generated by the mismatch of the coefficients will be elastically absorbed by the needle electrodes 丨 20, so that the metal layer 1 2 1 of the needle electrodes 1 2 1 can maintain effective contact with the test electrode 4 1 of the wafer under test 4 1 3 'Therefore, the wafer-level burn-in board of the present invention can ensure full contact with the wafer 400 to be tested during the wafer-level burn-in process, so as to complete the wafer-level burn-in test reliably. Therefore, the scope of protection of the present invention shall be defined by the scope of the appended patent application ^ shall prevail. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention shall be protected by the present invention. Fan

557557

Page 12 557557 Brief description of the drawings [Illustration of the drawings] Figure 1. According to the invention Figure 2 According to the invention Figure 3 According to the invention Figure 4 According to the invention Figure 5 According to the invention Figure 6 According to the invention Figure and Figure 7: Partially placed according to the present invention [Illustration of the drawing number] 100 wafer-level burn-in board 110 substrate 111 surface 120 needle electrode 121 metal layer 123 side surface 200 sacrificial photoresistor 300 thick photoresistor 400 Wafer 410 Wafer 411 Active surface 420 Carrier 11 2 Connection pad 122 Support layer 1 2 4 End 2 1 0 Support surface forms a cross-sectional view of a substrate of a sacrificial photoresist; Cross-section view of a substrate forming a thick photoresist layer; Sectional view of the substrate; Sectional view of the substrate forming the metal layer; Sectional view of the wafer-level burn-in board; Cross-section of the wafer burn-in board and a wafer to be tested 412 Non-active surface 413 Test electrode

Claims (1)

557557 6. Scope of patent application [Scope of patent application] 1. A wafer-level burn-in board includes a substrate, one of which includes a plurality of needle electrodes, each layer and a support layer, of which the corresponding For the connection pad, strip-shaped support layers at the other end are formed in pairs to support the strip-shaped metal layers. 2. For example, in the scope of patent application, one of these strip-shaped support layers is at the end. 3. If the strip-shaped branch floors in item 1 of the patent application are thick photoresistors 4, if the strip-shaped support layers in item 1 of the patent application scope are benezo cyclobutene 5. If the patent application scope is 1 The strip-shaped metal layers are nickel and gold. For example, the substrate in the scope of patent application No. 1 is a Shixi substrate, printed electronics, and a wafer-level burn-in board. A) Provide a substrate, the substrate pad; For electrical contact with a wafer to be tested, a plurality of connection pads are formed on its surface; and the needle electrode system includes a strip of metal, and one end of the strip metal layers is connected to the strip support layer. And one side surface of the corresponding strip metal layer, the wafer-level burn-in board, wherein the non-electrode combined with the wafer-level burn-in board described in the surface of the substrate, wherein (thick photoresist). The wafer-level burn-in board, wherein the amine (polyimide) or benzocyclobutene is the wafer-level burn-in board, wherein the, silver, copper or palladium. The wafer-level burn-in board is a circuit board or a ceramic substrate. Forming method, the steps of which include: & / surface system has a plurality of connections Page 14 557557 VI. Application scope b) Forming a plurality of sacrificial photoresist on the surface of the substrate, the sacrificial photoresist does not cover the connection pads, and each sacrificial photoresist has a supporting surface; C) Forming a thick photoresist layer on the surface of the substrate; d) patterning the thick photoresist layer to form a plurality of supporting layers, which are formed on the supporting floors of the sacrificed photoresist; e) forming a plurality of metals Layers, the metal layers are bonded to the connection pads of the substrate and cover the corresponding support layers; and f) the sacrificial photoresists are removed, so that the support layers support the metal layers. 8. The method for forming a wafer-level burn-in board as described in item 7 of the scope of patent application, wherein in step (d) of patterning the thick photoresist layer, one end of the support layers is bonded to the Non-electrode portion on the substrate surface. 9. The method for forming a wafer-level burn-in board as described in item 7 of the scope of patent application, wherein the way to form the sacrificial photoresist is screen printing or photolithography ° 1 0. The method for forming a wafer-level burn-in board according to item 7 of the scope of the patent application, wherein the method for forming a thick photoresist layer is sp i η coating, printing, or spraying. coating) 〇Π, the method for forming a wafer-level burn-in board as described in item 7 of the scope of the patent application, wherein the methods for forming the metal layers are plating, evaporation, and bonding ( sputtering) or touch 557557 VI. Patent application range etching 〇1 2. The method for forming a wafer-level burn-in board as described in item 7 of the patent application range, wherein in step (a) of providing a substrate, the substrate is Silicon substrate, printed circuit board or ceramic substrate. _ Page 16