TW554481B - A method of backend process integration - Google Patents

Abstract

A method of backend process integration is provided. A dielectric layer as a inter-layer dielectrics or an inter-metal dielectrics is deposited on a substrate first. A silicon hardmask is then formed and defined on the dielectric layer as a hardmask of following etching process. An etching process is performed to form a contact opening or a via opening in the dielectric layer. A nitridation is performed to convert the silicon hardmask into a nitride or oxynitride layer.

Description

554481 V. Description of the invention (1) The present invention relates to a semiconductor process, and particularly to a method for backend process integration.

Ik's semiconductor process continues to develop, and metal contact windows or interstitial window openings will also become smaller and smaller. Therefore, polysilicon or amorphous silicon (amorph〇us siHc〇n) is currently used to replace light. The photo resist acts as a siHcon hardmask. However, if the silicon hard mask layer is not removed after the remaining processes, the silicon hard mask layer will be subsequently sputtered and annealed with titanium and titanium nitride (Ti / TiN) layers. During the process), a self-aligned salicide metal is formed, and the self-aligned silicide metal (ie TiSix) will be difficult to be grinded by tungsten chemical mechanical grinding (CMP) or tungsten etching back process. Removal, so that the titanium silicide remaining on the dielectric layer will cause a short circuit in subsequent metal circuits. In addition, for certain leakage current (1 eakagecurrent) or data retention rate of memory, certain semiconductor components, such as flash memory, complementary metal-oxide-semiconductor image sensing, are more stringent. Device (C Μ 0 S image sensor), or the liquid crystal element (LCOS) on the sill, usually inter_iayer dielectrics (ILD) or inter-metal dielectrics (IMD) ) To deposit a thin layer of silicon nitride (silicon nitride) or silicon oxy-nitride as a charge-trapping layer to protect the components from plasma damage in subsequent etching processes. damage), and can prevent leakage current, improve the data retention rate of the memory, and make the fault voltage (

9589twf.ptd Page 5 554481 V. Description of the Invention (2) --- Two,; ^ Will: drop? x achieves better inter-oxide integration (gate at the contact window / gr: y? iGoi). However, after the nitrite or oxynitride layer (0, contact, or via) is etched, the subsequent metal layer is etched under the treatment of the resistance removal step in the case of oxygen ^ 2 ^ Yes, the capture capability will be greatly reduced, which will affect the electrical performance of the device. Therefore, the object of the present invention is to provide a back-end process integration system r: without silicon hard cover curtain layer in the titanium layer and titanium nitride layer. Self-aligned silicided metal was formed during the spattering of the i-version. 版 ui

Another purpose of the invention is to provide a back-end process integration to protect memory elements from damage. Method 'Another object of the present invention is to provide a back-end process integration that can improve the electrical performance of M so that the data retention rate of the memory does not increase the leakage current.准. Another objective of the present invention is to provide a back-end process integration so that the fault voltage does not drop to achieve a better gate oxide layer. According to the above and other purposes, the present invention proposes a back-end The method of forming a whole A = includes firstly depositing an inner dielectric layer or an inner layer on a substrate.

: Dielectric layer, and then f: dielectric to perform the planarization process, such as chemical J Φ grinding (Chemical mechamcal polish (CMp)). Called-silicon hard mask layer, such as polycrystalline silicon layer or amorphous silicon layer, and then define this / hard mask layer. Next, an etching process is performed to form a contact window or a dielectric window in the inner dielectric layer ′ metal dielectric layer. Subsequently, a nmidation process is performed to make the material cover curtain layer be nitrogen cut or oxygen cut.

554481

Because the present invention utilizes gas, nitrogen and oxygen to cut the layer, the manufacturing process makes the Shi Xi hard mask layer into a nitrogen step, and silicon can also be avoided. The titanium layer, the titanium nitride layer, and the plating and degraded silicon layer can protect the element and the metal. The problem of leakage current caused by the formed silicon nitride or oxynitride is caused by the plasma damage in the subsequent etching process to prevent Xi from falling, so as to achieve a good data retention rate of the memory, so that the fault voltage is a good time for the invention Oxidation layer integration.

It is easy to understand. The following special descriptions and other purposes, features, and advantages can be more clearly described as follows: The preferred embodiment of the cattle, and in conjunction with the attached drawings, the detailed description of the drawings: 100 ′ m: substrate 101 , 201: diffusion barrier (diffusion barrier) 102: dielectric layer 104, 104a: silicon hard cover curtain layer 106: photoresist layer 108: opening

110, 204, 216: nitride layer 202: inner layer dielectric layer 2 0 8: contact window opening 21 0: contact window plug 212, 222: metal layer 214: inner metal dielectric layer

554481

218: through window opening 220: through window plug embodiment Figures 1A to 1E are cross-sectional views of the manufacturing process of a semiconductor device according to a preferred embodiment of the present invention. People (backend process integration). Referring to FIG. 1A, a dielectric layer 102 as an inner dielectric layer or an inner metal dielectric layer is formed on the substrate 100, and the material is, for example, oxygen / dagger stone. After that, the dielectric layer 102 is subjected to a chemical mechanical polishing, and the thickness of the dielectric layer 102 is about 8000 angstroms. In addition, a diffusion barrier layer (such as a silicon nitride or silicon oxynitride layer) may be formed on the substrate 100 before the dielectric layer 102 is formed. Then, please refer to FIG. 1B, a silicon hard mask layer 104 is formed on the dielectric layer 102. The silicon hard mask layer 104 is, for example, a polycrystalline silicon layer or an amorphous silicon ( amorph〇us siiicon) layer. Next, please refer to FIG. 1C, and define the silicon hard mask layer 丨 〇4 as a mask for the subsequent description process, and the method of defining the silicon hard mask layer 丨 〇4 is, for example, formed on the silicon hard mask layer 104 A patterned photoresist layer 106 is used, and the photoresist layer 106 is used as an etching mask to etch the silicon hard mask layer 104 to obtain a patterned silicon hard mask layer 104a. Thereafter, referring to FIG. 1D, the photoresist layer 10 was removed, and the Shixi hard mask layer 104a was used as an etching mask to etch the dielectric layer 〇2 to the dielectric layer 102. An opening 108 is formed in the opening, such as a contact window or a via window. Moreover, if the base 10 () also includes the first

9589twf.ptd Page 8 554481 V. Description of the invention (5) A silicon nitride layer formed before (5), then the etching stop layer of the etching process is this silicon nitride layer 101. At this time, the remaining thickness of the silicon hard mask curtain layer 丨 0 4 a is between 100 and 2000 angstroms. Then, referring to FIG. 1E, a nitridation process is performed to change the silicon hard mask layer into a nitride layer 110. The material is, for example, a silicon nitride or silicon oxynitride layer. The manufacturing process is, for example, plasma nitriding or a nitriding annealing process including furnace annealing and rapid thermal annealing (RTA), and the above nitriding processes use a nitrogen-containing gas, such as Nitrogen (chemical), ammonia (NH3), nitric oxide (no), or nitrous oxide (n2O). Then, another etching process may be performed to remove the diffusion barrier layer 101 at the bottom of the opening 108. Example In order to enhance the applicability of the present invention, please refer to FIG. 2. Fig. 2 is a cross-sectional view of an exemplary metal interconnect according to a preferred embodiment of the present invention. Please refer to FIG. 2. According to the foregoing preferred embodiment, applying the present invention to a metal interconnect process in a semiconductor process can obtain the results shown in FIG. 2, including forming a substrate 200 on a substrate. The inner dielectric layer 202 ′ is formed on the inner dielectric layer 202 and is defined as a hard mask layer which is used as an insect mask. In addition, the inner dielectric layer may be formed on the substrate before the inner dielectric layer 202 is formed. A diffusion barrier layer 201 is first formed on 2000. After a contact window opening 208 is formed in the inner dielectric layer 202 after the etching process, a nitride process is performed on the Shi Xi hard mask layer so that the silicon hard mask layer becomes a nitride layer.

Page 9 554481 V. Description of the invention (6) 2 〇 4 ′ The nitriding process can be plasma nitriding with lower process temperature or furnace tube annealing and rapid thermal annealing (RTA) with higher process temperature. Next, please continue to refer to FIG. 2 to form a contact window plug 210 in the contact window opening 208. Before forming the contact window plug 21, the method further includes performing a titanium layer and a titanium nitride layer (Ti / TiN). Sputtering; and performing an annealing process. Subsequently, a metal layer 2 1 2 is formed on the contact plug 21 0. After that, similar to the above process, an inner gold layer dielectric layer 214 is formed on the substrate 200 to cover the metal layer 212, and then a silicon hard mask curtain layer is formed on the inner gold layer dielectric layer 214 and defined as an etching mask. screen. After an interlayer window opening 218 is formed in the inner gold layer dielectric layer 214 after the etching process, another nitridation process needs to be performed on the Shixi hard mask layer to make the silicon hard mask layer into another nitride layer. 216 ^, in which the nitridation process can choose a nitriding process with a lower process temperature, such as plasma nitridation, so as to prevent the previously formed metal layer from being affected by excessive temperature and causing defects. Thereafter, a via window plug 220 is formed in the via window opening 218. Then, another metal layer 222 is formed on the via window plug 22 and the interconnection process is completed. The sign package of each product is still · 1 · The present invention uses a nitriding process to make the silicon hard screen a silicon or oxynitride layer, so that the silicon hard screen is prevented from entering the titanium layer and Self-aligned gold silicide is formed during the sputtering and annealing process of the titanium oxide layer. The present invention uses a nitriding process to make the hard mask layer or the silicon oxide layer to avoid damage to the subsequent etching process. ). It is made into π by electric water 3. The present invention is because the hard cover layer becomes nitrogen cut or oxynitride.

554481 V. Description of the invention (7) layer, so it can prevent leakage to maintain the data retention rate of the memory and prevent the breakdown voltage from falling 'to achieve better integration of the gate oxide layer (Gate 〇xide integrity, referred to as g〇I). Limitation ϊ = hair: the month has been disclosed as above in a preferred embodiment, but it is not intended to be used by any person skilled in the art. Without departing from the present invention, God can make various changes and improvements. Zhi Shen Zhishi 丨 ^^ ^ Ming's protection owes to Moxibustion Jiaming.

554481 Brief description of the drawings Figures 1A to 1E are cross-sectional views of the manufacturing process of a semiconductor device according to a preferred embodiment of the present invention; and Figure 2 is an example of a metal according to a preferred embodiment of the present invention A cross-sectional view of the interconnect. ill 9589twf.ptd Page 12

Claims (1)

554481 々, 7 patents for integrating back-end process integration methods, including forming a dielectric layer on the substrate; forming a single hard film layer on the dielectric layer; defining the silicon hard mask layer; performing an etching A process of forming an opening in the dielectric layer; and performing a nitriding process. 2. The method for integrating back-end processes as described in item 1 of the scope of the patent application, wherein the silicon hard mask layer includes one of a polycrystalline silicon layer and an amorphous silicon layer. 3. The method for integration of a back-end process as described in item 1 of the scope of patent application, wherein the nitriding process includes plasma nitriding. 4. The method of integrating the rear-end process as described in item 1 of the scope of patent application, wherein the nitriding process includes one of furnace tube annealing and rapid thermal annealing. 5 · The method of integrating the rear-end process as described in item 2 or 3 of the scope of patent application ', wherein the nitriding process uses a nitrogen-containing gas. 6. The method for integrating back-end processes as described in item 1 of the scope of patent application, wherein after the nitriding process is performed, the silicon hard mask layer is made to include one of a silicon nitride layer and a silicon oxynitride layer. 7. The method of integration of a back-end process as described in item 1 of the stated patent scope, which further includes forming a diffusion barrier layer before forming the dielectric layer on the substrate. As described in the method of integration of back-end process as described in item 7 of the patent scope, the 8M expansion barrier layer includes one of a silicon oxide layer and a silicon oxynitride layer. i The method of integration of the back-end process as described in item 7 of the scope of patent application, and / or after performing the hafnium nitridation process, it further includes removing the expansion at the bottom of the opening. 1 〇. A method for manufacturing metal interconnects, comprising: forming an inner dielectric layer on a substrate; forming a first hard mask layer on the inner dielectric layer; defining the first silicon hard A mask layer; using the first silicon hard mask layer as an etching mask, performing an etching process on the inner dielectric layer to form a contact window opening σ in the inner dielectric layer; performing a first nitriding A process for making the first silicon hard mask curtain layer a first nitride layer; forming a contact window plug in the contact window opening; forming a first metal layer on the contact window plug; on the substrate An inner gold layer dielectric layer is formed thereon to cover the first metal layer; a second silicon hard mask layer is formed on the inner gold layer dielectric layer; defining the second silicon hard mask layer; using the second The silicon hard mask layer is used as an etching mask, and a gold engraving process is performed on the inner gold layer dielectric layer to form a dielectric window opening in the inner gold layer dielectric layer; a second nitriding process is performed so that The second Shi Xi hard cover curtain layer becomes a second nitride layer; it is shaped in the opening of the via window. A via plugs; the plug and forming a second metal layer on the vias. 11. Manufacture of metal interconnects as described in item 10 of the scope of patent application 9589twf.ptd Page 14 554481 6. Scope of Patent Application Method 'The second nitriding process further includes controlling the process temperature to prevent defects in the first metal layer. 1 2 · The method for manufacturing a metal interconnect as described in item 10 of the patent scope of the patent, wherein the first silicon hard cover curtain layer and the second silicon hard cover curtain layer include " One of the crystal second layers. 13 · The method for manufacturing a metal interconnect as described in item 10 of the patent application scope, wherein the first nitrided process and the first nitrided process include electro-nitriding I 1 4. The method for manufacturing a metal interconnect as described in the scope of the patent application, wherein the first nitriding process includes furnace tube annealing and rapid thermal annealing < ° 1 5 · As applied The manufacturing method of the metal interconnects as described in the third or the fourteenth of the patent scope, wherein the gas system used in the first nitriding process and the first nitriding process contains a nitrogen gas. 1 6 · As applied The method for manufacturing a metal interconnect as described in the patent scope item 10, wherein the first nitride layer and the second nitride layer include one of a silicon nitride layer and a silicon oxynitride layer. 1 7 • As applied The method for manufacturing a metal interconnect as described in item 10 of the patent, wherein the substrate is formed on the substrate. Before the inner dielectric layer, it further includes forming a diffusion barrier layer on the substrate. 1 8 · The method for manufacturing a metal interconnect as described in item 7 of the patent application scope, wherein the diffusion barrier layer includes nitride One of the silicon layer and the silicon oxynitride layer-〇1 9 · The manufacturer of the metal interconnect as described in the scope of the patent application No. 丨 〇 554481 6. Method of applying for a patent, wherein after forming the inner gold layer dielectric layer on the substrate, the method further includes performing chemical mechanical polishing on the inner gold layer dielectric layer. 20. The method for manufacturing a metal interconnect as described in item 10 of the scope of patent application, wherein after forming the inner dielectric layer on the substrate, the method further includes performing chemical mechanical polishing on the inner dielectric layer. 2 1. The method for manufacturing a metal interconnect as described in Item 10 of the scope of patent application, wherein before the contact plug is formed in the contact window opening, the method further comprises: sputtering a titanium layer and a titanium nitride layer. ; And performing an annealing process. 9589twf.ptd Page 16