TW554476B - Method for forming an electronic device and display device - Google Patents

Abstract

A method for forming an electronic device, comprising: forming a first conductive or semiconductive layer; forming a sequence of at least one insulating layer and at least one semiconducting layer over the first conductive or semiconductive layer; locally depositing solvents at a localised region of the insulating layer so as to dissolve the sequence of insulating and semiconducting layers in the region to leave a void extending through the sequence of layers; and depositing conductive or semiconductive material in the void.

Description

554476 A7

This invention relates to a solution processing device and a method for forming the device. Semiconductor conjugated polymer thin film transistors (TFTs) have recently been applied to inexpensive, logic circuits integrated on plastic substrates (C Dru, Y, et al., Issue 73, APL, page 108, 1998), and are also used Yu Yu resolution active matrix display optoelectronic integrated device and pixel transistor switch. (Issued by H. Sirringhaus et al., No. 280, 8 (^ 11〇6, page 1741 and 1998.00) 3 丨 3 卩 11 "Appl_ Phys_ Lett, published by others in 1998, No. 73 (Page 142). In the test device configuration with polymer semiconductors and inorganic metal electrodes and gate dielectric layers, high-performance TFTs It has appeared. Compared with the efficiency of amorphous silicon TFTs, high-efficiency TFTs have reached charge carrier mobility of up to 0.1cm2 / Vs and on-off current ratio of ι〇6_ι〇8 (by H. Sirringhaus et al. Advances in Solid State Physics, Issue 39, 1999 (Page 101). Device-quality films of conjugated polymer semiconductors can be formed by coating a polymer solution in an organic solvent onto a substrate. This technology Therefore suitable for elasticity, Gel matrix is compatible with cheap, large-area solution processing. In order to take full advantage of cheap and easy processing technology, preferably, all components in this device, including semiconductor layers, dielectric layers, and conductive electrodes and interconnects The conjoined body is deposited from the solvent. In order to manufacture all-polymer TFT devices and circuits, the problems that must be overcome are as follows: 'This paper size applies the Chinese National Standard (CNS) A4 specification (21〇X 297 public love)

-------- ^ --------- · (Please read the notes on the back before filling out this page) 4 554476 A7 V. Description of the invention ($-the integrity of the multilayer structure: in During the subsequent solution deposition of the semiconductor, insulating or conductive layer, the underlying layer should not be dissolved or expanded by the solvent used to deposit in the subsequent layer body. If the solvent cannot be injected into the underlying layer, which will degrade the properties of the layer body Expansion will occur if the plutonium layer is used.-Two-resolution patterning of the electrode: The conductive layer must be patterned to form a well-defined interconnect and a TFT channel with a channel length u1O | Jm.-To manufacture a TFT Circuit, a vertical interconnect region (through-hole) must be formed to electrically connect the electrodes in different layers of the device. In WO99 / 10939 A2 patent application, a method for making U all-polymer TFT is disclosed. After the device, the layer is processed / constructed. The solution processing layer of the device is converted to an insoluble form. This method can solve the problem of dissolution and expansion of the underlying layer. However, it is serious Ground limits the available semiconductor materials The choice is to use only some of the unwanted precursor polymer groups. Furthermore, the interconnection of dielectric gate insulation layers makes it difficult to make through-holes through dielectric layers, so it is necessary to use, for example, mechanical perforations Technology (WO 99/10939 A1). According to the first aspect of the present invention, the device and method as described in the appended patent application scope are prepared. The independent patent application scope will also describe the preferred features of the invention. According to In one aspect of the present invention, a paper size application (CNS) A4 secret paper G x 297 is issued (please read the precautions on the back before filling this page). -Order ---------. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5 554476

5. Description of the invention (3) A method for crystals, comprising: depositing a first material from a solution with a first solvent to form a first layer of the transistor; and then depositing a second material from the solution with a second solvent. To form a second layer of the transistor; wherein the first material is substantially insoluble in the second solvent. Suitably, the at least one layer of the transistor is formed using inkjet printing (IJP). The layer may be a layer provided with an electrode of the transistor, such as a gate, a source, or a drain. Preferably, the method includes a method of forming an active layer of the transistor, forming an isolation layer on the active layer, and forming the transistor gate on the isolation layer. The isolation layer can be provided with a diffusion barrier and a surface modification layer, which will serve as a separate or the same layer body. According to a second aspect of the invention, a method is provided for limiting the deposition of a solution of a material onto a defined area on a substrate. The method includes patterning the surface of the underlying substrate to become regions with different surface free energy. The substrate can have water-repellent surface areas and other hydrophilic surface areas. Solution deposition can include inkjet printing methods, as well as methods for limiting the ink to areas of the substrate that are water repellent or hydrophilic. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Preferably, the pattern on the substrate will define the source and drain of the transistor, which preferably has a small channel length of L < 20pm, and the gate and source therein. Pole / non-pole presentation has defined overlap and has interconnections According to the third aspect of the present invention, a through hole is provided to define the electrical connection between electrodes and interconnects in different layers. This paper is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) 6 554476 Λ7 V. Description of the invention (7)-A semiconductor layer having a high on-off current conversion ratio exceeding the charge carrier mobility and exceeding 104. -A thin gate insulation. A diffusion barrier layer which protects the semiconductor layer and the insulating layer from accidental doping caused by the diffusion of impurities and ions. -A surface modification layer, which uses printing technology to achieve high-resolution prototyping of the gate. -Vias to the interconnect through the dielectric layer. However, what is desired is that the method described here is not limited to a method of manufacturing a device having all of the features described above. A method of manufacturing the first exemplary device will now be described with reference to FIG. The device in Figure 1 is a thin film field effect transistor (TFT), which is configured to have a top gate structure. On top of the cleared 7059 glass substrate 1, the interconnects between the source-drain electrodes 2 and 3 'and the electrodes and contact pads (not shown) will use inkjet printing to deposit an aqueous conductive polymer polyethylene. A solution of dilute dioxythiophene / polystyrene sulfonic acid (PEDOT (0.5 weight ratio) / PSS (0 8 weight ratio)). Other solvents such as methanol, ethanol, isopropanol or acetone can be added to affect the surface tension, viscosity and wetting properties of the ink. PEDOT / PSS can be obtained commercially from Baye "company (such as " Baytron P "). The jp printer is a piezoelectric type. It has a precision 2D conversion stage and a micro stage, which enables subsequent printing The samples can be aligned with each other. 丨 JP print head uses voltage pulse

Please read it first, read the back, pay attention to the stupid things, and then fill in. 装 Page I Order Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs

10 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 554476 Λ7 _______ B7 V. Description of Invention (g). At 20V pulse chirp, when the rise time is ιμ3 and the fall time is 10Ms, an appropriate driving condition for injecting a typical solid content of 0.4ng per drop can be achieved. After drying on a glass substrate, they will produce PEDOT dots with a typical diameter of 50 μm and a typical thickness of 500 A. The source-non-polar IJP takes place in the air. Thereafter, the sample is transferred to an inert gas drying cabinet. The substrate will then be spin-dehydrated in an organic solvent which will then be used to deposit the active semiconductor layer, such as mixed xylene in a polymer. They are then annealed in an inert nitrogen gas at 200 ° C for 20 minutes to remove residual solvents and other volatile substances from the PEDOT / PSS electrode. Subsequently, a 200-1 000 A thick film of the '4 active semiconductor polymer 4 will be deposited using a spin coating method. A number of different semiconducting polymers have been used, such as ortho-oriented poly-3-ethylpyrene (P3HT), and polyfluorene copolymers such as poly-9,9.-dioctylpyrene-dithiophene (FBT2). FBT2 is a better choice because it can exhibit good stability in the air when the gate electrode is deposited in the air. A 5-10 mg / m FBT2 solution in anhydrous xylene (commercially available from Romi) was spin-coated at 1500-2000 rpm. In the case of P3HT, a solution having a weight percentage of 1 in xylene will be used. The underlying PEDOT electrode is not soluble in non-polar organic solvents such as diphenylbenzene. The membrane body is then subjected to spin-drying in a solvent, such as isopropanol or methanol, which will be used later for the deposition of the gate insulating layer 5. (Please read the precautions on the back before filling this page) γ Zhuangyi -------- Order ---------

11 554476 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the Invention (9) The subsequent annealing step will be performed subsequently to improve the charge transport properties of the semiconductor polymer. For polymers that exhibit a liquid crystal-like phase at high temperatures, annealing at a temperature higher than the liquid crystal-like transition will cause the polymer chains to be parallel to each other. In the case of F8T2, the annealing process is performed in an inert n2 gas at 285 ° C for 20 minutes. The sample will then be quickly cooled to room temperature to freeze the chains and produce an amorphous glass. If the sample is prepared on a flat glass substrate without an alignment layer, the polymer will adopt a multi-domain configuration in which multiple liquid crystal-like domains with random orientations will be located in the TFT channel. Using the cooling from the liquid crystal phase to prepare a transistor device in which the F8T2 is in the vitrified state, it will show a level of fluidity of 5 10 3cm2 / Vs, which will not only be higher than that measured on a device with a rotating F8T2 film Liquidity is an order of magnitude. The deposited device simultaneously exhibits a higher turn-on voltage v0. This will be attributed to the lower density of the pseudo-domain electron complement states in the vitrification phase, compared to the partially crystalline deposition phase. If the polymer is formulated in a single domain state with uniaxial adjustment of the polymer chain parallel to the transistor channel, a further improvement in fluidity can be obtained by a typical 3-5 factor. This can be achieved by coating a glass substrate with an appropriate adjustment layer, such as a mechanically rubbed polyimide layer (9 in Figure 1 (b)). In the single domain state, the polymer chains are aligned uniaxially in a rubbing direction parallel to the underlying polyimide layer. This will lead to a re-human enhancement of the charge carrier mobility in the device, which "adjusts the direction of the channel parallel to the chain. This process will be modified in the pending British patent application 9914489.1

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V. Description of the Invention (Printed in 554476 by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Detailed description. After the semiconductor layer is deposited, the gate insulating layer 5 is spin-coated with a polar solvent of polyalkylene styrene (also known as polyethylene Phenol (PVP)), in which the underlying semiconducting polymer is insoluble. Preferred solvents are alcohols, such as methyl, 2-propanol, or butanol, where, for example, FBT2 non-polar polymer has Unexpectedly low solubility and does not swell. The thickness of the gate insulation layer is between 300nm (solution concentration is 30mg / ml) and 1-3Mm (solution concentration is 100mg / ml). It can also be used to meet the solubility Other insulating polymers and solvents required, such as water-based polyvinyl alcohol (PVA) or propylene glycol ethyl acetate poly-isobutylene methyl ester (ρMMA). Gate 6 will then be at the gate Deposited on the gate insulation layer. The gate insulation layer can be deposited directly on the gate insulation layer (see Figure 1 (c)), or for example due to surface modification, diffusion barriers or process factors such as solvent compatibility, etc. Can have a layer or Layer (see Figure 1 (a) and (b)) 〇 In order to form the simpler device in Figure 1 (c), the PEDOT / PSS gate 6 can be printed directly on top of the PVP insulation layer 5 The substrate will be converted to the IJP station in the air again, where the PEd〇t / pss gate pattern will be printed from an aqueous solution. The underlying pvp gate insulation layer has low solubility in water to make the gate dielectric The integration is retained during the printing process of the PEDOT / PSS gate. Although pvp contains high-density polar hydrocarbon groups, its solubility in water is low due to the relatively non-polar polystyrene backbone. Figure 2 shows This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page)

13 554476 A7 V. Description of the invention (^ It has a FBT2 semiconductor layer, a pvp gate insulation layer and 丨 Jp PEDOT / PSS source-drain and gate switching characteristics. Jp TFT. The characteristics of this device are under nitrogen Measurements are performed continuously. Continuous measurements will show gate voltages that increase (upward triangle) and decrease (downward triangle) respectively. This feature belongs to the batch with the new configuration and the PEDOT / PSS (Baytron P) batch one year ago. The device is made. However, the action of the transistor is clearly visible, and the device will present an unusually normally open state with a fixed positive voltage V0> 10V, and the evaporated gold source-drain and gate The reference device made of the pole will show a normally closed state (V0 < 〇). In the device formed with PEDOT (Figure 2 (b)), • a year ago " a large hysteresis will be observed Effect, which will be attributed to the high concentration of mobile ionic impurities (see below). If the sweeping action starts in a very empty state (Vg = + 40V), the transistor will be at Vfoe + 20V (upward triangle) On. However, in the opposite sweep action (toward Triangle), the transistor is only turned off at Vr0 > + 35V. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs due to the diffusion of ionic substances in one layer of the device, usually the on state and hysteresis effect may occur. Usually A large positive value of V. implies that the ions are negative. A positive material can be expected to compensate for some of the moving charges in the accumulation layer and convert V. to a value that is more negative. In order to identify the source of the ionic material, Manufacturing device in which the top gate IJP PEDOT is replaced by an evaporated gold electrode, while other layers and PEDOT source / drain are manufactured as described above. It has been found that in this configuration, the device is normally closed The paper size is stable and the paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm). 14 554476 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of invention (limited voltage. This will It is implied that the doping and hysteresis effects in all-polymer devices will be related to the solution deposition of the conductive polymer top gate, and the movement in the PEDOT solution / film, Impurities may diffuse to the underlying layer of the device. It has been found that by depositing gates on the heated substrate, it may be possible to control the value of the fixed voltage and reduce the hysteresis. This will reduce the droplets on the substrate. Drying time. Figure 3 (b) shows the switching characteristics of a TFT device, in which the substrate will be heated to a temperature of 50 ° C during the deposition of the gate. It can be seen that the hysteresis effect will be much smaller than at room temperature The gate electrode (Figure 3b), and V. has a relatively small positive value of 6V. By controlling the deposition temperature, the fixed voltage can be adjusted in the $ color range of V0 = 1 -20V. As shown in Fig. 1 (C), the device having a gate electrode directly deposited on the PVP layer is an empty type. For empty-type logic circuits, such as simple empty-load logic converters (Figure 14 (a)), the on state is usually useful. In order to make enhancement-type TFTs are usually turned off, during the deposition of the gate, the semiconductor barrier can be avoided by incorporating a diffusion barrier layer. In the device of Figures 1 (a) and (b), a non-polar polymer will be deposited on top of the pVp gate insulation layer before the conductive polymer gate is deposited. This layer can act as a diffusion barrier to hinder the diffusion of ionic substances into the moderately polar PVP insulator. PVP contains a high density of polar hydrocarbon groups that will easily enhance the conductivity and diffusivity of ionic conduction and diffusion into the film. Several non-polar polymers have been used. The paper size applies to Chinese National Standard (CNS) A4 (2K) x 297 mm (Please read the precautions on the back before filling this page)

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V. Description of the Invention (Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, such as poly_9,9'_dioctylgolfate (F8), polystyrene (PS), poly (9,9 · -dioctyl 芴 ·· Co-N- (4-butylphenyl) diphenylamine) (TFB) or F8T2. 50-100nm grade polymer films can be deposited from a solution of a non-polar organic solvent such as xylene on PVP gate insulation On the surface of the layer, PVP is insoluble. It has been found that it is problematic to print PEDOT / PSS directly on top of the non-polar diffusion barrier layer from an aqueous polar solution because of the poor wetting properties and large contact angles. To solve this problem, the 'surface modification layer 8 will be deposited on top of the non-polar polymer. This layer provides a hydrophilic surface instead of a water-repellent surface, on which PEDOT / PSS can be formed more easily. This will High-resolution printing of gate patterns is allowed. In order to form a surface modification layer, a thin layer of PVP can be deposited from an isopropanol solution, wherein the underlying diffusion barrier layer is insoluble. The thickness of the PVP layer is preferably less than 50nm. South resolution of PEDOT / PSS printed on PVP table It is possible. Alternative surface modification layers can also be used. This includes thin layers such as soap-like surfactants, or polymers containing hydrophilic and water-repellent functional groups. These molecules will tend to separate the phase from water-repellent and hydrophilic groups, They are attracted to the interface between the non-polar polymer and the blank surface. Another possibility is that the surface of the non-polar diffusion barrier will be exposed to a mild 02 gas, making the surface hydrophilic. If the gate The electrode is printed from a solvent that is less polar than water, such as formulas containing alcohols (isopropanol, methanol, etc.). The surface modification layer on the non-polar diffusion barrier may not be required. This paper size is applicable to China Standard (CNS) A4 size X 297 mm) (Please read the notes on the back before filling this page) I— I -------- ^ --------- Jan 16 554476 A7 ^ ^ -ill ___

V. Description of the invention (The integration of the layer A sequence will depend on the alternate deposition of polymer materials from polar and non-polar solvents. What is desired is that the solubility of the first layer in the solvent deposited for the second layer will be less than 0_1 weight percent per volume, preferably less than 0_01 weight percent per volume. At the same time, the difference in the Hildebrand solubility parameter is desired, which is between the material of the first layer and the solvent used to deposit the second layer. The qualified polarities between them will be as large as possible (Properties of Polymer published by DW van Krevelen in Elsevier, Amsterdam, 1990). For some device configurations, the polymer replacement sequence can be used to create a full multilayer structure The polymer mainly contains polar groups and is soluble in highly polar solvents such as water, and polymers that contain only some or no polar groups and are soluble in non-polar solvents such as diphenylbenzene. One example is electricity Crystal device containing a highly polar source-drain of PEDOT / PSS, such as a non-polar semiconductor layer of fBT2, such as polyvinyl alcohol deposited from water A highly polar gate dielectric layer, a TFB non-polar diffusion barrier layer that can also be used as a buffer layer to allow layered deposition, and a Pedot / PSS gate. However, it is also possible to build a layered sequence that contains a clip A moderately polar polymer layer deposited between a highly polar and a non-polymeric polymer layer and deposited from a moderately polar solvent. A moderately polar polymer is a polymer that contains polar and non-polar groups and is essentially It is insoluble in a highly polar solvent. Similarly, a moderately polar solvent contains polar and non-polar groups, but is essentially insoluble (please read the precautions on the back before filling this page)

Packing -------- Order --------- Line I Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs

17 554476 A7 B7 V. Description of the invention (imitating a non-polar polymer. The moderately polar polymer may also contain a specific functional group, such as a hydrocarbon group, which causes it to be dissolved in a solvent containing a functional group, and the Functional groups will be attracted to the polymer. The functionality of the polymer can be used to increase the solubility in moderately polar solvents and reduce the solubility in polar solvents. One example of a moderately polar polymer is a PVP gate A polar dielectric layer sandwiched between a non-polar semiconductor layer and a PEDOT / PSS gate electrode layer (Figure 1c). An example of a moderately polar solvent is an alkanol. Figure 4 shows a PVP gate insulating layer The output end (a) and conversion characteristics (b) of the all-polymer F8T2 IJP TFT of F8 diffusion barrier layer and PVP surface modification layer, as shown in Figure 1 (a) (L = 50 / Jm). This device Presents a clean, nearly ideal, normally off transistor action, which is turned on at v0 ^ ov. The fixed voltage between the upward (upward triangle) and downward (downward triangle) voltage sweep action is converted to yv. This Features of the device are quite similar Manufactured in an inert gas environment and has the characteristics of a standard device of gold source-drain and gate. The level of field effect fluidity is 0.005_0.01cm2 / Vs, and measured between Vg = 0 and -60V The on / off current ratio is 10 ^ 1 〇5. The device has been manufactured to have a wide range of non-polar diffusion barrier layers, such as FB, TFB (Figure 5 (a) shows the conversion characteristics), ps (5 (b ) Shows switching characteristics) and FBT2. In each case, you will observe clean and normally closed conditions, small hysteresis effects, and fixed voltage switching, which are of the same weight class as a reference device with a gold source-drain. This will support the solution deposition process of the gate insulation layer and thereafter, in the paper of the gate electrode (CNS) A4 secret Q χ 297 public love. Please read-read, memorize

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 18 554476

V. Description of the invention (Your data analysis of the insertion of non-polar polymers that will block the diffusion of ionic impurities. It has been found that it will produce a reproduced TFT threshold voltage and a good operation qualitative. A normally closed device including a diffusion barrier is better compared In the above-mentioned empty-type device, the former has been expected to exhibit a longer time-limited voltage stability and longer life because ion diffusion has been suppressed. For the semiconductor layer, any treatable conjugated polymer can be used Or a solution made of a polymer material, which exhibits sufficient field effect fluidity in excess of 10-3 cm2 / Vs, preferably in excess of 10 2 cm2 / Vs. Appropriate materials will be tested in examples, such as by Η · Ε · Katz and J_ Mater, No. 7 Chem., P. 369, published in 1997, or pp. 227, No. 12 Advanced Materials, published by Ze Bao in 2000. Printed by the Intellectual Property Bureau, Ministry of Economic Affairs, Consumer Consumption Cooperative One of the important requirements for printing TFTs with good stability and high on-off current ratio is the good stability of the semiconductor material, which can resist oxygen and oxygen during processing and printing steps. Unintended doping of water. Various semiconductor polymers have been used to make printed TFTs as active semiconductor layers, such as FBT2 (see above), or normal orientation deposited from a mixed xylene solution, P3ht. In terms of P3HT For TFTs configured in a test device configuration under inert gas, the field effect fluidity of 0_05-0.1cm2 / Vs is slightly higher than that using F8T2. However, for oxygen or water doping, it is normal Orientation P3HT is unstable, which will cause the paper size in the printing step to apply the Chinese National Standard (CNS) A4 specification ⑵0x297 public meal) '------- 19 554476 V. Description of the invention (for and Poor switching current compared to the increase in membrane conductivity. This is related to the relatively low ionization potential of P3HT, W9ev. The high on-off current ratio of less than 106 has been shown for P3HT, but after deposition is required, reduction is required The step of removing doping is, for example, exposure to a hydrazine-based gas (Issue 39, Solid State Physics, p. 101, published by Sir Sirhaus et al., 1999. However, on the aforementioned | jp TFTs, this Processing steps after reduction cannot #, Because it will simultaneously lead to the de-doping of the PEDOT electrode and greatly reduce its conductivity. Therefore, in order to achieve a high current conversion ratio, it is important to use unintentional doping that resists oxygen or water. A polymer semiconductor with stability. A better type of material to achieve good environmental stability and high fluidity is AB hard needle block copolymer, which contains a normal grade sequence of eight and eight blocks. Suitable A block It is a stepped part with a well-defined structure and a high band gap. It has a high ionization potential higher than 55 eV, as a homopolymer and good environmental stability. Examples of suitable A-blocks are Gou derivatives (U.S. Patent No. 5,777,07), indene derivatives printed by the Consumer Cooperatives of the Intellectual Property Office of the Ministry of Economic Affairs of the Indene (No. 33 published by S_Setayesh in 2000) Macromolecules, 2016), phenylene or trapezoidal phenylene derivatives (No. 7 Adv., 1995, published by J. Grimme et al.

Mat, p. 292). Suitable β-blocks are pore-transporting portions' with low band gaps which contain heteroatoms, such as sulfur or nitrogen, and are homopolymers with ionization potentials below 5.5 eV. Examples of pore-transporting beta agglomerates are plugged with 1% bamboo organisms or diphenylamine derivatives. The utility of the block B is 297 mm.) This paper size is applicable to the Chinese National Standard (CNS) A4 specification (2) 0 20 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 554476 Λ7------— ~ — — B7 ___ V. Explanation of the invention (仂 Decrease the ionization potential of the block copolymer. The ionization potential of the block copolymer is preferably within the range of 4.9eV and 5.5ev. An example of this copolymer is F8T2 (the ionization potential is 5 5eV) or TFB (U.S. Patent No. 5,777,070) 〇 Other suitable pore-transporting polymers are homopolymers of polyisophene derivatives with ionization potentials greater than 5eV, such as polyfluorene with fluorinated oxygen or fluorinated side chains (No. 10 Advanced Materials, published by RDMcCullough, 1998, page 93). In addition to hole-transporting semiconductor polymers, soluble electron-transporting materials can also be used. This requires a high electron affinity of greater than 3eV, preferably Greater than 3.5eV to avoid residual gas impurities such as oxygen from being captured as a carrier. Suitable materials may include solutions that can process small molecules of electron-transporting electrons (issued by Η · Katz et al., No. 404 Nature 2000) Magazine 478 pages) Or polythiophene derivatives with incompletely fluorinated side chains of electrons. AB-type block copolymers with a well-defined trapezoidal octave block and a high ionization potential higher than 5_5eV 'and increase the electrons of the copolymer For an electron-transport B block having an affinity to a value higher than 3 eV, preferably higher than 3.5 eV is also suitable at the same time. Examples of suitable A blocks are fluorene derivatives (US Patent No. 5,777,070), indeno芴 Derivatives (No. 33 Macromolecules, 2000 by 3.3613, Yap 63, 2000, p. 2016), phenylene or trapezoidal phenylene derivatives (No. 33 by j_ Grimme et al., 1995 7th issue Adv_ Mat · page 292). An example of the electron transport B block is a benzothiadiazole derivative (U.S. Patent No. This paper size applies Chinese National Standard (CNS) A4 specifications (2) 0 X 297 public ^) ^ Μ. -------- (Please read the notes on the back before filling this page) 21 554476

V. Description of the invention (Visit 5,777,070), Perylene derivatives, Naphthalene tetracarboxylic acid diamidine derivatives (Na | published by Η E · Katz in 2000; ure404 Issue 478 pages) or fluorine Thiophene derivatives. To operate logic circuits quickly, the channel length of the transistor and the overlap between the source / drain and gate should be as small as possible, which is typically a few microns. The most important dimension is L because the operating speed of the transistor circuit is about a ratio of L 2. This is especially important for semiconductor layers with relatively low fluidity. Even today's inkjet printing technology cannot achieve high-resolution prototyping. 'Even JP technology, which has the state-of-the-art technology, is limited to 10-20Mm external dimensions (Figure 6). If faster operations and denser appearance packaging are needed, then a technique that allows finer appearance resolution must be used. The technique described below will use the interaction of the ink surface to define inkjet droplets on the substrate surface. This technique can be used to achieve smaller channel lengths than can be achieved with conventional inkjet printing methods. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs This limited technology can be used to allow a high resolution deposition of a deposition material on a substrate. The surface of the substrate is first treated so that selected portions thereof are relatively attractive and relatively waterproof to the desired deposition material. For example, the matrix can be patterned in advance so that it is partially water-repellent in some areas and partially hydrophilic in other areas. Due to the high-resolution and correct-reading pre-modeling steps, subsequent depositions can be correctly defined. An example of prior patterning is shown in FIG. 7. Figure 7 This paper size applies the Chinese National Standard (CNS) A4 specification (2) χ 297 public love 22 554476 V. Description of the invention (printed and displayed by employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Oil Economy, Figure 1 (c) The formation of the same device, but with a particularly thin channel length. Identical components are represented by the same numbers as in Figure 1 (c). Figure 7 (a) shows a square vector for making a pre-patterned substrate Figure 7 (b) shows the printing method and ink definition on the pre-patterned substrate. Prior to the deposition of the source electrodes-electrodes 2 and 3, a thin polyimide layer 10 will be formed on the glass sheet. 1. The polyimide layer is excellently patterned to remove it where the source-drain is formed. The removal step can be done by a photolithography process to allow excellent The appearance is defined and correctly read. In an example of this process, polyimide can be covered with a layer of photoresist material. The photoresist material can be patterned by photolithography to collect Remove the imine where it was removed. Next, use a This is a robust process that removes polyimide from the photoresist material. The photoresist material can then be removed to leave the polymorph imine properly shaped. Polyimide will be selected because it is Relatively water-repellent, and the glass substrate is relatively hydrophilic. In the next step, the PEdot material forming the source-drain will be deposited on the hydrophilic substrate region 12 by inkjet printing. When the expansion is in When the ink droplets in the glass substrate area touch the edge of the water-repellent polyimide area 10, the ink will be discharged and will not flow to the water-repellent surface area. Through this limiting effect, the ink is only in the hydrophilic surface area Deposited, high-resolution patterns with small band gaps and transistor channel lengths of less than 10 μm can be defined (Figure）). After the polyimide is removed, the polyimide is removed. The paper size of the paper in the process of division is subject to the Chinese National Standard (CNS) A4 specification (2) 0 X 297 mm 23 554476 A7 B7 V. Description of the invention (2i example, or it can be applied to improve the relative surface effect, will Shown in Figure 7 (a) .Polyimide layer 1 The photoresist material 11 will be exposed to oxygen. Oxygen will etch a thin polyimide layer (500 A) faster than it will etch a thick (1_5μηι) photoresist material layer. Before removing the photoresist material, borrow By exposure to oxygen, the exposed glass surface 12 in the source-drain region will be quite hydrophilic. It should be noted that during the removal of polyimide, the surface of polyimide is The photoresist material protects and maintains water resistance. If necessary, the surface of the polyimide can be made more water-resistant by additional exposure to CF4 gas. The cf4 gas will fluorinate the surface of the polyimide, but not Interaction with hydrophilic glass substrate. This additional gas treatment can be performed before removing the photoresist material, so that only the side wall of polyimide type 10 will be fluorinated, or the After the photoresist material. The contact angle between PEDOT / PSS in water and 0 2 plasma-treated 7059 glass is 0 glass »20 °, compared to a contact angle of 0 PIW0 ° to 80 ° on the surface of polyimide. The contact angle of PEDOT / PSS with fluorinated polyfluorene imine in water was 120. . Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. As described, when PEDOT / PSS is deposited from an aqueous solution onto a previously patterned polyimide layer, PEDOT / PSS inks will be limited to source-drain Polar region, even if the channel length L is only a few microns (Figure 7 (b)). The definition of ink droplets depends on the contact angle 0 between the edge of the water-repellent surface and the hydrophilic surface area, and will be related to the air / paper size applicable to the Chinese National Standard (CNS) A4 specification (2) 0 X 297 mm ) 24 554476 A7 B7 V. Description of the invention (佥 The interfacial tension of polyimide and the ink / glass interface printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs □ 1 and port 2 and the surface tension port of the ink / air interface 3. Ignoring the effect of polyimide sidewalls-an estimated value will be obtained from Young's formula cos 0 = (port 1_port 2) / 匚) 3 (Figure 7 (b)). Preferably, the deposition of the 'ink droplets 13 will occur on the hydrophilic matrix region 12, a distance d between the center of the droplets and the margin of the polyimide. On the one hand, d must be small enough to reach the edge with extended ink, and the PEDOT film will extend directly to the edge of the polyimide. On the other hand, d must be large enough so that the rapidly expanding ink does not overflow into the water-repellent surface area. This will increase the risk of PEDOT deposition on top of the polyimide region 10 defining the TFT channel 'and will cause a short circuit between the source and the non-electrode. For PEDOT droplets with a solid content of _ 4 ng between two consecutive droplets with a lateral pitch of 12_5 μηι, deposited on 7059 glass treated with 〇2 gas plasma, a fraction of 〇ι »30 · 40μηι The values are already suitable. The optimum value d depends on the wetting properties on the surface, but also on the deposition pitch, which is the lateral distance between subsequent deposited droplets, and on the drying time of the solution. The polyimide layer 10 can be simultaneously used as the adjustment layer 9 (Fig. 1 (b)) 'in the example of the liquid crystal-like semiconductor polymer 4. Polyimide layer can be rubbed mechanically. The gate electrode 6 can be similarly defined by a patterned layer 14 formed on top of the gate insulating layer 5, which provides an attractive and evacuated surface area for the solution deposited by the gate electrode. The patterning layer 6 can be applied to the Chinese National Standard (CNS) A4 specification (210 X 297 public love) at this paper size (please read the precautions on the back before filling this page) -------- Order— — — — —--- I-25 554476

Description of the Invention (Use source-drain pattern adjustment to minimize the overlap between source / drain and gate (Figure 7 (c)). Materials other than polyimide can also be used It can also be used in other pre-modeling techniques other than photolithography. Figure 8 shows the structural ability of relatively water-repellent and hydrophilic layers to limit the liquid deposited by inkjet printing. Fig. 8 shows a light micrograph of a substrate containing elongated polyimide 10, which has been treated as described above to become relatively water-repellent, and makes a bare glass substrate treated as described above. The larger area of 12 becomes relatively hydrophilic. The source and drain of the pedqt material have been deposited using inkjet printing, which is a series of droplets flowing in lines 2 and 3 close to the strip 10. Although it has been sprayed The ink material will show a low contrast, as can be seen from the canine end forms of the end surfaces 2 and 3 of the deposition material, the deposition material has been defined by the strip 10, even if the thickness of the strip is below L = 5pm Figure 9 shows strips of polyimide 1 〇 Photograph of the inkjet deposition process of the surrounding area. The image will be taken with a stroboscopic camera fixed below the transparent substrate. Polyimide pattern 10 has white lines at the edges. Ink droplets 21 from the nozzles of the inkjet head 20 Injection, and stay at the center of distance d from the polyimide stripe 10. Images like this can be used to adjust the correct area for inkjet deposition of the stripe pattern 10, and can It is used to automate the area adjustment procedure using pattern recognition (please refer to the description below). Figures 10 and 11 show that they are formed as shown in Figure 7 (c) and the paper dimensions are applicable to the Chinese National Standard (CNS) A4 specifications ( 210 X 297 mm) (Please read the precautions on the back before filling out this page), -------- Order --------- line System 26 554476 A7 ^^ ----- ~ __ V. Invention ^ The output and conversion characteristics of the transistor with a channel length of L = 20pm and 7μηι are defined by the differential wetting process described above. In the two cases , The channel width W is 3mm. Figure 10 (a) shows 20μΓη Figure 10 (b) shows the output characteristics of a 7μηι device. Figure 11 (a) shows the conversion characteristics of a 20μΓη device. Figure 11 (b) shows the conversion characteristics of a 7μπ device. The 7μηι device It shows a characteristic short-channel state with reduced current at the small source-electrode voltage, and a limited output conductivity in the saturated state. The short-channel device's mobility and on / off current ratio will be similar to the above-mentioned long channel. The fluidity of the device is compared with the on-off current ratio, that is, μ = 0.005 · 0001cm2 / Vs, and 丨 on / Iff = 104-105. An alternative technique for manufacturing a matrix pre-type is to have a type Functionalization of the surface of glass substrates of self-assembled monolayers (SAM), such as SAM, which contains a hydrophobic alkyl or fluoro group such as tri-fluoroacetic acid_tri-methoxysilane, or a polar group such as alkoxy base. SAM can be modeled using appropriate methods, such as exposure to UV light through a shadow mask (printed by Η. Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs

Suginrujra et al., Langmuir 2000, p. 855, 2000), or microcontact printing (May 1998, Physics World May, p. 31, by Brittain et al., 1998). The substrate pre-patterning is compatible with the above process flow, because the pre-patterning is performed before the layer deposition of the TFT. Before the gate is deposited, a similar technique can be used to pre-type the surface of the gate insulation layer or the surface modification layer to achieve a small overlap capacitance. As shown in Figure 7 (c), the gate electrode 6 can use a patterning layer. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (2〗 〇297 × 297 mm) 27 554476

V. Description of the invention (limited to 14). One possible embodiment of the pre-type prototype is a micro-contact printing method or a UV-type prototype of a self-assembled monolayer, which includes a hydrocarbon group bonded to a pvp gate insulating layer. Gas silane or methoxysilyl group. Because it has a pre-shaped substrate, it is possible to manufacture high-speed logic circuits according to the TFT and through-hole manufacturing process disclosed in the present invention. Fabrication of transistor circuits on a large area One of the important requirements is to record and adjust in contrast to the deposition of the matrix pattern. It is particularly difficult to make sufficient records on the elastic matrix, because distortion will appear over a large area. The high-resolution inkjet developed here The printing process will be suitable for correct recording over a large area, even on a plastic substrate, because the position of the inkjet print head can be locally adjusted relative to the pattern on the substrate (Figure 9). This local adjustment process can The pattern recognition technology is used to automate the process, which uses the image shown in Figure 9. In order to use the above-mentioned device to form a multiple transistor volume body circuit, what is desired is to be able to directly pass through the device. Thickness to make through-hole interconnects. This allows the circuit to be formed particularly tightly. One of the methods of making this interconnect is to use vias made with solvents, as explained below. This method uses the TFTs described above The fact that the solution processing layer has not been converted into an insoluble form. This can form the opening of the through hole by local deposition of the solvent. In order to make the through hole formed by the solvent (Figure 12 (a)), the quantitative and appropriate The solvent 29 will be locally deposited on the top of the layer, and through-holes will be formed through the top. The solvent is selected so that it can dissolve the underlayer, and the through-hole can be formed through the underlayer. The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (2) 0 × 297 mm. (Please read the precautions on the back before filling this page) Μ -------- ^ ------ ---- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

I 28 554476 V. Description of the invention (Oil method, the solvent will penetrate the layer until the through hole is formed. The dissolved material will be deposited on the wall of the through hole w. The type of the solvent and the method of deposition can be based on individual However, the three better choices are: 5 · 1 · Solvent and process conditions are solvents that will evaporate or can be easily removed so that they will not interfere with subsequent processing and will not cause the device to Excessive or incorrect dissolution; and 2. Solvent deposition through a selective process, such as | Jp, where the correct solvent control amount can be applied correctly to the desired area of the substrate; and 3_ through hole diameter Will be affected by the surface tension of the solvent droplets and the solvent's ability to wet the substrate; and 4. The solvent cannot dissolve the underlayer, which is where the electronic connection occurs. Printed by the Consumer Cooperative of the Intellectual Property Bureau, Ministry of Economic Affairs, Figure 12 (A) Shows the deposition of droplets 29 of methanol solvent (each droplet contains 20ng) on a transistor device formed as part of the general type in Figure 1 (c). Partial device in Figure 12 (a) Contains thick PVP insulating layer 28, F8T2 semiconductor layer 27, PEDOT electrode layer 26, and glass substrate 25. In this example, it is desired to form a through hole through the insulating pVp layer. Methanol was chosen as the solvent because it easily dissolves pvp Because it can be easily evaporated, it will not hinder the subsequent processing; and because it is satisfactory for the wetting properties of PVP. In order to form a through hole in this example, a Jp print head is moved to the substrate On the position 'It is the position where the through hole is intended to be formed. Then, from this paper standard, China National Standard (CNS) A'l specification (21〇X 297 public love 29 554476)

Please read the notes on the back side ▲ Read and complete this page Binding 554476 A7

V. Description of the invention (small oil through-holes will also be required, such as high-resolution displays, which can use smaller droplet sizes, or the surface of the substrate can be pre-shaped by an appropriate technique to limit the surface Droplets, as described above. Other solvents can also be used. It can be seen from the surface profile measurement that the formation of through holes will cause the material to dissolve and be shifted to the edges of the through holes, where the solvent has evaporated Will be maintained (shown in w in Fig. 12 (b)). It should be noted that the formation of the offset material is smoother than that shown in Fig. 12 (b) and the 12 (b) outline The X and y axes in the figure will be dissimilar scales (the unit of X is " and the unit of y is A). Using the number of dripping solvent droplets and comparing the evaporation speed of the solvent with the speed of dissolving the matrix The combination can control the depth of the through hole. The environment and substrate temperature generated by the deposition may affect the evaporation rate. The material layer that does not dissolve or only slowly dissolves in the solvent will be used to limit the depth of dissolution. Because the layer sequence of the TFT includes replacement Polar and non It is possible to select a mixture of solvents and solvents so that the engraving of the surname stops at a well-defined depth. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In order to make contact through the through hole, a conductive layer can be deposited On it so that it extends into the through hole and the material is electrically connected at the bottom of the through hole. Figure 13 (a) shows the device of Figure 12 (a), but does not include manufacturing in the through hole as described above The gold electrode 25 formed later. Figure 13 shows the curve 30 between the bottom PEDOT electrode 25 and a conductive electrode 29 deposited on top of the PVP gate insulating layer 28. This paper applies Chinese National Standard (CNS) A4 Specifications (2) 0 × 297 mm 31 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 554476 A7 ------- B7 V. Description of the invention (characteristics of the measured current and voltage. The diameter of the through hole Is 50 μηι. For comparison, curve 31 shows a reference sample in which there are no through holes in the overlap between the top and bottom of the electrode. This feature clearly shows that in the absence of through holes, The current through the via will be several times higher than the leakage current through the gate insulator. With the conductivity of the PEDOT electrode, the measured current through the via is limited, as seen in the conductivity measurements of individual PEDOT electrodes It is not limited by the resistance of the via, so that a lower limit estimate of the via resistance Rv can be obtained from these measurements: Rv < 500kQ. The above is related to the via formation of Figure 12 The method will be directly applicable to empty-type devices without diffusion barriers (such as the first (magic) and devices without diffusion barrier deposition after the vias are opened. Figure 14 (a) shows that vias have been formed And a gate is then deposited without an intermediate diffusion barrier. Fig. 4 (b) shows a similar device in which a diffusion barrier polymer 7 has been formed after the formation of the through hole and before the deposition of the gate electrode 6. In this case, the 'diffusion barrier layer needs to exhibit good charge transport properties in order to minimize the through-hole resistance Rv. A suitable diffusion barrier is a thin layer TFT, as shown in Figure 5 (a). If a lower contact resistance is required, then the semiconductor layer will also be removed at the location of the via. After the formation of the diffusion barrier, it can be done better. The diffusion barrier 7 and the semiconducting polymer 4 can be locally dissolved by using a good solvent IJP deposition. For example, in this example, the paper size applies the Chinese National Standard (CNS) A4 specification (2) 0 X 297 g t. (Please read the back first (Notes for filling in this page)

P installed -------- order --------- line I 32 554476 A7

Medium is xylene. By mixing an excellent solvent for the semiconductor and the insulating material, the two-layer body can be dissolved at the same time. Figure 14 (c) shows a device that performs the above process following the deposition of the gate. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. By increasing the contact angle of the pre-dissolved solvent mix on the layer, the solvent mix can also be used to reduce the radius of the through hole. An alternative method of forming through-hole interconnects and subsequently depositing conductive materials for bridging is to locally deposit a material that locally modifies the underlying substrate so that they become conductive. One example is localized Jp deposition of a solution containing mobile doping, which can diffuse into one or more layers. This is shown in Figure 14 (d), where region 32 shows a conductive material treated with a dopant. The delta dopant may be a small molecule, such as n, n diphenyl-N, N -bis (3-methylphenyl)-(1,1 ·· biphenylbu 44, · diamine (Butyl pD) diarylamine. The dopant is preferably transported in a solvent state. The method of forming through holes through the PVP dielectric layer can be used to connect the gate of the TFT to the underlying body. Source or sink, for example, a logic converter device as shown in Figure 15. In most logic transistor circuits, a similar via connection is required. Figure 6 shows two normally closed The characteristics of the enhanced and loaded converter device formed by a transistor device. Two converters with different channel width to channel length ratio (W / L) of two transistors will be displayed (Figure 35 is a 3 M ratio, Figure 36 is a 5: 1 ratio. It can be seen that when the input voltage is switched from a logic low voltage to a logic high voltage, the output voltage is switched from a logic high voltage (-20V) to a logic low voltage (<〇ν ) Status. Conversion (please read the precautions on the back before filling this page) -------- Order ---------. This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) 33 554476 V. Description of the invention (the gain of the divider, that is, the maximum slope of the feature will be greater than 1, which is necessary to make more complex circuits, such as ring oscillators State. Vias as described above can also be used to provide electrical connections between interconnects in different layers. For complex electronic circuits, multilevel interconnect patterns are required. This can be achieved by depositing a series Interconnects 72 and different dielectric layers 70, 71 are manufactured in a manner that is deposited from compatible solvents (Figure 15 ((1). Vias 73 can be subsequently formed using the method described above to provide automatic margins). Interconnects with engraved stop instructions. Examples of suitable dielectric materials are polar polymers (70) such as PVP, and non-polar dielectric polymers (71) such as polystyrene. They can be polar and non-polar Solvent replacement deposition. Through local deposition of a good solvent for individual dielectric layers, the vias can be opened, and the underlying dielectric layer will be provided with an etch stop layer. 4 When selecting materials and deposition processes for the above type devices , You should pay attention The good thing is that if each layer is deposited from a solvent that does not substantially dissolve the underlying layer, then many advantages can be obtained. In this way, through the solution processing method, subsequent layers can be established One of the ways to choose a simplified material and process step is to alternately deposit two or more layers from polar and non-polar solvents, as in the layer sequence shown above. In this way, the multilayer body device contains a soluble, Conductive, semiconductor, and insulating layers can be easily formed. This will solve the problem of dissolution and the expansion of the underlying layer. The device structure, materials, and processes described above are examples. They can also vary. This paper size applies Chinese National Standard (CNS) A4 Specification (2) 0 × 297 mm 34 554476

Device configurations other than the top gate configuration shown in Figure 1 can also be used. The alternative configuration is the more standard bottom gate configuration shown in Figure 17, where it may be possible to combine the diffusion barrier 7 and the surface modification layer 8 if required. In Figure 17, components similar to Figure 1 will be represented by the same component numbers. Other device configurations with different layer sequences can also be used. Devices other than transistors can also be formed in a similar manner. With any conductive polymer, PEDOT / PSS can be replaced, which can be deposited from solution. Examples include polybenzylamine or polypyrrole. However, some attractive features of PEDOT / PSS include: (a) dopants (PSS) of polymers with low diffusivity; (b) excellent thermal stability and stability in working gases' and (c) The work function of »5 _ 1 θ \ /, which is quite consistent with the ionization potential of a common hole transporting semiconductor polymer, which allows the effective hole-like charge carrier to be ejected. Effective charge carrier injection is important, especially for short-channel transistor devices with a channel length L &lt; 10 Mm. In this device, the resistive effect of the source and terminal contacts may limit the TFT current to a small source-drain voltage (Figure 10 (b)). In devices with control channel lengths, it has been found that ejection from a PEDOT source / drain will be more efficient than ejection from an inorganic gold electrode. This shows that an ionization potential of a polymer source-drain electrode that is quite in line with the ionization potential of a semiconductor will be better as an inorganic electrode material. The conductivity of PEDOT / PSS deposited from an aqueous solution (Saytron P) will be on the order of 0.1-1 s / cm. Use this paper size containing solvent mixture to apply Chinese National Standard (CNS) A4 specifications (2〗 0 X 297 mm)

Please read &gt; Read the back of the note. Note the item. Win # 装 装 衣 Page I Order Printed by the Intellectual Property Bureau, Ministry of Economic Affairs, Consumer Consumption Cooperative 35 554476

Formulated for high conductivity up to 100 s / cm (Sayer CPP 105T, containing isopropanol and N-methyl_2-pyrrolidone (NMP)). In the latter state, it will be noted that the solvent combination formulation will be compatible with the solubility requirements of the layer sequence. For applications that require higher conductivity, other conductive polymers or solutions will be used—physical inorganic conductors, such as colloidal levitation bodies of liquid metal inorganic particles.

The processes and devices described herein are not limited to devices made from solution-processed polymers. In a circuit or display device (see below), some conductive electrodes of TFTs and interconnects can be formed from inorganic conductors, for example, by printing on a colloidal suspension or depositing on a preformed substrate plating. In devices where not all layers are deposited from solution, one or more PEDOT / PSS parts can be replaced with a soluble conductive material, such as a vacuum deposited conductor. With other semiconductor materials that can be processed by other solutions, the semiconductor layer can be replaced at the same time. Possibilities include small conjugates with printed chains of employees' cooperatives in the Intellectual Property Bureau of the Ministry of Economic Affairs, solubilizing side (issued by JG · Laquindanum et al., No. 120, 1998. J. Am_Chem · Soc, p. 664) Semiconductor-organic and organic-free hybrid materials, which self-assemble in solution (CR Kagan et al., Issue 286 Science Magazine, page 946, 1999); or solution-deposited inorganic semiconductors, such as CdSe nanoparticles ( (B.A. Ridley et al., 1999, Issue 286, Science Magazine, page 746). This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 36 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 554476 A7 ----- B7 V. Description of the invention Other techniques can be used to shape the electrode. Suitable techniques include soft lithographic printing (applied by J_A_Rogers et al., No. 75, Appl. Phys. Lett, p. 1010, 1999; by S. Brittain, et al., 1998 Physics World May issue, page 31), screen printing method (9th Chem. Mat, page 12999, published by Z. Bao et al., 1997), and light lithography type prototyping method ( (See WO 99/10939) or plating. Inkjet printing is considered to be most suitable for having large areas with good read patterns, especially for flexible plastic substrates. In addition to glass plates, the device Can be deposited on other substrate materials, such as plexiglass or a flexible plastic substrate, such as polyether. This material is preferably in the form of a flat plate, and is preferably a polymer material, and can be transparent or elastic Although it is better to use solvent Processing and printing technology, which can deposit and model the layers and components of all devices and circuits, one or more components, such as semiconductor layers, can be deposited using vacuum deposition technology, and use light lithography to pattern As mentioned above, a TFT device can be a part of a complex circuit or device, and one or more of these devices can be integrated with each other or with other devices. Examples of applications include logic circuits and active matrices of displays or memory devices Circuit, or user-defined gate array circuit. The basic composition of a logic circuit is the converter shown in Figure 15. If all the transistors on the substrate are empty or accumulated, there are

37 554476 A7 ------— B7____ V. Description of the invention (for two possible configurations. The empty-load converter (No. 15 (sentence diagram)) is suitable for normally opened devices (Figure 1 (c) and (Figure 3), and the enhanced_load configuration (Figure 15 (b)) is used to normally turn off the transistor (Figure 1 (a / b) and Figure 4). The two configurations require a through hole, They are located between the gate of the load transistor and its source and drain. The alternative configuration is a resistive load converter (Figure 15 (c)). The latter device can be printed with sufficient length and conduction The thin and narrow PEDOT line is used as the load resistance. By reducing the conductivity of PEDOT, for example, by increasing the pss ratio to PEDOT, the length of the resistance line can be minimized. It is clear that the above-mentioned TFT and In the hole manufacturing process, it is possible to manufacture converter devices and more complex logic gates. The solution · processing process described above can be used as the pixel switching transistor of an active matrix display, such as a liquid crystal display (Lcd) or an electrophoretic display. (B.Comiskey et al., Issue 394, Nature, 1998, p. 253 Wherein a appropriate circuitry appears in the first 18 (a) in FIG.; And a light emitting diode display (manufactured by η.

Issued by Sirringhaus et al., 1998, No. 280, Science, Intellectual Property Bureau, Ministry of Economic Affairs, Intellectual Property Bureau, Consumer Cooperative (Page 1741), one of the appropriate circuits is shown in Figure i8 (b); or active matrix addressing of memory devices A device, such as a random access memory (RAM). In Figs. 18 (a) and (b), the transistor T1 and the transistor T2 described above can be formed. Appearance feature 40 represents a display or a memory element with current and voltage supply pads. A possible device configuration for controlling the electrode voltage of an LCD display or an electrophoretic display will be shown in Figure 19, where the paper size similar to that of Figure 1 applies the Chinese National Standard (CNS) A, 丨 specifications (210 X 297 mm) ) 38 554476 A7 __________ B / ______ 5. Description of the invention (exempt parts will be represented by the same component number. In Figure 19 (such as Figures 7, 14 and 17), the gate insulation layer may include a multilayer body structure, It contains a diffusion barrier and a surface modification layer, as shown in Figure 1 (a). Please refer to Figure 18, the source and gate electrodes 2, 3 of the TFT are connected to the data of an active matrix made of different conductive materials Line 44 and addressing line 43 can achieve sufficient conductivity for a longer length. The drain electrode 3 of Tft can be a pixel electrode 41. From different conductive materials, the pixel electrode can be formed, as shown in Figure 19. In applications that rely on electric fields In a device that does not rely on charge carrier emission, it is not necessary for the electrode 41 to directly contact the display element 40, such as a liquid crystal display or an electrophoretic display, etc. In this configuration, all the pixel areas occupied by the TFT and the interconnect must be Keep it small enough to achieve a sufficient aperture ratio and reduce the potential interference between the display element 40 and the signal on the data line 43 and the address line 44. The configuration in Figure 19 (b) is more complicated. However, the overall pixel Or most of the pixel area is available for TFTs and interconnect lines, and with the pixel electrode 41, the display element will be shielded from the signals on the data line 43 and the address line 44. The fabrication of the configuration needs to be filled with conduction An additional dielectric layer 42 of material 45 and a via hole are used to connect the pixel electrode 41 to the TFT electrode 3. The above-mentioned procedure can be used to make the via hole. It should be noted that, in this configuration, the aperture ratio Will be maximized and can reach 100%. This configuration can be used in display applications with backlight at the same time, such as transmissive LCD displays, because the all-polymer TFTs made here are highly transparent in the visible range This paper size applies to Chinese National Standard (CNS) A4 specifications (2) 0 X 297 mm (Please read the precautions on the back before filling this page) -Installation -------- Order ----- ---- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics 39 554476 A7 B7 V. Description of the invention (3). Figure 20 shows the optical absorption spectrum measured on the F8T2 polymer TFT, in which a liquid crystal-like semiconductor polymer is deposited on a friction polyimide adjustment layer, The polymer chain appears to be uniaxially aligned, which can also be used as a high-resolution printing method and pattern. It can be seen that due to the relatively high band gap of F8T2, the device is highly in most visible light ranges Transparent. If the semiconductor layer, such as F8 or TFB or other polymer derivatives (U.S. Patent No. 5,777,070), has a band gap higher than that used, higher transparency can be achieved. The adjustment of the polymer chain will enhance the anisotropy of the light, so that the light polarized parallel to the adjustment direction (indicated by &quot; | | &quot; in the figure) can be more strongly absorbed 'than the polarization is perpendicular to the adjustment direction Light (&quot; 丄 &quot; in the picture). The guide is a normal polymer chain adjustment direction for the polarizer, which is between the glass substrate and the stupid light. The color anisotropy of the light can be used in the LCD display to further increase the light transparency of the TFTs. Under polarized light, the transistor device will appear almost colorless in visible light if the thickness of the F8T2 layer is less than 500A. All other layers of TFTs containing PEDOT will have low light absorption in the visible spectral range. Another advantage of the low light absorption of the semiconductor layer is the reduced sensitivity of the TFT characteristics to visible light. In the case of amorphous TFTs, a black matrix must be used to avoid a large turn-off current under light. In the case of polymer TFTs with a wide band gap, it is not necessary to protect the TFTs from the surrounding light and the backlight of the display. The configuration in Figure 19 (b) is also suitable for LED displays. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) r. Packing -------- Order ---------. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 40 554476

(Zero) The driving transistor T1, because the entire area under the pixel electrode 41 is utilized by manufacturing an inter-finger array of a source and a drain with a large channel width w, it will allow the driving current of the TFT to increase . Alternatively, the bottom gate TF1 ^ state of Fig. 17 can also be used in all the above applications (Fig. 19 (())). One of the important technical issues for manufacturing active matrix circuits is the contact between the PEDOT / PSS TFT and the pixel electrodes 2, 3, 6 and the metal interconnection lines 43, 44, and 41. Due to its strong acidity, pEDOT / pss is not compatible with any common inorganic metals, such as aluminum. When in contact with PEDOT / PSS ,! Lu easily oxidizes. One of the possible solutions is to make interconnects and pixel electrodes 43, 44 and 41 from indium tin oxide (ΐτο), or from other materials that are more stable in this environment, or use an appropriate barrier layer. For application displays, it is also preferable to manufacture TFTs with a small channel length, and print on a pre-shaped substrate shown as 10 in Figure 19, as described above. If the pre-controlled pixel element is not a display element, but a memory element, a similar device configuration of an active matrix transistor switch, such as a capacitor or a diode, can be used. As for the dynamic random access memory Instance. In addition to conductive electrodes, some layers of TFTs can also be patterned using direct printing methods, such as screen printing or | j p. Figure 21 (a) (where the same components as in Figure 1 are represented by the same component numbers) shows a device in which the active layer island shape of semiconductor layer 4 is in accordance with the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling out this page) -------- Order —------- · Printed by the Employees ’Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 41 Printed by the Consumer Cooperatives of the Property Bureau 554476 A7 ---------------- 5. Description of the invention (3 feed and gate insulation layer 5 can be printed directly. In this example, no through hole is required, but it must be used Direct printing to make a connection of the appropriate gate electrode pattern 6. In areas where the addressing or interconnecting lines 43, 44 overlap the thick islands of the dielectric polymer 46, they may have to be printed to provide electrical insulation (Figure 21 (b)). Multiple devices formed as described above can be formed on a single layer and interconnected by a conductive layer. These devices can be formed on a single level or more than one level, Some devices are formed on top of others. Using the interconnecting bar described above Through-holes can form compact circuit configurations. The technology developed here to manufacture inkjet printed transistors, vias, and interconnects can be used to manufacture integrated electronic circuits using inkjet printing methods. Hydrophilic and A prefabricated substrate of an array of water-resistant surface areas, which defines the channel length of the transistor and the width of the interconnection lines. The substrate may contain an array of highly conductive metal interconnection lines simultaneously. Use inkjet printing and deposition of a continuous layer from a solution A hybrid of the two technologies, the transistor device array can be defined at a customized location with a customized channel width. By forming an electronic connection between the transistor pair and the current interconnect, a spray of through-holes and conductive lines is used. The ink-printing method can then be used to fabricate an integrated circuit. It is also possible that the pre-fabricated substrate may already contain components of one or more transistor devices. The substrate may include, for example, an array of complete inorganic transistor devices, the device having at least An exposed electrode. In this example, the inkjet manufacturing process for integrated circuits can include the use of inkjet printed paper with a size that applies Chinese national standards (CN S) A4 size (210 X 297 mm) .J ^ ^ t -------- ^ --------- ^^^^ 1. (Please read the precautions on the back before filling (This page) 42 554476 554476

V. Description of the invention (_ Employee Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs printed agricultural brush vias, interconnections and isolation pads to form an electronic connection between the transistor pair and the deposition of a single or multiple level interconnection scheme (See Figure 15 (d).) In addition to transistors, 'electronic circuits can include other active and passive circuit elements, such as displays or memory elements or capacitive or resistive elements. Using the techniques described above' has many Units of individual transistors can be formed and subsequently configured for subsequent use, utilizing solution-based processing methods. For example, a substrate with multiple transistors 50, such as Section 1 (a), (b), or (C) The pattern shown in the form of the gate array can be formed on a plastic plate (Figure 22). Other devices, such as diodes or capacitors, can be formed on the plate at the same time. Then, The board can be placed in an inkjet printer, which has a print head with a suitable solvent (such as methanol) to form the through-holes 52, or has a suitable mark 53 for conducting and fills the through-holes. Material ( Such as ped〇t). The inkjet printer can be operated under the control of a suitably programmed computer, which has information on the configuration and location of the transistor on the plastic board. Then, through the formation of through-holes and Merging of interconnect steps, inkjet printers can be assembled with circuits to interconnect transistors in the desired way to perform the desired electronic or logic function. This technology therefore allows the use of small and inexpensive devices to Form a logic specific circuit on the substrate. Application examples of this type of circuit are the printing of active electronic tickets, baggage cards and identification cards. Tickets or card printing devices can be loaded into a variety of paper standards that are applicable to Chinese national standards (CNS ) A4 specification (2) 0 X 297 mm) (Please read the precautions on the back before filling this page)

43 554476 V. Description of the invention (also not assembling units, each unit contains a substrate carrying multiple transistors. The ticket printing device includes a computer, which can control an inkjet printer as described above, and An electronic circuit that can identify the effective function of the ticket. When the ticket needs to be printed, the printing device will use printed through holes and conductive materials to configure an appropriate electronic circuit to make the substrate on the substrate The transistor is properly assembled. The substrate can be subsequently packaged, for example, sealed with an adhesive plastic sheet, leaving the electrical connections 54 and 55 out of the way. Tickets will be assigned later. When the ticket is to be verified, The application is input to one or more input terminals, and the circuit output terminal on one or more output terminals will be monitored to verify its function. The ticket can be better printed on the elastic plastic substrate so that They are convenient for use as a ticket. User-defined circuits other than for price tagging or labeling purposes can also be manufactured in a similar way. Using, for example, wireless band frequency radiation, by remote detection, circuit verification And reading can also be done (Physics World Miscellaneous, page 31, February 1999). By performing simple inkjet printing on a standard array, the ability of the end user to define the circuit will provide an advantage over factory design The circuit has greater flexibility. The present invention is not limited to the examples described above. The present invention will include all the novelty and advancement of the disclosed concepts, and all the novelty and progress mixtures of all the disclosed features. It is to be understood that the present invention may include all express or implied features and combinations thereof, and is not limited to the above-disclosed paper standards and family standards (CNSM4, ^? Γ297 public love). Order 4 44 554476

V. Description of the invention (the scope of the definition must be disclosed. In summary, as long as it does not deviate from the scope of the present invention, there can be various changes for skilled artisans. Printed by employee consumer cooperatives 1 Glass substrate 13 Ink droplets 2 Source electrode 14 Modeling layer 3 Drain electrode 20 Inkjet head 4 Active semiconductor polymerization 21 Ink droplets / liquid crystal semiconductors 25 Glass substrate / gold pole polymer 26 PEDOT Electrode layer 5 Gate insulation layer / PVP 27 F8T2 Semiconductor layer insulation layer 28 PVP insulation layer 6 Gate / patterning layer 29 Appropriate solvent / droplet / transmission 7 Diffusion barrier polymer conducting electrode 8 Surface modification layer 30 Curve 9 Poly醯 imide layer 31 curve 10 thin poly 醯 imide layer / poly 32 area 醯 imine pattern 40 appearance features / display 11 photoresistive material element 12 hydrophilic substrate area / bare 41 pixel electrode glass surface 42 dielectric layer paper size Applicable to China National Standard (CNS) A4 specification (210 X 297 mm)-!.!! · (Please read the precautions on the back before filling this page) Installation -------- Order ----- ---- · Qu 45 5544 76

V. Description of the invention (must be 43 addressing line 44 data line 45 conductive material 46 dielectric polymer 50 transistor 52 through hole 53 trace 54 electronic connection terminal 55 electronic connection terminal 70 dielectric layer 71 dielectric layer / dielectric polymer 72 Interconnects 73 Vias T1 Transistors T2 Transistors (Please read the precautions on the back before filling this page) · ϋ I ϋ 1 · —ϋ m, I ϋ n ϋ I ϋ ϋ I * In the wisdom of the Ministry of Economic Affairs The paper size printed by the Property Cooperative Consumer Cooperative is applicable to the Chinese National Standard (CNS) A4 (210 x 297 mm)

Claims (1)

Scope of application for patent No. 90109546 Patent application for patent application Amendment S May 1, 1992 · A method for forming an electronic device, comprising: forming a first conductive or semiconductor layer; on the first conductive or semiconductor layer Forming an order of at least one insulating layer and at least one semiconductor layer on the layer; locally depositing a solvent on a localized area of the insulating layer so as to dissolve the order of the insulating layer and the semiconductor layer in the area to make a through hole Extending the sequence through the layer; and depositing a conductive or semiconductor material in the via. 2. The method of claim 1 in which the solvent is deposited at the same time. 3. The method of claim 1 in which the solvent is deposited sequentially. 4. A method for forming an electronic device, comprising: forming a first conductive or semiconductor layer; forming a soluble insulating layer on the first conductive or semiconductor layer; locally on a localized area of the insulating layer A solvent is deposited on the ground so as to dissolve the first insulating layer in the region so that a via extends through the insulating layer; and a conductive or semiconductor material is deposited in the via. 5. The method according to item i in the patent application, wherein the first layer is substantially insoluble in a bath or a plurality of solvents. The method in item 5 of the patent application, wherein the first layer is Contains a semiconductor conjugated polymer. For example, the method of claim 5 of the patent scope, wherein the first layer comprises F8T2 or TFB. For example, the method of claim 5 in which the first layer is an active layer of the electronic device. The method as claimed in claim 5 includes the step of depositing a conductive layer under the first layer body. For example, the method of claim 9 in which the conductive layer is an electrode of the electronic device. For example, the method of claim 5 in which the first layer comprises a conductive conjugated polymer. For example, the method of claim 5 in which the solvent or the solvents are cut in the volume required to dissolve the insulation and semiconductor layers in a pure domain. For example, the method in the patent application scope β includes a material that forms another conductive or semiconductor layer on the insulation layer or the semiconductor layer or contacts the through hole. The method of claim 13 in which the first conductive or semiconductor layer will form an electrode or an interconnect. For example, the method of claim 13 wherein the other conductive or semiconductor layer will form an electrode or an interconnect. The method according to item 丨 of the aforementioned patent application scope, in which profit / applicability application scope A8B8C8D8 is printed by the inkjet printing method of the consumer cooperative of employees of the Intellectual Property Bureau of the Ministry of Economic Affairs to deposit the solvent or solvents. 17. The method according to the scope of application for the patent No. 16 item, wherein the solvent or the plurality of solvents is deposited as a single pseudo-droplet by an inkjet printing method. 18. The method according to claim 16 in which the solvent or solvents are deposited as a plurality of droplets by an inkjet printing method. 19. The method as claimed in claim U, wherein the boiling point of the solvent or a mixture of solvents is higher than 800c. 〇 The method according to item 1 of the Zhonglian patent, wherein the boiling point of the solvent or a mixture of the solvents is higher than 1000c. 21. The method of claim 1 or 18, wherein the boiling point of the solvent or a mixture of the solvents is less than 100oC. 22. A method as claimed in the patent application, wherein each of the layers in the one or more solvents has a solubility of greater than 1% by weight per volume. 23. The method according to item [] in the scope of patent application, wherein in the one or more solvents, each layer of the layer has a solubility of two to two percent by weight per volume. 24. The method according to item 4 of the patent application, wherein in the solvent, the first insulating layer has a solubility higher than 100% by weight per volume. 25. If the method of item 4 of the patent is claimed, wherein the solvent 6. Applying for profit-seeking Fanyuan Zhongyuan's far-insulating layer has a solubility of more than 2 weight percent per volume. 26. The method according to item 1 of the patent application, wherein the electronic device is an electro-crystal and the material deposited in the through hole will form a channel between the electrode and the interconnection line in different layers. Hole interconnect. 27. The method according to claim w, wherein the solvent or the δ? Solvents are an alcohol. 28. The method of claim μ, wherein the solvent or solvents are IPA or methanol. 29. The method as claimed in item 1 of the patent application scope, which comprises the step of using its wetting properties to form a defined structure to confine the solvent or the cereal / cereal in the localized area. 30. A method for forming an electronic device, comprising: forming a first conductive or semiconductor layer; forming an order of the insulating layer and the semiconductor layer on the first conductive or semiconductor layer; and localizing the insulating layer A diffusive dopant is locally deposited on the area so as to adjust the insulating layer and the semiconductor layer in the area, and then form a channel of electrically conductive material extending through the layer body sequence. 31. The method of claim 30, wherein the diffusion dopant is deposited by an inkjet printing method. 32. The method according to item 30 of the scope of patent application, in which the electronic device is 297 mm) Paper size 剌 + Family Standard (CNS) A4 specification (210 554476 Application for profit-seeking range 33. 34. 35. 36. 37. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 38 · Set as f crystal ', and the channel will form a layer between the electrode and the interconnection line in different layers of the device A through-hole interconnect. For example, the method of claim 1 in which the insulation layer includes PVP. For example, the method of applying for the first item of the patent scope, in which a layer between the insulating layer and the layer directly below the insulating layer can be dissolved in a polar solvent, and the insulating layer and the layer directly below the insulating layer can be dissolved. The other layers in the body can be dissolved in a non-polar solvent. For example, the method of claim 1 in the patent scope, wherein a plurality of electronic devices formed by the method can be included in a logic circuit, a display, or a memory device. For example, the method of claim 1 in the patent scope, wherein a plurality of electronic devices formed by the method can be included in a logic circuit and interconnected to perform a logic function. For example, if the method of claim 36 is applied, in the logic circuit, at least H of the devices will be connected to other devices by using conductive materials located in the through holes, and the through holes are through the devices H "to -A display device including-an optical active area, which can be switched by an electronic device formed by the first slave branch, which is located in a pass, please read the note S) ί (Fill in # hardcover, page I, order 51 reference paper standards, stab Zhongguan family standard (CNS) A4 secret g 297 mm) 554476 8888 ABCD VI. Patent application scope The conductive material in the hole is coupled to the optical active area 'The through hole is formed through at least one layer of the device. (Please read the precautions on the back before filling this page) The paper printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs applies the Chinese National Standard (CNS) A4 size (210 X 297 mm)