TWI229884B - Solution processed devices - Google Patents

Abstract

A method for forming a transistor, comprising: depositing a first material from solution in a first solvent to form a first layer of the transistor; and subsequently whilst the first material remains soluble in the first solvent, forming a second layer of the transistor by depositing over the first material a second material from solution in a second solvent in which the first material is substantially insoluble.

Description

I229884 V. Description of the Invention (The invention relates to a solution processing device and a method for forming the device. Semiconductor conjugated polymer thin film transistors (TFTs) have recently been applied to inexpensive, logic circuits integrated on plastic substrates. (Publication No. 73, APL, published by Man in 1998, p. 108), and also applied to optoelectronic integrated devices and pixel transistor switches of high-resolution active matrix displays. (Published by H. Sirringhaus et al., 1998 280 Science, page 1741 and 1998. AppL Phys. Lett, page 142, published by a. Dodaba 丨 apur et al. 1998. Testing of polymer semiconductors and inorganic metal electrodes and gate dielectrics In the device configuration, high-efficiency TFTs have appeared. Compared with the performance of amorphous silicon TFTs, high-efficiency! ^ 3 has reached a charge carrier mobility of up to CMcm2 / Vs and on / off current of 〇m〇8 Ratio (Advances in Solid State Physics, Issue 39, published by H. Sirringhaus et al., 1999, p. 101). Device Quality of Conjugated Polymer Semiconductors Printed by Consumer Cooperatives of the Intellectual Property Office of the Ministry of Economic Affairs The thin film can be formed by applying a polymer solution in an organic solvent to the substrate. This technology is therefore suitable for processing of large-area solutions that are compatible with flexible, plastic substrates. To make full use of cheap And the advantages of the simple processing technology, preferably, all the components in the device, including the semiconductor layer, the dielectric layer, and the conductive electrodes and interconnects, are deposited from the solvent. In order to manufacture all-polymer TFT devices and Circuits, the problems that must be overcome are as follows: This paper size is applicable to the Chinese National Standard (CNS) A4 specification (x Nogakuai) 1229884 A7 B7 V. Description of the invention (-the integrity of the multilayer body structure ... During solution deposition of the conductive layer, the underlying layer should not be dissolved or expanded by the solvent used to deposit in subsequent layers. If the solvent cannot be injected into the underlying layer that causes the layer's properties to deteriorate, it will occur Expansion.-High-resolution patterning of electrodes: The conductive layer must be patterned to form well-defined interconnects with channel length LslOpm TFT channel.-In order to manufacture a TFT circuit, a vertical interconnect region (through hole) must be formed to electrically connect the electrodes in different layers of the device. In WO99 / 10939 A2 patent application, a method for A method for manufacturing an all-polymer TFT, in which the processing layer of the device is converted to an insoluble form before subsequent layers of the device are deposited. This method can solve the problem of dissolution and swelling of the underlying layer. However, However, it severely limits the choice of semiconductor materials that can be used, that is, only certain groups of small precursor polymers that are not desired can be used. Furthermore, the interconnection of the dielectric gate insulating layer makes it difficult to make through holes through the dielectric layer, and therefore a technique such as mechanical perforation is required (WO 99/10939 A1). According to a first aspect of the present invention, a device and method are provided as described in the scope of the appended patent application. According to an aspect of the present invention, a preferred feature of the present invention is provided in an independent patent application line. In accordance with one aspect of the present invention, a paper size for use in forming electronic paper is applicable. A7 B7 printed by the Consumer Cooperatives of the Ministry of Intellectual Property Bureau V. Invention description (3 Crystal method, which includes: using a first solvent to deposit a first material from a solution to form a first layer of the transistor; and then A second material is deposited from the solution using a second solvent to form a second layer of the transistor; wherein the first material is substantially insoluble in the second solvent. Suitably 'the at least one layer of the transistor is The formation is by an inkjet printing method (IJP). The layer body may be a layer body provided with an electrode of the transistor, such as a gate, a source, or a drain. Preferably, the method includes forming the transistor. An active layer, a method for forming an isolation layer on the active layer, and a method for forming the transistor gate on the isolation layer. The isolation layer can be provided with a diffusion barrier and a surface modification layer, which As a separate or identical layer. According to the first aspect of the invention, a method is provided for depositing a solution of a defined material onto a defined area of a substrate. The method includes patterning the surface of the underlying substrate to become Areas with different surface free energies. The substrate may have water-repellent surface areas and other hydrophilic surface areas. Solution deposition may include inkjet printing methods and methods for limiting ink to water-repellent or hydrophilic substrate areas. 'The pattern on the substrate will define the source and drain of the transistor, which preferably has a small channel length of L < 20pm, and where the gate and source / drain present a defined overlap, and have interconnects According to the third aspect of the present invention, a through-hole is formed to define the electrical connection between the electrodes and the interconnects in different layers. 6 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) Love) ---- · ---- ^ ------------ Order --------- line (Please read the precautions on the back before filling this page) 1229884 Economy Printed by the Ministry of Intellectual Property Bureau's Consumer Cooperative

i J ------- --Order --------- Line _ (Please read the notes on the back before filling this page) A7 --------___ V. Description of the invention ( Cold method. The method includes dissolving or doping the layer by local deposition of a solvent or a doping solution, preferably by an inkjet printing method. According to another aspect of the present invention, a method is provided. A method for manufacturing an electronic device array having at least one exposed electrode. The method includes using an inkjet printing method of conductive materials to interconnect electronic devices to obtain an electronic circuit with user-defined functionality. It will be exemplified by The invention is explained with reference to the drawings in the appendix, in which: Fig. 1 shows different device configurations of solution processing and all-polymer TFTs; Fig. 2 shows the F8T2 active layer and pVp gate insulation layer according to the diagram Conversion characteristics of polymer TFTs with PEDOT / PSS gate electrode; Figure 3 shows the conversion characteristics of polymer TFTs with F8T2 active layer, pVp gate insulation layer, and PEDOT / PSS gate electrode according to (ii) , With the sample at room temperature (a) and about 500 ° c (b) Deposition; Figure 4 shows the output and transition characteristics of the F8T2 all-polymer TFT including the F8 diffusion barrier and PVP surface modification layer as shown in Figure 1 (a) (bj; Figure 5 shows as in Figure 1 (a ) The conversion characteristics of F8T2 all-polymer TFTs with TFB (a) and polystyrene (b) diffusion barrier and PVP surface modification layer; National paper standard (CNS) A4 size (210 X 297) Love) 1229884

Printed in Figure 6 by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, showing optical microscopy of an all-polymer TFT with F8T2 active layer and source-drain printed directly on a bare glass substrate according to figure i (a) Fig. 7 shows the manufacturing process of TFTs with small channel length and small overlapping capacitance, which is patterned on the surface of the substrate to become a water-repellent and hydrophilic region; Fig. 8 shows the area around the water-repellent polyimide group Light micrograph of the channel region of the transistor with L = 20pm (a) and L = 5pm (b) after IJP deposition of the pedot / PSS source // and electrode; Figure 9 shows the Photomicrographs taken during the deposition of a few drops of ink around the imine group; Figures 10 and 10 show the phototransistors formed as shown in Figure 7 (c) and having channel lengths ί_ = 20μιτι and 7μίτι, respectively. Output and conversion characteristics; Figure 12 shows an exploded view of the process of successively depositing several drops of methanol on a 13μηι thickness ρνρ gate dielectric layer to form a through-hole (a), Dektak profiler and optical display Micrograph (b); Fig. 12 (c) shows a succession of 彳 3μηι thickness A schematic side view of a via hole formed by depositing a few drops of methanol on the pvp gate dielectric layer. Figure 13 shows the current-voltage characteristics of a bottom PEDOT electrode and a top electrode through the via; Figure 14 shows Different processes for manufacturing vias; Figure 15 shows the application of vias, such as logic converters (empty_load (a), enhancement · load (b) and resistive-load (c)), and multiple bits Figure of quasi-interconnect (d); Figure 16 shows the enhanced and loaded converter circuit as shown in Figure 1 (a). 8 paper sizes are applicable to China National Standard (CNS) A4 (210 X 297 mm) I I --- 丨 —-I 丨 丨 — 丨 --I ----- Order ----- • Line · I (Please read the notes on the back before filling out this page} 1229884 A7 V. Description of the invention ( $ Features, which are made of printed all-polymer TFTs with a W / L size of two transistors in different proportions; Figure 17 shows the configuration of an alternative bottom gate device; Figure 18 is a structural diagram of an active matrix pixel, where The display or memory element is controlled by a voltage (a) or a current (b); Figure 19 shows a possible configuration of the pixels of an active matrix; Figure 20 shows a pair of Polarized optical absorption of F8T2 TFT; Figure 21 shows (a) polymer FTs with patterned active layer islands manufactured by semiconductor and dielectric layer printing; and (b) printed islands Overlapping areas between conductive interconnects separated by objects; Figure 22 shows a matrix of transistor devices connected by the | jp interconnect network to make user-defined electronic circuits. The preferred manufacturing method will allow the manufacture of all-organic, solution-processed thin-film transistors where no layers will be converted or interconnected to an insoluble form. Each layer in the device can be maintained in a form that can be > dissolved in the deposited solvent. As will be explained in more detail below, this will allow the vias to be fabricated in a simple manner through a dielectric insulating layer based on local solvent deposition. For example, the device will contain one or more of the following components: i-conducted conductive source-dim and gate and interconnect. A semiconductor layer having a charge carrier mobility of more than 0.01 cm2 / Vs and a high on-off current conversion ratio of more than 104. -A thin gate insulation. Binding Line Size of this paper: Guan Jiaxian x 297 mm) 1229884 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

, I -------- ^ --------- (Please read the notes on the back before filling out this page) A7 -----— V. Description of the Invention (T) _ One Diffusion A barrier layer that protects the semiconductor layer and the insulating layer from accidental doping caused by the diffusion of impurities and ions. -A surface reforming layer that uses printing technology to achieve high-resolution prototyping of the gate. -Vias to the interconnect through the dielectric layer. However, what is desired is that the method described here is not limited to a method of manufacturing a device having all of the features described above. A method of manufacturing the first exemplary device will now be described with reference to FIG. The device in Fig. 1 is a thin film field effect transistor (TF), which is assembled to have a top gate structure. At the top of the cleared 7059 glass substrate 1, the interconnects between the source electrodes _ 2 and 3 ′ and the electrodes and contact pads (not shown) will use inkjet printing to deposit an aqueous conductive polymer polyethylene A solution of dioxythiophene / polystyrene sulfonic acid (PEDOT (0.5 weight ratio) / pSS (0-8 weight ratio)). Other solvents, such as methanol, ethanol, isopropanol, or acetone can also be added to affect the surface tension, viscosity and wetting properties of the ink. PEDOT / PSS is commercially available from Bayer, such as " Baytron P ".丨 JP printer is piezoelectric type. Its equipment has a two-dimensional conversion stage and a micro stage, which enable subsequent printing patterns to be aligned with each other. The IJP print head is driven by a voltage pulse. At 20V pulse height, when the rise time is ιμ3 and the fall time is 10ps, an appropriate driving condition for injecting a typical solid content of 0.4ng per drop can be achieved. 10 paper sizes for drying on a glass substrate are in accordance with Chinese National Standard (CNS) A4 (210 x 297 mm) 1229884 A7 V. Description of the invention (including

After the staff of I Bureau has printed f, they will produce PEDOT dots with a typical diameter of 50 [Jm and a typical thickness of 500 A. The source-drain IJP takes place in the air. Thereafter, the sample is transferred to an inert gas drying cabinet. The matrix will then be spin-dehydrated in an organic solvent which will then be used for active semiconductor layer deposition, such as mixed xylene in polymer. They will then be annealed for 20 minutes in an inert nitrogen gas at 200 ° C to remove residual solvents and other volatiles from the PEDOT / PSS electrode. Subsequently, the 200__ of the active semiconductor polymer 4 The 1000-thick film will be deposited using a spin-on coating method. A number of different semiconductor polymers have been used, such as normal-orientation polyethylthiophene (P3HT), and, for example, poly-9,9, -dioxine -Polyfluorene copolymers of co-dithiophenebutene 2). FBT2 is a better choice because when the gate electrode is deposited in the air, it can show good stability in the air. An anhydrous, mixed xylene (purchased from Romj |) solution of 10 mg / m of FBT2 will be spin-coated at 1500 — 200 — ^^. For P3HT, mixed xylene will be used. A solution with a weight percentage of 1. The underlying PEDOT electrode is not dissolved in a non-polar organic solvent, such as xylene. The membrane is subsequently spin-dehydrated in a solvent that will be used later for the gate insulation layer 5 Deposited solvents, such as isopropanol or methanol. Subsequent annealing steps will be performed later to improve the charge transport properties of the semiconducting polymer. For polymers that exhibit a liquid crystal-like phase at high temperatures, the temperature is higher than the liquid crystal-like transition temperature Annealing will be performed next. Guideline 11 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 Printed by the Intellectual Property Bureau of the Ministry of Public Welfare and Intellectual Property, Employee Consumption Cooperative, 1229884 A7 B7 V. Description of the invention Parallel to each other. In the case of F8T2, the annealing process is performed at 28yC for 20 minutes in an inert A gas. The sample will then be rapidly cooled to room temperature to freeze the chain and produce an amorphous glass. If If the compound is formulated on a flat glass substrate without an alignment layer, the polymer will adopt a multi-domain configuration, in which a plurality of liquid crystal-like domains with random orientations will be located in the TFT channel. The cold part from the liquid crystal-like phase will be used to prepare it. The transistor device of the F8T2 in the vitrified state will exhibit a fluidity of the order of 5.10-3cm2 / vs, which will not only be an order of magnitude higher than that measured on a device with a rotating F8T2 film. The deposited devices are simultaneously Shows a higher opening voltage v. This will be due to the lower density of the electron complement state in the vitrified phase, compared to the partially crystalline deposition phase. If the polymer is formulated to have parallel to electrical In a single domain state where the polymer chain of the crystal channel is uniaxially adjusted, the fluidity can be further improved by a typical 3-5 factor. This can be achieved by coating a glass substrate with an appropriate adjustment layer, such as Mechanically rubbed polyimide layer (9 in Figure 1). In a single domain state, polymer chains are aligned uniaxially parallel to the rubbing direction of the underlying polyimide layer. This will lead to a further enhancement of the charge carrier mobility in the device, in which the TFT channel is parallel to the adjustment direction of the chain. This process will be explained in more detail in the pending British patent application 9914489.1. After the deposition of the semiconductor layer The gate insulation layer 5 is a polyalkylene styrene (also known as polyvinyl phenol (pvp)) that is spin-coated with a polar solvent. The paper size is applicable to China National Standard (CNS) A4 (210 X 297).

1229884

V. Description of the Invention (Allow a solution printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs to deposit the underlying semiconductor polymer. It is insoluble. The preferred solvent is alcohol, such as tritium, 2-propanol or Butanol 'among which, for example, FBT2 non-polar polymer has unexpectedly low solubility and does not swell. The thickness of the gate insulating layer is between 300nm (the solution concentration is 30mg / ml) and 1-3 μm (the solution concentration is 10%). 〇mg / ml). Other insulating polymers and solvents that meet the solubility requirements, such as water-based polyvinyl alcohol (PVA) or propylene glycol methyl ester acetate-based poly · isobutylene salt formaldehyde (PMMA ). Gate 6 will then be deposited on the gate insulation layer. The gate insulation layer can be deposited directly on the gate insulation layer (see Figure 1 ((;)), or, for example, due to surface modification, a diffusion barrier Or, such as solvent-compatible process factors, there may be one or more intermediate layers (see Figure 1 (a) and (b)). In order to form the simpler device in Figure 1 (c), PEDOT / PSS gate 6 can be printed directly on The top of the PVP insulation layer 5. The substrate will be converted to the airborne JP station again, in which the PEDOT / PSS gate pattern will be printed from an aqueous solution. The underlying PVP gate insulation layer has low solubility in water, so that The integration of the gate dielectric is preserved during the printing process of the PEDOT / PSS gate. Although pvp contains high-density polar hydrocarbon groups, its solubility in water is low due to the relatively non-polar poly (phenylene acetofluorene) skeleton. Figure 2. Figure 2 shows a FBT2 semiconductor layer, a PVP gate insulation layer, and one of the JP PEDOT / PSS source drain and gate 丨 JP TFT conversion features. 13 This paper standard applies to Chinese National Standards (CNS) A4 specifications (210 X 297 mm) ·; ------------ Order --------- line ---; (Please read the precautions on the back before filling this page ) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Consumption Cooperative, I229884 A7 ~ ^ " -----------____— 15. Description of the Invention (Imitation. The characteristics of this device are measured in nitrogen. Continuous measurement The values will show the increased (upward triangle) and weakened (downward triangle) gate voltages respectively. Device made with batch and PEDOT / PSS (Baytron P) batch from one year ago. However, 'transistor operation is clearly visible, the device will present a positive voltage with a fixed limit voltage V0> 10V Unusually normally on, and a reference device made of evaporated gold source-drain and gate will assume a normally off state (v0 < 〇). One year with PEDOT (Figure 2 " one year In the former " batch formation device, a large hysteresis effect will be observed, which will be attributed to the high concentration of mobile ionic impurities (see below). If the sweeping action starts in the extremely empty state (Vg = + 40V), the electric crystal will turn on at Vfod20V (upward triangle). However, in the opposite sweep action (downward triangle), the transistor is only at Vr. > Off at + 35V. Due to the diffusion of ionic materials in one layer of the plutonium device, usually the on state and hysteresis effects may occur. V is usually a large positive value. This implies that the ions are negative. A positive species can be expected to compensate for some of the mobile charges in the accumulation layer, and will be V. Switch to a more negative value. In order to identify the source of the ionic material, a device is manufactured, in which the top gate IJP PEDOT is replaced by an evaporated gold electrode, and the other layers and the PEDOT source / drain are manufactured as described above. It has been found that in this configuration, the device is normally switched off and presents a stable, fixed voltage limit. This will imply that the doping and hysteresis effects in all-polymer devices will be related to the conductive polymer top gate. This paper uses Chinese national standards (CNSM4 regulation 0 X 297 public love)

Η; Φ -------- ^ ------ (Please read the notes on the back before filling out this page) -line »1229884 Printed by A7, Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs (The solution is deposited and the PEDOT solution / membrane moves and ionic impurities may diffuse to the lower layer of the device. It has been found that by depositing a gate electrode on a heated substrate, it is possible to control the Limit the value of the voltage and reduce the hysteresis. This will reduce the drying time of the droplets on the substrate. Figure 3 (b) shows the switching characteristics of a TFT device, where the substrate will be heated to 50 ° C during the deposition of the gate It can be seen that the hysteresis effect will be much smaller than that of the gate electrode at room temperature (Northern figure), and v0 has a relatively small positive value of 6V. By controlling the deposition temperature, the fixed voltage can be set at Va = 1_ 20V range adjustment. As shown in Figure 1 (c), the device with gates deposited directly on the pvp layer is empty. For empty_type logic circuits, such as simple empty-load For the logic converter (Figure 14 (3)), the normally open state is Useful. In order to make enhancement-type TFTs are usually turned off, semiconductor diffusion can be avoided by incorporating diffusion barrier layers during gate / child product. In Figure 1 (a) and (b) In the device, before the conductive polymer gate is deposited, a non-polar polymer will be deposited on top of the pVp gate insulation layer. This layer can serve as a diffusion barrier to prevent ionic species from diffusing into the moderately polar PVP insulator. PVp A polar hydrocarbon group containing a bifurcation degree, which will easily enhance the conductivity and diffusivity of ionic conduction and diffuse to the film. Several non-polar polymers have been used, such as poly_9,9, _dioctylfluorene ( F8), polystyrene (PS), poly (9,9 · -dioctylgo, co_N_ (4-butylphenyl) diphenylamine)

7 ----- (Please read the notes on the back before filling in this page) H 1 ^ 1 Order · --- Line · This paper size applies to China National Standard (CNS) A4 x 297 Meal) Wisdom of the Ministry of Economic Affairs Printed by the Property Cooperative Consumer Cooperative 1229884 A7 _____B7 V. Description of the invention (color TB) or F8T2 ° 50-1 00 nm grade polymer film can be deposited from a solution of non-polar organic solvent such as diphenylbenzene in pVP On the surface of the gate insulating layer, PVP is insoluble. It has been found that it is problematic to print PEdot / pss directly on top of the non-polar diffusion barrier layer from the aqueous polar solution because of the poor wetting property and large contact angle relationship. In order to solve this problem, the surface reforming layer 8 will be deposited on the top port of the non-polar polymer, the p σ σ layer layer k is provided with a hydrophilic surface instead of a water-repellent surface, on which PEDOT / PSS can be formed more easily. This will allow high-resolution printing of the gate pattern. To form a surface modification layer, a thin pvp layer can be deposited from an isopropanol solution, where the underlying diffusion barrier layer is insoluble. The thickness of the PVP layer is preferably less than 50 nm. High-resolution PEDOT / PSS printing is possible on pvp surfaces. Alternative surface modification layers can also be used. This includes thin layers such as soap-like surfactants, or polymers containing hydrophilic and water-repellent functional groups. These molecules will tend to separate from the water-repellent and hydrophilic groups, and they will be attracted to the interface with the underlying non-polar polymer and blank surface, respectively. Another possibility is that the surface of the non-polar diffusion barrier will be exposed to a mild 02 gas, making the surface hydrophilic. If the gate electrode is printed from a solvent that is less polar than water, such as formulations containing alcohols (isopropyl alcohol, methanol, etc.), the surface modification layer on the non-polar diffusion barrier may not be needed. The integration of the layer sequence will depend on the alternate deposition of polymer materials from polar and non-polar solvents. What you want is to use as the second (Please read the notes on the back before filling this page) -------- Order --------- line · 16

1229884 A7 _______ Β7 ___ V. Description of the Invention (The solubility of the first layer in the solvent deposited by the layered body will be less than 0.1% by weight per volume, preferably less than 0_01 by weight per volume. At the same time, the Hildebrand solubility parameter is desired The difference between the first layer material and the solvent used to deposit the second layer will be as large as possible (Properties of Polymer, published by Dw · van Krevelen in Amsterdam, Elsevier, 1990 ) 〇 For some device configurations, the full multilayer structure can be established by using the replacement order of the polymer, which mainly contains polar groups and is soluble in highly polar solvents such as water, and contains only some or no A polymer that is polar and soluble in a non-polar solvent such as xylene. One example is a transistor device that contains a highly polar source-drain of PEDOT / PSS, such as a FBT2 non-polar semiconductor layer, such as deposited from water The highly polar gate dielectric layer of polyvinyl alcohol can also be used as a buffer layer to allow the sequential deposition of the TFB layer. Barriers to sexual diffusion, and pedOt / pss gates. However, it is also possible to build a bulk sequence that contains a highly polar and a non-polymeric polymer layer and is deposited from a moderately polar solvent Moderately polar polymer layer. A moderately polar polymer is a polymer that contains polar and non-polar groups and is substantially insoluble in a highly polar solvent. Similarly, a moderately polar solvent contains polar and non-polar groups , But does not substantially dissolve a non-polar polymer. The moderately polar polymer can be simultaneously 1229884 A7

Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economy The functionality of the polymer can be used to increase the solubility in moderately polar solvents and reduce the solubility in polar solvents. One example of a moderately polar polymer is a PVP gate dielectric layer sandwiched between Between a non-polar semiconductor layer and a PEDOT / PSS gate electrode layer (Figure 1c). An example of a moderately polar solvent is an alkanol. Figure 4 shows a p // p gate insulation layer and an F8 diffusion barrier layer The output of the all-polymer F8T2 | Jp tft with the PVP surface modification layer ^ (a) and conversion characteristics (b), as shown in Figure 1 (a) (L = 50pm). The device presents a clean, almost ideal, and usually The transistor action is turned off, which is turned on at vO ^ ov. The fixed voltage between the upward (upward triangle) and downward (downward diagonal) voltage sweeping action is converted to v. The characteristics of this device are quite similar to Under inert gas environment It has the characteristics of a standard device of gold source-drain and gate. The level of field-effect mobility is 0.0005-0.01cm2 / Vs, and it is measured between vg = 〇 and -60V. The on-to-off current ratio is 1 〇4-1 〇5. The device has been manufactured with a wide range of non-polar diffusion barrier layers, such as FB, TFB (Figure 5 (a) shows the conversion characteristics), ps (page 5 (b) shows switching characteristics) and FBT2. In each case, a clean and normally closed condition, small hysteresis effect, and fixed voltage switching will be observed, which are the same as reference devices with a gold source-drain Heavyweight. This will support the application of the Chinese National Standard (CNS) A4 specification (210 X 297 mm) in 18 paper sizes during and after the solution deposition of the gate insulation layer: -------- ^ ---------- ^-^^-1 (Please read the precautions on the back before filling this page) 1229884 A7

Please read the notes of the © © before filling in this page

A 1229884 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ------ B7_____ V. Description of the invention (Increase of air and poor on-off current ratio in the cutting step increases membrane conductivity Relatively low ionization potential, | ρ & 4 · 9 eV. The ratio of high on / off current less than 106 has been shown for P3HT, but after deposition, a reduction and doping step is required, such as exposure to moon well vapor (Issue 39 Advances in Solid State Physics, published by H. Sirringhaus et al. In 1999, page 101). However, on the aforementioned JP TFTs, the post-reduction processing step cannot be performed because it will simultaneously This leads to the dedoping of the PED0T electrode and greatly reduces its conductivity. Therefore, in order to achieve a high current conversion ratio, it is important to use a polymer that has good stability against unintentional doping of oxygen or water Semiconductor. A better type of material to achieve good environmental stability and high fluidity is AB hard needle block copolymer, which contains a normal grade sequence of a and b blocks. Suitable A blocks Structurally well-defined stepped part with high band gap, which has a high ionization potential higher than 5 · 5βν, as a homopolymer and good environmental stability. An example of a suitable A block is a Gou derivative ( U.S. Patent No. 5,777,070), Hydrazine Derivatives (Macrolecules, Issue 33, 2000, published by S. Setayesh, 2000, p. 2016), Subphenylene or Trapezyl Subphenylene Derivatives (by J. Grimme et al., In Issue No. 7 Adv. Mat, published in 1995, p. 292). Appropriate B-blocks are pore-transporting parts with a low band gap, which contain heteroatoms such as sulfur or nitrogen, and are Homopolymer of ionization potential. Pore transmission b into 20 pieces This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) _. ^ -------- t ------ --- Μφ—J (Please read the precautions on the back before filling in this page) 1229884

V. Description of the Invention (An example of a printed product of the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is a thiophene derivative or a triarylamine derivative. The utility of the block is to reduce the ionization potential of the block copolymer. Block copolymerization The ionization potential of the substance is preferably in the range of 4-9eVdp 5.5eV. Examples of the copolymer are F8T2 (ionization potential is 5.5eV) or TFB (U.S. Patent No. 5,777,070). Other suitable pore-transporting polymers have Homopolymer of polythiophene derivatives with ionization potential, such as polythiophenes with alkoxy groups or ratified side chains (R.D. McCullough, 1998, Issue 10, Advanced Materials, page 93). Except for hole-transport semiconductor polymerization In addition to other substances, dissolvable electron transport materials can also be used. This requires a high electron affinity of greater than 3eV, preferably greater than 3.5eV, to avoid residual gas impurities such as oxygen to be collected as a carrier. Suitable materials can include Solutions can handle small electron-transporting semiconductors (produced by Η · E_ Katz et al., Issue 404, Nature, page 478, 2000), or polyfluorene derivatives with incompletely fluorinated side bonds of electrons AB-type block copolymer with a well-defined trapezoidal A block and a high ionization potential higher than 5.5eV ', and an electron transport B which increases the electron affinity of the copolymer to a value higher than 3eV For blocks, preferably higher than 3.5eV is also suitable at the same time. Examples of suitable A blocks are fluorene derivatives (U.S. Patent No. 5,777,070), indigo derivatives (2000 by S. Setayesh) Issue 33 of Macromolecules, 2016), phenylene or trapezyl phenylene derivatives (issued by J. Grimme et al. 1995, Issue 7 Adv. Mat ^ 292). Electronic Journal 21,- -: ------------ Order --------- Line (Please read the precautions on the back before filling this page) This paper size _ (CNS) A4 (210 χ 297 ^) I229884 A7 B7 V. Description of the invention (The examples printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Transport and Economics for the production of block B are benzodiazepine derivatives (U.S. Patent No. 5,777,070), perylene derivatives Derivatives, naphthalenetetracarboxylic acid difluorene imine derivatives (derived from HE Katz, Nature404, page 478, published in 2000) or fluorinated thiophenes In order to operate the logic circuit quickly, the channel length of the transistor and the overlap between the source / drain and gate should be as small as possible, which is typically a few microns. The most important dimension is L because the transistor circuit The operating speed is about a ratio of L · 2. This is particularly important for semiconductor layers having relatively low fluidity. With today's inkjet printing technology, it is not possible to achieve high-resolution prototyping, and even the JP technology, which has the current level of technology, is limited to the external size of 10-20 lm (Figure 6). If faster operation and denser appearance packaging are required, then a technique that allows finer appearance resolution must be used. The technique described below will use the interaction of the ink surface to define inkjet droplets on the substrate surface. This technique can be used to achieve smaller channel lengths than can be achieved with conventional inkjet printing methods. This qualification technique can be used to allow a fine resolution deposition of a deposition material on a substrate. The surface of the substrate is first treated so that selected portions thereof are relatively attractive and relatively waterproof to the desired deposition material. For example, the matrix may be patterned in advance so that it is partially water-repellent in some areas and partially hydrophilic in other areas. Due to the high-resolution and correct-reading pre-modeling steps, subsequent depositions can be correctly defined. This paper size applies the Chinese National Standard (CNS) A4 regulations ^^ (Please read the precautions on the back before filling in this page) -------- Order --------- line · 22 1229884 A7

Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. An example of prior styling is shown in Figure 7. Fig. 7 shows the formation of the same device in Fig. 1 (c), but with a particularly thin channel length. Identical components are denoted by the same reference numerals as in Fig. 1 (c). Figure 7 (a) shows a method for making a pre-patterned substrate. Figure 7 (b) shows the printing method and ink limitation on this pre-patterned substrate. Before the source-drain electrodes 2 and 3 are deposited, a thin polyimide layer 10 will be formed on the glass sheet 1. The polyfluorene layer is very well patterned to remove it where the source-drain is formed. The removal step can be done by a photolithography process to allow good appearance definition and correct reading. In one example of this process, polyimide can be covered with a layer of photoresist material 11. The photoresist material can be patterned by photolithography to remove it where the polyimide is removed. Next, polyimide is removed using a process that is robust to photoresist materials. The photoresist material can then be removed to leave the polymorphimide properly patterned. Polyimide 'will be selected because it is relatively water-repellent and the glass substrate is relatively hydrophilic. In the next step, a source-deposited PEDOT material will be deposited on the hydrophilic substrate region 12 by inkjet printing. When the ink droplets diffused in the glass substrate area touch the edge of the water-repellent polyimide area 10, the ink will be discharged and will not flow to the water-repellent surface area. Through this limiting effect, the ink is deposited only in the hydrophilic surface area, and the high-resolution pattern with a small band gap and the transistor channel length of less than 10 μm are 23. This paper size applies the Chinese National Standard (CNS) A4 specification ( 210 X 297 public love) ^ Ί. Order -------- line 丨 · !! (Please read the notes on the back before filling out this page) 1229884 A7 V. Description of invention (浼 can be defined (No. 7 (b). An example of the process of removing polyimide after removing polyimide, or it can be applied to enhance the relative surface effect, is shown in Figure 7 (a). Poly The imine layer 10 and the photoresist material 11 will be exposed to oxygen. Oxygen will etch the thin polyimide layer (500 A) faster than the thickness (1.5 μΓΠ) photoresist material layer. Before removing the photoresist material, by exposing to oxygen, the exposed glass surface 12 in the source-drain region will be quite hydrophilic. It should be noted that during the process of removing polyimide, The surface of the polyimide is protected by a photoresist and maintains water resistance. If necessary, Exposed to CF4 gas, the surface of polyimide can become more water-repellent. C f4 gas will fluorinate the surface of polyimide, but does not interact with the hydrophilic glass substrate. This additional gas treatment method can Perform before removing the photoresist material, so that only the side wall of polyimide pattern 10 will be fluorinated, or after removing the photoresist material. 7059 glass treated with PEDOT / PSS and 〇2 plasma The contact angle is 0 g | ass 40. Compared with the contact angle of 0 Pl «70 ° ~ 80 ° on the surface of polyimide. The contact angle of PEd〇t / PSs in water with fluorinated polyimide is 120. When PEDOT / PSS is deposited from an aqueous solution onto a previously patterned polyimide layer as described, PEdot / pss ink will be confined to the source-drain region, even if the channel length L It is only a few microns (Figure 7 (b)). 24 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Public Economics and Economic Affairs)

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1229884 The definition of ink droplets depends on the contact angle 0 between the edge of the water-repellent surface and the hydrophilic surface area, and will be related to the interfacial tension of the air / polyimide and the ink / glass interface, respectively 1 and 2, And the surface tension port 3 in the ink / air interface. Ignoring the effect of polyimide sidewalls, an estimate will be obtained from the public ScoS0 = (匚) 1- [112) / 匚] 3 of YoUng (Figure 7 (b)). Preferably, the deposition of the 'ink droplets 13 will occur on the hydrophilic matrix region 12, a distance d between the center of the droplets and the margin of the polyimide. On the one hand, d must be small enough to reach the edge with the extended ink, and the PEDOT film will extend directly to the edge of the polyimide. On the other hand, d must be large enough so that the rapidly expanding ink does not overflow into the water-repellent surface area. This will increase the risk of PEDot being deposited on top of the polyimide region 10 defining the TFT channel 'and will cause a short circuit between the source and the drain. For PEDOT droplets with a solid content of 0.4 ng, with a lateral pitch of 12_5 μm between two consecutive droplets, deposited on 7059 glass treated with 02 gas plasma, a value of c ^ 30_4pm has been suitable. The optimal value d depends on the wetting properties on the surface, but also on the deposition pitch, which is the lateral distance between subsequent deposited droplets, and on the drying time of the solution. The polyfluorene layer 10 can be used simultaneously as the adjustment layer 9 (FIG. 1 (b)), in the example of the liquid crystal-like semiconductor polymer 4. Polyimide layer can be rubbed mechanically. The gate electrode 6 can be formed by a one, T on the top of the gate insulation layer 5, -------- order --------- line. (Please read the precautions on the back before filling (This page) 25

This paper size applies to China National Standard (CNS) A4 (21〇 X 297 public love) 1229884 A7

V. Description of the Invention (The patterned patterning layer 14 is similarly limited, and it provides an attractive and drained surface area for the solution deposited by the gate electrode. The patterning layer 6 can use a source / drain pattern. Adjust to minimize the overlap of source / drain and gate (Figure 7 (c)). Materials other than polyimide can also be used for the pre-modeling layer. Other than photolithography can also be used Appropriate pre-modeling techniques other than printing. Figure 8 shows the structural capabilities of relatively water-repellent and hydrophilic layers to limit the liquid, ink, and ink deposited by inkjet printing. Figure 8 shows the inclusion of slenderness The light micrograph of the polyimide 10 matrix has been treated as described above to become relatively water-repellent, and a relatively large area of the bare glass substrate 12 treated as described above has been made relatively hydrophilic. The source and electrode have been deposited using inkjet printing, which is a series of droplets flowing in lines 2 and 3 close to the strip 1 0. Although the inkjet material will show low contrast, it can be removed from the deposition Projection of the end surfaces 2 and 3 of the material It can be seen in the final form that the deposition material has been limited by the strips 10, even if the thickness of the strips is less than 5 μm. Figure 9 shows the spray in the area around the polyimide strips. A photo of the ink deposition process. The image will be taken with a stroboscopic camera fixed under a transparent substrate. The edges of the polyimide pattern 10 appear as white lines. Ink droplets 21 are injected from the nozzles of the inkjet head 20 and stay at Polyimide strips 10 are centered at a distance of d. An image similar to this can be used for inkjet deposition of strips 10 corresponding to 26. This paper is sized for China National Standard (CNS) A4 Specifications (21G χ 297 public love) (Please read the precautions on the back before filling out this page) -------- Order --------- Line-Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 1229884 A7

V. Description of the invention (Rabbit correct area adjustment, and can be used to automate the area adjustment process using pattern recognition (see the description below). Figures 10 and 彳 彳 are shown as Figure 7 (formed in magic mode and have Channel length ί_ = 20μηι and 7μηι transistor output and conversion characteristics, which are defined using the differential wetting process described above. In the two cases, the channel width W is 3mm. Figure 10 shows the characteristics of the output terminal of the 20μΓΠ device Figure 10 (b) shows the output characteristics of a 7μΓγι device. Figure 11 (a) shows the conversion characteristics of a 20μιτι device. Figure 11 (b) shows the characteristics of the conversion terminal of a 7μπγ device. The 7μΓγΊ device is shown in Xiaoyuan The pole-drain voltage has a characteristic short-channel state with reduced current 'and limited output conductivity in a saturated state. The short-channel device's mobility and on-off current ratio will be similar to the long-channel device's mobility described above. Ratio to switching current, ie, μ = 0.05.05_0.01cm2 / Vs, and | ON / | OFF = 1〇4-1〇5. An alternative technique for manufacturing a matrix pre-type is to have a self-organizing pattern. Functionalization of the surface of a glass substrate containing a monolayer (SAM), such as SAM, which contains a hydrophobic or fluoro group such as tri-fluoroacetic acid-trimethoxysilane, or a polar group such as alkoxy SAM can be modeled using appropriate methods, such as UV exposure through a shadow mask (Langmuir 2000, published by H. Sugimura et al. 2000, p. 855), or micro-contact printing (by Brjttain et al., In Physics World May, 1998, page 31, published in 1998). The pre-modeling of the substrate is compatible with the above process flow, because 27 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ----- (Please read the precautions on the back before filling out this page) Order --------- Line · Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperative! 229884 A7 ~ ---------V. Description of the invention (The pre-modeling of the dragon is performed before the layer deposition of the TFT. Before the gate deposition, similar techniques can be used to pre-type. Sample the surface of the gate insulation layer or the surface modification layer to achieve a smaller weight Capacitance. As shown in FIG. 7 (c), the gate electrode 6 can be defined by the patterning layer 14. One possible embodiment of the pre-modeling is a micro-contact printing method, or a self-assembled UV of a single-layer body Optical patterning, which includes a chlorite or methoxide group that is a hydrocarbon group bonded to the PVP gate insulating layer. With a pre-typed substrate, it is possible to make TFTs and vias as disclosed in the present invention. The manufacturing process is used to manufacture high-speed logic circuits. One of the important requirements for manufacturing transistor circuits on a large area is to record and adjust against the deposition of the matrix pattern. It is particularly difficult to make adequate recordings on an elastic substrate, as distortions will appear over a large area. The high-resolution inkjet printing process developed here will be suitable for correct recording over a large area, even on a plastic substrate, because the position of the inkjet print head can be locally adjusted relative to the pattern on the substrate ( (Figure 9). This local adjustment process can be automated using pattern recognition technology, which uses the image as shown in Figure 9. In order to use the above-mentioned device to form a multiple transistor volumetric body circuit, it is desirable to be able to make a through-hole interconnect directly through the thickness of the device. This allows the circuit to be formed particularly densely. One way to make this interconnect is to use vias formed by solvents, as explained below. This method uses the solution processing of the above TFTs. The paper size is applicable to the Chinese Standard (CNS) A4 specification (21G X 297 public love). ^ -------- t ---------- I (Please read the notes on the back before filling out this page) 1229884 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs

A7 B7

The fact that the physical layer has not been converted to an insoluble form. This can form via openings by local deposition of the solvent. In order to make a through hole formed by a solvent (Fig. 12 (a)), a suitable amount of a proper solvent 29 is locally deposited on the top of the layer, and a through hole is formed through the top end. The solvent is selected so that it can dissolve the underlayer 'and the through hole can be formed through the underlayer. By continuous dissolution, the solvent will penetrate the layer until through-holes are formed. The dissolved material will be deposited on the wall W of the through hole. The type of solvent and the method of deposition can be selected according to the individual application. However, the three better choices are: 1. The solvent and process conditions are such that the solvent will evaporate or can be easily removed so that it does not interfere with subsequent processing and does not cause excessive or incorrect dissolution of the device ; And 2. The deposition of the solvent is through a selective process, such as 丨 "p, in which the correct solvent control amount can be correctly applied to the desired area of the substrate; and the diameter of the 3 through-hole will be affected by the solvent droplets. The surface tension and the ability of the solvent to wet the substrate are affected; and 4. The solvent cannot dissolve the underlayer, which is where the electronic connection occurs. Fig. 12 (a) shows the deposition of droplets 29 of the methanol solvent on the transistor device formed as part of the general pattern of Fig. 1 (C) (each droplet contains 20 ng). Part of the device of FIG. 12 (a) includes a thick pvp insulating layer 28, a F8T2 semiconductor layer 27, a PE DOT electrode layer 26, and a glass 29.

This paper size applies to the national standard of Yin (CNSM4 specification (210 X 297)

ά! φ!] ------------- ^ --- · ----- (Please read the notes on the back before filling this page) -------- Order ---- 1229884 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (Effective glass substrate 25. In this example, what is desired is to form a through hole through an insulating PVP layer. Methanol is selected as the solvent, Because it easily dissolves PVP 'Because the dagger can be easily evaporated, it will not hinder subsequent processing; and because it is satisfactory for the wetting properties of PVP. In order to form a through hole in this example, a JP print head It is moved to the position on the substrate, which is the position where the through-holes are intended to be formed. Subsequently, the methanol droplets of the appropriate size and necessary amount from the IJP print head are continuously dripped until the through-holes are completed. Continuous selection will be selected The period between the droplets is compatible with the rate at which methanol dissolves the device layer. Preferably, each droplet can be completely or nearly completely evaporated before the next droplet is deposited. It should be noted that When the via hole reaches the bottom non-polar semiconductor layer, the etching action will stop so that The underlayer will not be removed. Other solvents such as isopropanol, ethanol, butanol or propanol can also be used. In order to achieve high yields, it is desirable to complete the vias with a single solvent droplet For a 300 nm thick film with a droplet size of 30 pl and a diameter of 50 μm, the solubility of the layer in the solvent needs to be less than 1-2% by weight per volume. If it is necessary to form a through hole with a single droplet, A high boiling point is also desirable. If PVP 1,2-dimethyl_2_midsigma (DMI) is used, a boiling point of 225 ° C can be used. Figure 12 (b) shows sequential drops The effect of multiple drops of methanol falling on the position of the via. The right panel shows the micrograph of the device after 1, 3 and 10 microdrops. The left panel shows the same device that measures the Dektak surface profile across the via when it is formed (Through holes in each panel ---- r ---- ^ ------------ order --------- line--if (Please read the Note: Please fill in this page again) 30 1229884 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs --- ____B7_____ V. Description of the invention (the position of addition is usually marked at T position). When several drops of methanol are sequentially deposited at the same location, a pit will open in the pvp film. When subsequent droplets are performed, the depth of the pit will increase, and after about 6 drops, the surface of the underlying FBT2 layer will be Uncovered. The dissolved pvp material is deposited on the side wall W of the via. The diameter of the via is 50μΓγι, which is limited by the size of the droplets. This size is appropriate for many applications, such as logic circuits And large display area displays. For some applications, smaller through-holes will also be required, such as high-resolution displays, which can use smaller droplet sizes, or the substrate surface can be pre-shaped by an appropriate technique. To define droplets on the surface 'as described above. Other solvents can also be used. It will be seen from the surface profile measurement that the formation of the through hole will cause the material to dissolve and be shifted to the edge of the through hole, which will be maintained after the solvent has been evaporated (shown in w in Figure 12 (b)) ). It should be noted that, compared with that shown in Fig. 2 (b), the formation of the offset material is smoother, and the X and y axes in the 12 (b) contour image will be dissimilar scales ( The unit of X is pm and the unit of y is A). The combination of the number of dripping solvent droplets and the comparison of the solvent evaporation speed with the dissolution matrix speed can control the depth of the vias. The deposition environment and substrate temperature may affect the evaporation rate. Material layers that do not dissolve or only slowly dissolve in solvents will be used to limit the depth of dissolution. Since the layer sequence of the TFT includes replacement of polar and non-polar layers, it is possible to choose a mixture of solvent and solvent, so as to stop the rest of the time (Please read the precautions on the back before filling this page) J. ---- ----- Order --------- line · h This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 1229884 Printed by A7 B7, Employee Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs V. Description of the invention (219 to a well-defined depth. In order to make contact through the via, a conductive layer can be deposited thereon so that it extends into the via, and electrons are carried on the bottom of the via. Fig. 13 (a) shows the device of Fig. 12 (a), but does not include the gold electrode formed after the through-hole manufacturing as described above. 25 ° Fig. 13 shows on curve 30, between the bottom PEDOT Current and voltage characteristics measured between electrode 25 and a conductive electrode 29 deposited on top of PVP gate insulating layer 28. The diameter of this via is 50 μηη. For comparison, curve 31 shows a reference sample where the electrode is located at the electrode The overlap between the top and bottom of the Existing. This feature clearly shows that in the absence of a through-hole, the current through the through-hole will be several times higher than the leakage current through the gate insulator. The conductivity of the PEDOT electrode is measured through the through-hole The current is limited, as seen in conducting conductivity measurements of individual PEDOT electrodes. It is not limited by the resistance of the via, so that the lower limit estimate of the via resistance Rv can be derived from these measurements. Obtained: Rv < 500kD. The method for forming the through hole in Figure 12 above will be directly applicable to the empty type device without diffusion barrier (such as in Figure 彳) and after the through hole is opened. No device for diffusion barrier deposition. Figure 14 (a) shows a device in which a through-hole has been formed, and the gate will then be deposited without an intermediate diffusion barrier. Figure 14 (b) shows a different device. After the through hole is formed, the gate U -------- ^ --------- ^ ---- (please first (Read the notes on the back before filling out this page) 32

1229884 A7 V. Description of the invention (Before the deposition of electrode 6, a diffusion barrier polymer 7 has been formed. Under this condition, the diffusion barrier layer needs to exhibit good charge transport properties in order to minimize the through-hole resistance Rv. A suitable The diffusion barrier is a thin layer TFT, as shown in Figure 5 (a). If a lower contact resistance is required, then the semiconductor layer will also be removed at the location of the via. After the diffusion barrier is formed, it can be compared The diffusion barrier 7 and the semiconducting polymer 4 can be locally dissolved using a good solvent IJP deposition, for example, xylene in this example. By mixing a solvent that is excellent for the semiconductor and the insulating material, the bilayer can be Simultaneous dissolution. Figure 14 (c) shows a device that performs the above process after deposition of the gate. By increasing the contact angle of the pre-dissolved solvent mix on the layer, the solvent mix can be used to reduce Radius of the through hole. An alternative to forming through-hole interconnects and subsequently depositing conductive materials for bridging is to deposit a material locally, so that beans can be localized: ground Fabricate the erbium substrates so that they are conductive: One example is a solution containing a mobile dopant. Local | jp deposition, which can diffuse into one or more layers. This is shown in Figure 14 (d) , Where region 32 shows a conductive material treated with a doping f. The dopant may be a small molecule, such as N, N · _diphenyl · N, N'-bis (3- Methylphenylphenyl (11 ,, phenyl) _44 dipyridylamine (TPD) is a one-month-old female. The dopant is preferably transported in a solvent state. The method of forming a through hole through the electrical layer can be Used to connect 1 paper size _, _ Fresh (CNS) A4 Regulation 33 1229884 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ------- B7_____ 5. Description of the invention (31 TFT gate to the bottom The source or sink in the pad body, for example, a logic converter device as shown in Figure 15. In most logic transistor circuits, similar through-hole connections are required. Figure 16 shows two Features of an enhancement-load converter device formed by a normally-closed transistor device. Features of two transistors The two converters of channel width to channel length ratio (W / L) will be displayed (Figure 35 is a 3: 1 ratio, and Figure 36 is a 5: 1 ratio). It can be seen that when the input voltage changes from a logic low When the voltage is switched to a logic high voltage, the output voltage is switched from a logic high voltage (_20v) to a logic low voltage (wV) state. The gain of the converter, that is, the maximum slope of the feature will be greater than 1, which is more complicated to manufacture Circuits, such as the necessary state of a ring oscillator. The vias described above can also be used to provide electrical connections between interconnecting lines in different layers. For complex electronic circuits, multiple levels of interaction are required. This can be fabricated by depositing a series of interconnects 72 and different dielectric layers 70, 71, which are deposited from a compatible solvent (Figure 15 (d). The through hole 73 may be subsequently formed by the method described above to provide an interconnection line for an automatic last stop instruction. Examples of suitable dielectric materials are polar polymers (70) 'such as pVp and non-polar dielectric polymers (71) such as polystyrene. They can be deposited from alternative polar and non-polar solvents. By local deposition of a good solvent for the individual dielectric layers, the dagger can be opened and the underlying dielectric layer will be provided with an etch stop layer. When selecting materials and deposition processes for the above-mentioned types of devices, it should be noted that if each layer is essentially insoluble, the Chinese National Standard (CNS) A4 specification (210 X 297) )

-I ---- Meal (please read the precautions on the back before filling this page) II Order --------- line · 1229884 A7 V. Description of the invention Many advantages can be obtained if it is deposited in the middle. In this way, the subsequent layer can be established by the solution processing method. One of the methods to choose simplified materials and process steps is to alternately deposit from polar and non-polar solvents. Two or more layers, such as the layered body sequence exemplified above. In this way, the multilayer body device 'contains soluble, conductive, semiconductor, and insulating layered bodies and can be easily formed. This will solve the dissolution problem and the underlying layer The problem of swelling. The above device structure, material, and process are for illustration. They can also be changed. Other device configurations besides the top gate configuration shown in Figure 1 can also be used. Alternative configurations For the more standard bottom gate configuration shown in Figure 17, where it may be possible to merge the diffusion barrier 7 and the surface modification layer 8 if necessary. In Figure 17, components similar to Figure 1 will be the same Number generation Table. Other device configurations with different layer sequences can also be used. Devices other than transistors can also be formed in a similar way. By any conductive polymer, PEDOT / PSS can be replaced, which can be deposited from solution. Examples include polyaniline or polypyrrole. However, some attractive features of PEDOT / PSS include: (a) dopants (pss) of polymers with low diffusivity; (b) excellent thermal stability and air Stability, and (c > 51eV work function, which is quite in line with the ionization potential of the common hole-transporting semiconducting polymer, which allows ejection of effective pore-like charge carriers. (Please read the precautions on the back before filling out this page) · Order --------- Line-Printed by Employee Consumption Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 35 1229884 A7 B7 V. Description of Invention (Printed by Employee Consumption Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs

Effective charge carrier injection is important, especially for short-channel transistor devices with a channel length L < 10pm. In this device, the source-drain contact resistance effect may limit the TFT current to a small source-drain voltage (Figure 10 (b)). In devices with control channel lengths, it has been found that the emission from the PEDOT source / drain will be more efficient than that from the inorganic gold electrode. This shows that an ionization potential of a polymer source-drain electrode that is quite suitable for the ionization potential of a semiconductor will be preferably an inorganic electrode material. The conductivity of PEDOT / PSS deposited from an aqueous solution (Saytron P) will be on the order of 0. 1-1 S / cm. With formulations containing solvent mixtures, higher conductivity up to 100 S / cm can be achieved (Sayer CPP 105T, containing isopropanol and methyl-2-pyrrolidine (NMP)). In the latter state, it will be noted that the solvent combination formulation will be compatible with the solubility requirements of the layer sequence. For applications that require more local conductivity, other conductive polymers or solution-processible inorganic conductors, such as colloidal spiral floats of liquid metal inorganic particles, will be used. The processes and devices described herein are not limited to devices made from solution-processed polymers. In a circuit or display device (see below), some conductive electrodes of TFTs and interconnects can be formed from inorganic conductors, for example, by printing on a colloidal suspension or depositing on a preformed substrate plating. In devices where not all layers are deposited from solution, one or more PEDOT / PSS parts can be replaced with a soluble conductive material, for example

This paper size applies to China National Standard (CNS) A4 (210 X 297 male f)

" ^ -------- Order ------ I (Please read the notes on the back before filling in this page) Line-1229884 A7 B7 Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs Description (like a vacuum-deposited conductor. Semiconductor materials that can be processed with other solutions can simultaneously replace the semiconductor layer. Possibility includes small conjugated molecules with solubilized side chains (No. 1 published by JG Laquindanum et al. In 1998 120 J. Am. Chem. Soc_p.664); semiconductor organic-organic-free hybrid materials, which self-assemble in solution (CR. Kagan et al., 1999, Issue 286, Science Magazine, p.946 ); Or solution-deposited inorganic semiconductors such as CdSe nanoparticles (B. A. Ridley et al., Issue 286, Science Magazine, 1999, p. 746). Samples can be made using techniques other than inkjet printing Appropriate techniques include soft lithographic printing (applied by J, A. Rogers et al., Issue 75, Appl_Phys_Let, page 101, published by S. Brittain, et al., 1998 Physics world may issue page 31), Sieve Printing method (No. 9 Chem_ Mat. P. 12999 published by z_ Bao et al., 1997), and light lithography type prototyping method (see WO 99/10939) or plating method. Inkjet printing is It is considered to be most suitable for having a large area patterned with excellent readability, especially for elastic plastic substrates. In addition to glass plates, the device can be deposited on other substrate materials, such as plexiglass or an elastic plastic substrate For example, polyether 飒. The material is preferably in the form of a flat plate, and is preferably a polymer material, and can be transparent or elastic. Although preferably, using solution processing and printing technology, ( Please read the note on the back? Matters before filling out this page) --------- Order --------- line · 37 1229884 A7 B7 V. Invention Description (瓮 Intellectual Property Bureau, Ministry of Economy Employee consumer cooperatives print and deposit layers and components of all devices and circuits, and one or more components, such as semiconductor layers, can be deposited using vacuum deposition techniques and patterned using a light lithographic process. The TFT device can be a complex electrical device. Or a part of a device, one or more of which can be integrated with each other or with other devices. Examples of applications include logic circuits and active matrix circuits of displays or memory devices, or gate array circuits defined by users. The basic composition of the logic circuit is the converter in Figure 15. If all the transistors on the substrate are empty or cumulative, there are three possible configurations. The empty-load converter (fig. 15 (a)) is suitable for devices that are normally turned on (fig. 1 (c) and 3), while the enhanced-load configuration (fig. 15 (b)) uses The transistor is normally turned off (Figure 1 (a / b) and Figure 4). Two configurations require a through-hole, which is between the gate of the transistor and its source and non-electrode. An alternative configuration is a resistive load converter (Figure 15 (c)). The latter device can use a printed PEDOT line with sufficient length and conductivity as the load resistance. By reducing the conductivity of PEDOT, for example, by increasing the PSS ratio to PEDOT, the length of the resistance line can be minimized. It is clear that using the TFT and via manufacturing process described above, it is possible to manufacture converter devices and more complex logic gates. The solution-processed TFTs as described above can be used as pixel switching transistors for active matrix displays, such as liquid crystal displays (LCDs) or electrophoretic displays (No. 1 published by B.Comiskey et al. ? Please fill out this page again)-^ 1 -J. --------- Order --------- line. 38 I229884 A7 B7 V. Description of Invention (Exempt from 394 Nature Miscellaneous 253), one of the appropriate circuits will be shown in Figure 18 (a); and a light-emitting diode display (28 (^ jScience, page 1741) by h_ Siiringhaus et al., 1998) 'One of the appropriate circuits It is shown in Fig. 18 (b); or the active matrix addressing element of the memory device, such as a random access memory (RAM). In Figs. 18 (a) and (b), it can be formed from the above Transistor T1 and Transistor T2. Appearance feature 40 represents a display or a memory element with current and voltage supply pads. Possible device configurations for controlling the electrode voltage of an LCD display or an electrophoretic display will be shown on page 19. Figures, which are similar to the first, are represented by the same component numbers. In FIG. 19 (for example, FIGS. 7, 14 and 17), the gate insulating layer may include a multilayer body structure including a diffusion barrier and a surface modification layer, as shown in FIG. 1 (a). Please refer to FIG. 18 In the figure, the source and gate electrodes 2 and 3 of the TFT are connected to the data line 44 and the address line 43 of the active matrix made of different conductive materials to achieve sufficient conductivity for a longer length. The drain of the TFT 3 It can be the pixel electrode 41. From different conductive materials, the pixel electrode can be formed, as shown in Figure 19. In the device that depends on the electric field instead of the charge carrier, it is not necessary for the electrode 41 to directly contact the display element 40, for example Liquid crystal display or electrophoretic display, etc. In this configuration, all pixel areas occupied by TFTs and interconnect lines must be kept small to achieve sufficient aperture ratios and reduce display elements on data lines 43 and address lines 44 The potential between 40 and the signal interferes with each other. 39 Paper size_ t_two (CNS) A4 size ⑽ x297 public issue 1229884 A7 V. Description of the invention (317 The configuration in Figure 19 (b) is more complicated. However, the whole Most of the pixels or pixel areas Available for TFTs and interconnects, and with pixel electrodes 41, display elements will be shielded from signals on data lines 43 and address lines 44. The fabrication of the configuration requires an additional dielectric filled with conductive material 45 The electrical layer 42 and a through hole are used to connect the pixel electrode 41 to the drain electrode 3 of the TFT. The through hole can be made using the procedure described above. It should be noted that in this configuration, the aperture ratio will be maximized and the Up to 1000/00. This configuration can be used in display applications with backlight at the same time, such as transmissive LCD displays, because the all-polymer TFTs made here are highly transparent in the visible range. Fig. 20 shows the optical absorption spectrum measured on the F8T2 polymer TFT, in which the liquid crystal-like semiconductor polymer is deposited, and the polymer chains appear to be uniaxially aligned on the rubbed polyimide adjustment layer, which can simultaneously As a high-resolution printing method and patterning. It can be seen that due to the relatively high band gap of F8T2, the device is highly transparent in most visible light ranges. If the half layer, such as F8 or TFB or other polyfluorene derivatives (U.S. Patent No. 5,777,070), has a band gap higher than that used, more southern transparency can be achieved. The adjustment of the polymer chain will increase the anisotropy of the light, so that the polarization of the light parallel to the adjustment direction (indicated by " 丨 丨 " in the figure) can be absorbed more strongly than the polarization is perpendicular to the adjustment Directional light (indicated by " 丄 " in the figure). The guide uses a normal polymer chain for the polarizer to adjust the direction, which is between the glass substrate and the stupid light. The color anisotropy of the light can be used in the LCD display. The paper size is in accordance with the Chinese National Standard (CNS). A4 size (210 X 297 public love

(Please read the precautions on the back before filling out this page) .Refer to -------- Order --------- line- ♦! 1229884 A7 B7 Printed by the Employees' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs Further increase the light transparency of TFTs. Under polarized light, the transistor device will appear almost colorless in visible light if the thickness of the F8T2 layer is less than 500A. All other layers of TFTs containing PEDOT will have low light absorption in the visible spectral range. Another advantage of the low light absorption of the semiconductor layer is the reduced sensitivity of the TFT characteristics to visible light. In the case of amorphous dream TFTs, a black matrix must be used to avoid a large turn-off current under light. In the case of polymer TFTs with a wide band gap, it is not necessary to protect the TFTs from the surrounding light and the backlight of the display. The configuration in Fig. 19 (b) is also suitable for the driving transistor " π of the LED display (Fig. 18 (b)), because with the source_ > and In the fabrication of the inter-array, using the entire area under the pixel electrode 41, it will allow the driving current of the TFT to increase. Alternatively, the bottom gate TFT configuration in Figure 17 can be used in all of the above applications (Figure 19 (c)). One of the important technical issues for manufacturing active matrix circuits is the contact between the PEDOT / PSS TFT and the pixel electrodes 2, 3, 6 and the metal interconnection lines 43, 44, and 41. Due to its strong acidity, pEDA is not compatible with any common inorganic metals, such as Ming. When in contact with PEDOT / PSS, the nicks are susceptible to oxidation. One of the possible solutions is to make interconnects and pixel electrodes from "Indium Tin Oxide (丨 T0)", or from other materials that are more stable in this environment, or use an appropriate barrier layer. Choi_tsuka standard (cns) a4 (Please read the notes on the back before filling this page) —ml -J. --------- Order --------- line-41 Ministry of Economy Printed by the Intellectual Property Bureau employee consumer cooperative 1229884 A7 ----- --__ B7 V. Description of the invention (for application display, it is also better to manufacture TFTs with small channel length, using 10 shown in Figure 19 as 10 Printed on the preformed substrate, as described above. If the pre-controlled pixel element is not a display element, but a memory element, a similar device configuration of an active matrix transistor switch can also be used. For example, capacitors or diodes, as in the example of dynamic random access memory. In addition to conductive electrodes, some layers can be modeled using direct printing methods, such as screen printing or P. Section Figure 21 (a) (where the same elements as in figure) use the same (Representation of the part number) shows a device in which the active layer islands of the semiconductor layer 4 and the gate insulating layer 5 can be directly printed. In this example, no through holes are required, but direct printing must be used to make the appropriate gate Connection of electrode pattern 6. In areas where the addressing or interconnecting lines 43, 44 overlap the thick islands of the dielectric polymer 46, it may be necessary to print to provide electrical insulation (Figure 21 (b)) Multiple devices formed as described above can be formed on a single layer and interconnected by conductive layers. These devices can be formed on a single level or more than one level, and some devices are formed on other devices Using the above-mentioned interconnecting strips and vias, a compact circuit configuration can be formed. The technology developed here to manufacture inkjet printed transistors, vias and interconnects can be used in inkjet printing To build integrated electronic circuits. Pre-42 can be used with an array of hydrophilic and water-repellent surface areas.

(Please read the precautions on the back before filling in this page), · · · Order --------- line-1229884 A7 B7 V. Description of the invention (also: the channel length of the soil crystal boundary and The width X of the interconnect lines. The substrate can simultaneously contain an array of highly conductive metal interconnect lines. Using a hybrid of inkjet printing and deposition of a continuous layer from a solution, the array of transistor devices can be customized at The customized channel width, and / or boundary can be used to form an integrated circuit by forming an electronic connection between the transistor pair and the interconnect, and using an inkjet printing method of vias and conductive lines. What's exciting is that the prefabricated substrate may already contain components of one or more transistor devices. The substrate may include, for example, an array of complete inorganic transistor devices with at least one exposed electrode. In this example, '胄The inkjet manufacturing process T of the bulk circuit includes the use of a spray-binder P brushed through holes, interconnect lines, and isolation pads to form an electrical connection between the transistor pair and the deposition of a single or multiple level interconnection scheme (please (See Figure 15 (d)). In addition, the electronic circuit can contain 70 other main and passive circuits, such as a display or a memory element or a capacitive or resistive element. Using the technology described above, units with multiple transistors can be formed and subsequently configured for For subsequent use, use a solution-based processing method. For example, a substrate with multiple transistors 50, as shown in Figure 1 (a), (b), or (c) in the form of a gate array Type can be formed on a plastic board (Figure 22). Other devices, such as diodes or capacitors, can be formed on the board at the same time. The board can then be placed in an inkjet printer, It has 43 paper sizes to form the Chinese National Standard (CNS) A4 specification (210 X 297 public love) 1229884

V. Description of the Invention (4 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

A print head of a suitable solvent (such as methanol) for the through-holes 52, or a suitable material (e.g., PEDOT) for forming conductive traces 53 and filling the through-holes. The inkjet printer can be operated under the control of a suitably programmed computer. # 4 The computer has information about the configuration and location of the transistors on the plastic board. Subsequently, the combination of the step of forming vias and interconnects through an inkjet printer can be used to configure circuits and interconnect transistors in a desired manner to perform desired electronic or logic functions. This technology therefore allows the use of small and inexpensive devices to form logic-specific circuits on the substrate. Examples of such circuits are the printing of active electronic tickets, luggage cards, and identification cards. The ticket or card printing device can be loaded with a variety of non-assembled units, each unit contains a substrate carrying multiple transistors. The ticket printing device includes a computer, which can control an inkjet printing as described above. And an electronic circuit that can identify valid functions of the ticket. When it is necessary to print the ticket roll, the printing device will use printed through holes and conductive materials to configure a substrate for the appropriate electronic circuit so that the transistors on the substrate are properly assembled. The substrate can be subsequently packaged, for example, sealed with an adhesive plastic plate, and the electrical connection terminals 54 and 55 are exposed. Tickets will be assigned later. When the ticket is to be verified, the application is input to one or more inputs and the circuit output on one or more outputs is monitored to verify its function. Tickets can preferably be printed on an elastic plastic substrate so that they can be conveniently used as a ticket. User-defined circuits other than the price or labeling purpose ---- ^ --- ί ------------ Order --------- line (please read the (Please fill in this page again)

This paper scale sword + Guan Family Standard (CNS) A4 specification (210 X 297 public) 1229884 V. Description of the invention (must also be made in a similar way. Use, for example, wireless band frequency light emission by remote speculation The verification and reading of the circuit can also be ordered (Physics World in the March 1999 issue, page 31). By performing simple inkjet printing on a standard array, the end user's ability to define the circuit will be Provide greater flexibility than factory-designed circuits. The present invention is not limited to the examples described above. The present invention will include all the novelty and progress of the road disclosed, and all novel and progressive features of the disclosed features. The applicant would like to note that the present invention may include all explicit or implied features and combinations thereof, and is not limited to the scope of the roads disclosed above. In summary, as long as it does not deviate from the scope of the invention For those skilled in the art, there can be various changes. Wire glass substrate source drain active semiconductor polymer / liquid crystal semiconductor polymer stand-alone reference table 5 Gate Edge layer / PVP insulation layer 6 Gate / patterning layer 7 Diffusion barrier polymer 8 Surface modification layer 9 Polyimide layer 45 This paper size is applicable to China National Standard (CNS) A4 specification (21〇X 297 public love) I— ~ —I—Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 1229884 A7 _B7 V. Description of the invention (4¾ 10 thin polyimide layer / poly 45 conductive material 醯 imine type 46 dielectric polymer 11 photoresist Material 50 Transistor 12 Hydrophilic substrate area / bare 52 Through-hole glass surface 53 Traces 13 Ink droplets 54 Electronic connection end 14 Patterned layer 55 Electronic connection end 20 Inkjet head 70 Dielectric layer 21 Ink droplet 71 Dielectric layer / Dielectric polymer 25 glass substrate / gold pole 26 PEDOT electrode layer 72 interconnect 27 F8T2 semiconductor layer 73 through hole 28 PVP insulating layer T1 transistor 29 suitable solvent / droplet / transistor T2 transistor conducting electrode 30 curve 31 curve 32 Area 40 Appearance / Display element 41 Pixel electrode 42 Dielectric layer 43 Addressing line 44 Data line 46 (Please read the precautions on the back before filling this page) ΙΓ_ -scaleΦ Order --------- line-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

Sixth, the scope of application for patent No. 90109553 Patent application for amendment of patent scope August 28, 91 1. A method for forming a transistor, comprising: depositing a first material from a solution of a first solvent to form A first layer of the transistor; and then when the first material remains dissolved in the first solvent, the second material is formed by depositing a second material from a solution of the first solvent on the second material to form the transistor. The second layer, wherein the first material is substantially insoluble in the second solvent. 2. The method according to item 1 of the scope of patent application, the additional step is' when the second material remains dissolved in the second solvent, by depositing the third material from the solution of the third solvent on the second material, The third layer of the transistor is formed, wherein the second material is substantially insoluble in the third solvent. 3_ If the scope of patent application is the first! The method of claim 1, wherein one of the first and first solvents is a polar solvent, and the other of the first and second solvents is a non-polar solvent. 4. The method of claim 3, wherein one of the solvents in the second and first mixtures is a polar solvent, and the other solvent in the second and third solvents is a non-polar solvent. 5. The method according to item 2 of the scope of patent application, wherein the second solvent is a moderately polar solvent including a polar and non-polar group, and one of the first and third solvents is a solvent containing only a polar group. Highly polar solvents. This paper rule money_ 家 鲜 1229884 6. Scope of patent application 6. If the solvent in item 5 of the scope of patent application is a kind of alcohol. "Method" where the moderately polar 7. If the method of the second item of the scope of the patent application, 1, can be dissolved in a non-polar solvent, where the first layer is dissolved in a moderately polar solvent & the second layer is Dissolving ^ ^-isolation layer, the moderately polar bath agent includes a hydrophilic and a hydrophobic group. For example, the method in item 7 of the scope of patent application can be dissolved in a polar solvent. For example, the method in item 7 of the scope of patent application can be dissolved in a non-polar solvent. 10. The method according to item 7 of the scope of patent application is an active layer of the transistor. U. The method according to item 1 in the scope of the patent application, wherein the first layer and the second layer are the source and / or drain layers of the transistor, and [and the second layer The other layer is a semiconductor layer of the transistor. 12 · If the scope of patent application is the first! The method of claim, wherein one of the first and second layers is a semiconductor layer of the transistor, and the other of the first and second layers is an insulating layer of the transistor. 13. A method as claimed in claim 1, wherein the semiconductor layer comprises a conjugated polymer. 14. The method according to item 丨 丨 in the scope of patent application, wherein the semiconductor 8. 9. (CNS) A4 specification (210X297 mm) where the third layer body of the third layer body of the second layer body and 48 Order — (Please read the notes on the back before filling in this page) 15. The layer contains a total of 1¾ block copolymers. 2. The method of claim U in the patent scope, wherein the semiconductor: comprises a -block-dipolymer containing a conjugated monopolymer unit, the units being connected to each other by at least two covalent bonds, and The second block containing the monopolymer units, the sub-block copolymer has an electrical affinity of greater than 3 tears or 3.5 eV. For example, the method of claim 11 in which the semiconductor layer comprises a -block-forming-ghost, polymer-containing material containing co-polymer units, and is connected to each other by at least two covalent bonds, and A second block comprising the monopolymer unit, the block copolymer has an ionization potential ranging between 5.5 eV to 4.9 eV. 17 · = The method of claim 15 in the patent scope, wherein the -block of the monomer unit comprises one or more groups of a 1 derivative, a _-phenylene derivative and a -nonuol derivative, The second block of the monomer unit includes one or more groups of a monophene derivative, a triaryl derivative, and a benzothiadiazole derivative. 18. The method of claim 丨 丨, wherein the semiconductor polymer is F8T2 or TFB. The female patent application method of item 11 of the patent, wherein the semiconductor layer comprises a liquid crystal-like conjugated polymer. This paper is suitable for financial standards (A4 size, Gx297 public love) -49 Shenqing Patent Fanyuan 20 · If the method of patent application item 19, it includes the step of adding liquid crystal polymer to liquid crystal phase . 21 · = material grade ㈣19 slave material M with uniaxial ground wither!忒 Liquid crystal polymer step. 22. The method of claim 21, wherein the step of slitting the crystalline polymer includes depositing the liquid crystalline polymer on a substrate having an adjusted molecular structure. 23. The method of claim 22, which includes the step of adjusting the molecular structure by mechanically rubbing the matrix. 4. The method of claim 22 in the scope of patent application, which includes the step of adjusting the molecular structure by optically processing the layer body. 25. The method of claim U, wherein the semiconductor layer is optically transparent and has a band gap of greater than 23 mm, preferably a band gap of greater than 2.5 eV. 26. The method of UJ | under the scope of patent application, wherein the semiconductor layer body has an ionization potential greater than 4.9 eV. 27. The method according to item 丨 丨 of the patent application, wherein the semiconductor layer has an ionization potential greater than 5.1 eV. 28. The method of claim u, wherein the semiconductor layer has an electron affinity of greater than 4.9 eV. 29. The method of claim 丨 丨, wherein the semiconductor layer has an electron affinity of more than 3.5.eV. 30. For the method of applying for item No. 丨 in the scope of patent application, wherein the first layer of this paper is in accordance with the Chinese National Standard (CNS) M specification ⑵〇χ297 公 豪) 50 1229884 π, patent scope One of the body and the second layer is an insulating layer of the transistor, and the other of the first layer and the second layer is the gate layer of the transistor. For example, the method of claim 2 in the patent scope, wherein one of the first layer body and the third layer body is an insulating layer of the transistor, and the other layer body of the first layer body and the third layer body is Is the gate layer of the transistor, and the second layer is an isolation layer of the transistor. 32. The method of claim 31, wherein the isolation layer is a diffusion barrier layer. 33. The method of claim 32, wherein the diffusion barrier layer comprises a non-polar polymer. 34. = The method of claim 32, wherein the diffusion barrier layer comprises a non-polar conjugated polymer. 35. The method of claim 32, wherein the diffusion barrier layer comprises a polyfluorene derivative. 36. The method of claim 35, wherein the polyaniline derivative is F8, F8T2 or TFB. 37. The method of claim 31, wherein the isolation layer is a surface modification layer. 38. The method of claim W, which includes the step of modifying the surface of the first layer body before depositing the second layer body. For example, the method of claim 38 in the patent scope, where the first layer 31 paper 51-(Please read the precautions on the back before filling this page) (CNS) A4 specification (210X297 mm) 1229884 A «DO C8 D8 VI. The scope of the patent application The modification of the body surface is to provide a contact angle of less than 100 ° for the second material on the first layer Deposition. 40. For the method of claim 38, wherein the surface of the first layer body is modified to provide a contact angle of less than 80 °, so as to deposit the second material on the first layer body. 41. The method of claim 38, wherein the modification of the surface of the first layer is to provide a contact angle of less than 60 ° for deposition of a second material on the first layer. 42. The method of claim 38, wherein the step of modifying the surface of the first layer body includes treating the surface of the first layer body. 43. The method of claim 38, wherein the step of modifying the surface of the first layer body comprises depositing a surface modification material on the surface of the first layer body. 44. The method of claim 43 in which the surface modification material is deposited from a solution of a moderately polar solvent. 45. The method of claim 1, wherein the first layer is deposited on a substrate, and the method includes heating the substrate before the second or third layer is deposited. 46. For the method of applying for the first item of the patent scope, wherein at least one of the first, second and third layers is made by the inkjet printing method-52-This paper size is applicable to China National Standard (CNS) A4 specifications ( 210X297 mm) (Please read the notes on the back before filling this page) 47. The method of claim 46 in which the scope of the patent application is applied, wherein any one of the original electrode and the electrode or gate of the transistor is formed by an inkjet printing method. 48. If the scope of patent application is the first! The method of item 4, wherein the transistor has a source, an electrode, or a gate made of a conductive polymer. 49. The method of claim 48, wherein the electrode is made of a light transparent conductive polymer. 50. The method of claim 48, wherein the conductive polymer comprises a polymer counterion dopant. Α 51. The method of item 1 in the scope of the patent, wherein the material f of the first and second layers is pEDOT / pss. 52. If the scope of patent application is the first! The method of claim, wherein the transistor has two layers, a rim layer, which is formed of a non-co-light or partially co-light polymer. 53. 2 The method of claim 52, wherein the insulating polymer contains hydrophilic and hydrophobic groups, and is soluble in a moderately polar solvent. According to the method of the patent application scope μ, the material of one of the first and second layers is PVP. 55 · —A transistor comprising: a first active layer, which is soluble in a first solvent; 53 claims the patent scope and a second active layer in which the active layer is soluble in a second solvent The first material is substantially insoluble in the second solvent. 56. The transistor of claim 55, comprising a third active layer adjacent to the second active layer and dissolved in a third solvent, wherein the second material in the third solvent is substantially free of Dissolved. 5 Enter the transistor as described in claim 55, wherein the -layer of the first layer and the second layer contains a polar polymer that can be dissolved in a polar solvent, and the first layer and the second layer The other of the layers is a non-polar polymer that is soluble in a non-polar solvent. %. For example, the transistor of claim 57, wherein one of the second and third layers contains a polar polymer that is decomposable in a polar solvent, and one of the second and third layers is The other layer is a non-polar polymer that is soluble in a non-polar solvent. 59. The transistor of claim 57 in which one of the solvents is an alcohol. 60. For example, the transistor in the 55th aspect of the patent application, wherein one of the first and second layers is the source and / or drain layer of the transistor, and the other of the first and second layers is the other. A layer is a semiconductor layer of the transistor within the scope of the patent application. 61. "Please request the transistor in the scope of patent No. 55, wherein one of the first and second layers is a semiconductor of the transistor and the other one of the first and second layers is the transistor. An insulating layer body of a crystal. For example, the transistor of claim 60 in the patent scope is declared, and the material of the semiconductor layer formed is a polymer derivative. 63. The transistor of claim 60 in the patent scope, wherein the The semiconductor layer is optically transparent and has a band gap of more than 2々ν, preferably a band gap of more than 2.5 eV. 64. For example, a patent application range of a 60-type transistor, in which the semiconductor layer body has an ionization greater than 4.9 eV 65. For example, the transistor in the 60th area of the patent application, wherein the semiconductor layer body has an ionization potential greater than 5.leV. In the case of the transistor 60, the semiconductor layer package 3a has a total of 1¾ the first block of a monopolymer unit is a block of a co-former, the unit is connected to each other by at least two covalent bonds, and contains a second block of the monomer unit, and the block is copolymerized The substance has an electron affinity of more than 3.0 eWv. 67. The transistor of claim 60, wherein the semiconductor layer includes the first block-containing co-polymer containing a total of monopolymer units, the unit having at least two covalent bonds 55 1229884 A8 B8 ____ C8 is connected to each other and contains the second block of the monopolymer unit, the block copolymer has an ionization potential ranging from 5 5eV to 4.% ν. 8. If the scope of patent application is 66 A crystal, wherein the first block of the monomer unit comprises one or more radicals of a derivative, a primary phenyl group and an indenofluorene derivative, and a second element of the monomer unit The block contains one or more groups of a monothiophene derivative, a diaryl derivative, and a benzothiadiazole derivative. 69. The transistor according to item 62 of the patent application, wherein the polyfluorene derivative is F8T2 or TFB. Nr \ • If the transistor of the scope of application for the patent No. 60, wherein the semiconductor layer has an ionization potential greater than 4.9eV. 71 · For the transistor of the scope of the patent application for 60, wherein the semiconductor layer has greater than 5. Ionization potential of leV 72. If applying for a patent The transistor surrounding item 55, wherein one of the first layer body and the second layer body is an insulating layer of the transistor, and the other layer body of the first layer body and the second layer body is the Gate layer of transistor. 73. The transistor of claim 55, wherein one of the first layer body and the third layer body is an insulating layer of the transistor, and the first layer body And the other layer of the third layer is the gate layer of the transistor, and the second layer is the transistor. 56 The paper size is suitable for the national standard of the country (Which) A4 size⑵QX297 public love) (Please read first Note on the back, please fill in this page again}. Order 1229884 as B〇C8 D8 VI. An isolation layer for the scope of patent application. (Please read the precautions on the back before filling this page) 74. For the transistor with the scope of patent application No. 73, the isolation layer is a diffusion barrier layer. 75. The transistor of claim 74, wherein the diffusion barrier layer comprises a polyfluorene derivative. 76. For example, the transistor of claim 75, wherein the polyfluorene derivative is F8, F8T2 or TFB. 77. For example, the transistor of claim 73, wherein the isolation layer is a surface modification layer. 78. The transistor of claim 55, wherein the first or second layer body is formed by an inkjet printing method. 79. For example, the transistor of claim 55, wherein the third layer is formed by an inkjet printing method. 80. For example, the transistor of claim 55, wherein the material of one of the first layer body and the second layer body is PEDOT / PSS. 81. For example, the transistor of claim 55, wherein the material of one of the first layer body and the second layer body is PVP. 82. The transistor of claim 55, wherein the transistor is optically transparent. 83. The transistor of claim 55, wherein the transistor is a thin film transistor. 84. —A kind of logic circuit, including the scope of patent application 55.-57-This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 public love) 1229884, patent application scope A8 B8 C8 D8 to 83 Transistor requested by a pavilion. 85. A display device comprising a transistor as described in any one of claims 55 to 83 in the patent application scope. 86. A memory device comprising a transistor as claimed in any one of claims 55 to 83 of the scope of patent application. 87. A logic circuit comprising an active matrix array of a plurality of transistors as claimed in any one of claims 55 to 83. A display device 'includes an active matrix array of a plurality of transistors as claimed in any one of claims 55 to 83 of the scope of patent application. 89. A memory device comprising an active matrix array of a plurality of transistors as requested by any one of members 55 to 83 of the patent application. 90 · —A display including a plurality of display elements, at least one of which is switched by an optically transparent thin film transistor. 91. The display of claim 90, wherein the electric body is located behind the display element. For example, the display device under the scope of patent application No. 91, wherein the display element includes an optical active area switchable by the transistor, and the transistor is electrically coupled to the optical active area by using a conductive material located in a through hole. ^ Γ 92 This paper size applies to China National Standard (CNS) Α4 size (210 X 297 mm) Crystal display (Please read the precautions on the back before filling this page) 1229884 A8 B8 C8 D8 Patent application scope The through hole is formed through at least one layer of the device. (Please read the precautions on the back before filling out this page) 59 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)