TW552671B - Formation method of shallow trench isolation structure with Si/SiGe substrate - Google Patents

Formation method of shallow trench isolation structure with Si/SiGe substrate Download PDF

Info

Publication number
TW552671B
TW552671B TW91118657A TW91118657A TW552671B TW 552671 B TW552671 B TW 552671B TW 91118657 A TW91118657 A TW 91118657A TW 91118657 A TW91118657 A TW 91118657A TW 552671 B TW552671 B TW 552671B
Authority
TW
Taiwan
Prior art keywords
silicon
substrate
germanium
shallow trench
forming
Prior art date
Application number
TW91118657A
Other languages
Chinese (zh)
Inventor
Hsien-Kuang Chiu
Fang-Cheng Chen
Hun-Jan Tao
Original Assignee
Taiwan Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Priority to TW91118657A priority Critical patent/TW552671B/en
Application granted granted Critical
Publication of TW552671B publication Critical patent/TW552671B/en

Links

Landscapes

  • Element Separation (AREA)

Abstract

This invention provides a formation method of shallow trench isolation (STI) region with Si/SiGe substrate, which comprises the following steps: providing a semiconductor substrate; depositing a Si/Ge layer on the semiconductor substrate; forming a Si layer on the Si/Ge layer to form the above-mentioned Si/SiGe layer substrate; providing a patterned hard mask layer on the Si/SiGe layer substrate to define the STI region of the Si/SiGe layer substrate; using the hard mask pattern as a mask to etch the Si/SiGe layer substrate to form a plurality of trenches, in which (I) oxygen mixed with (II) hydrogen bromide, chlorine or their combination are used as the etching source for plasma etching; forming a liner layer on the side wall of the trenches; depositing a dielectric layer to fully fill the trenches; performing a planarization process to remove the dielectric layer outside of the trenches to complete the STI region with Si/SiGe substrate.

Description

552671 五、發明說明(1) 本發明係一種具石夕/矽鍺層基底之淺溝槽隔離結構形 成方法,、特別有關於利用在矽鍺層所形成之偽(pseud〇)基 底上形成矽層,而在此矽/矽鍺基底形成淺溝槽隔離結構 之製造方法。 隔離半導體元件(semic〇nductQr elements isolation)如電晶體等,一般可藉由局部矽氧化法 (LOCOS)或淺溝槽隔離結構(sn :shall〇w isolation)達成’其中淺溝槽隔離結構通常形成於兩個主 動區間,並以一隔離物質填滿該溝槽。由於使用淺溝槽隔 離技術可避免以局部矽氧化法(L〇c〇s)隔離所造成之輪廓 不平坦(topographical irreguUrities)的問題,及因以 氮化矽層做罩幕而產生氧化層侵入(encr〇achment)主動區 之鳥嘴效應(bird’s beak effect),因此,使用淺溝槽隔 離結構除可具有較咼之封裝密度(package density),尚 有較大平坦度(planarity)及良好之隔離品質等優點。 傳統上,乂溝槽隔離結構(如美國專利第6 1 9 & 2 8 5 & 以及6 1 1 0 7 9 3號所揭露)係由蝕刻矽基底而形成之淺溝槽 隔離結構。然而,隨著閘極元件尺寸的縮小化,要使金曰氧 半場效電晶體(M0SFET )元件能在低操作電壓下,具有高 趨動電流和高速的效能是相當困難的。因此,許多人在努 力哥求改善金氧半場效電晶體元件之效能的方法。 利用應變引發的能帶結構變型來增加載子的遷移率, 以增加場效電晶體的趨動電流,可改善場效電晶體元件之 效能,且此種方法已被應用於各種元件中。當石夕M〇SFET元552671 V. Description of the invention (1) The present invention relates to a method for forming a shallow trench isolation structure with a stone / silicon-germanium layer substrate, and particularly relates to forming silicon on a pseudo substrate formed by a silicon-germanium layer. Layer, and a manufacturing method of forming a shallow trench isolation structure on the silicon / silicon germanium substrate. Isolation semiconductor elements (semiconductor Qr elements isolation) such as transistors, etc., can generally be achieved by local silicon oxidation (LOCOS) or shallow trench isolation structure (sn: shall isolation) where the shallow trench isolation structure is usually formed In the two active sections, the trench is filled with an isolation substance. The use of shallow trench isolation technology can avoid the problems of topographical irreguurities caused by local silicon oxide (LoCos) isolation, and the intrusion of oxide layers due to the use of a silicon nitride layer as a mask (Encr0achment) bird's beak effect in the active area. Therefore, in addition to using shallow trench isolation structure, in addition to having a relatively high package density, there is still greater planarity and good Isolation quality and other advantages. Traditionally, a trench-isolated structure (as disclosed in U.S. Patent Nos. 6 1 & 2 8 5 & and 6 1 10 7 9) is a shallow trench isolation structure formed by etching a silicon substrate. However, with the reduction in the size of the gate element, it is quite difficult to make the gold oxygen field-effect transistor (MOSFET) element with high actuating current and high speed under low operating voltage. Therefore, many people are trying to find a way to improve the performance of metal-oxide half-field-effect transistor devices. Strain-induced band structure modification is used to increase the mobility of carriers to increase the actuating current of the field effect transistor, which can improve the performance of the field effect transistor element, and this method has been applied to various elements. When Shi Xi M0SFET Yuan

552671 五 、發明說明(2) ::通道處於拉伸應變的情況時,可增加電子及:^ dtJ:二本發明提供-淺溝槽形成方法,„ /石夕錯Λpseudo)基底上形成石夕層,:,用 子較大?Λ 溝槽隔離結構;由於鍺(⑷传此矽 卞季乂大之金屬,將之摻雜於矽之係一種原 他之:鍺層薄m,使得後來遙晶之=較為鬆 本發明之淺溝槽形成方法,至少而杈伸。 底;沉…錯層於半導體基底么:成提供 :之硬’形成前述之石夕“夕鍺層基底;•供1了 某:更:幕層於矽/矽鍺層基底,以定義出前述圖案 ^中之次溝槽隔離區;姓刻該石夕/石夕錯層基底-層 2以(工繼混合(Π)漠化氫氣體、議其气么槽’ ?源,施行電漿#刻;在溝槽側壁形成襯墊層:u二為麵 心沉積介電層’將該等溝槽填滿;施行—平坦化 移除5亥等溝槽外部之介電層,完二 淺溝槽隔離區。 、/ /缚盾基底的 本發明之功效在於,提供一可增加電子及電 次溝槽隔離結構,並可對蝕刻淺溝槽之深度及卢 好控制。 俅付則良 實施例: 請參閱第1〜6圖,說明本發明實施例製造流程。 首先,由第1圖,提供一半導體基底丨〇〇,例如一矽美 底或是一絕緣層上有矽之基底,在此基底丨〇〇上,以化學&552671 V. Description of the invention (2) :: When the channel is under tensile strain, electrons can be increased and: ^ dtJ: II. The present invention provides a method for forming shallow trenches. The layer is larger, Λ trench isolation structure; due to germanium (which is a large metal of silicon, it is doped in silicon. It is a kind of original: the germanium layer is thin m, which makes the remote crystal = The method for forming shallow trenches according to the present invention is relatively loose, at least while extending. Bottom; Shen ... Is the wrong layer on the semiconductor substrate: Provided by: Hardness to form the above-mentioned Shixi "XiGe layer substrate; : More: The curtain layer is on the silicon / silicon-germanium layer substrate to define the second trench isolation region in the aforementioned pattern ^; the last name is Xishi / Shixi Bilayer Substrate-Layer 2 with (Work-Mixed (Π) Desert The source of hydrogen gas, the gas channel, and the plasma are etched; a gasket layer is formed on the sidewall of the trench: u2 is a face-centered dielectric layer to fill the trenches; The dielectric layer outside the trenches, such as 5H, is removed to complete the two shallow trench isolation regions. // The effect of the invention of the shield substrate is to provide a Adding electronic and electrical trench isolation structure, and can control the depth and thickness of the shallow trench etched. Example of Fu Zeliang: Please refer to Figures 1 to 6 to explain the manufacturing process of the embodiment of the present invention. FIG. 1 provides a semiconductor substrate such as a silicon substrate or a substrate with silicon on an insulating layer. On this substrate, a chemical &

552671 五、發明說明(3) 氣相沉積(CVD )之磊晶(epitaxy )方式 、 例含有石夕與鍺原子之氣體(例如,SiH4, GeH^l適當比 入置有前述基底1〇〇之空腔内,形成較 軋體,導 如Si"、。層"。,㈣與鍺之比例可y二之:夕錯(例 移率做適當調整;再其次,以同樣之 、:之電子遷 石夕之氣體,成長一層石夕層12〇於碎鍺層丨^:法’通入僅有 石夕錯厚度範圍分別為5〇〜3〇〇入與4〇〇〇 :層,及 再❺芩閱第2圖,接著形成一具有型樣之 0〇 A。 做為後續蝕刻步驟之擋罩。其中,硬罩 幕層130 Γ:ΓΓΛ5:0Α 5 此硬罩幕層13G較佳是由下而上依序由氧切。且 化石夕//本化或氧切/氮切/氮氧切所組成乳 例,ΐΐ=:二氧 厭r Q + ,. …乳化法形成,或是以習知的常 c)或低屢化學氣相沉積法( : r=:“position ;lpcvd)沉積而 ^ ^ ^夕層可利用低壓化學氣相沉積法 ^ ,以厂氯矽烷(s 1 c丨2%)與氨氣(νη3)為反應原料沉 ’以一光阻罩幕覆蓋住後續欲形成主動元件 、I、1播氮化石夕層與氧化石夕層進行乾餘刻,以露出後續 之淺溝槽隔離區域。 J後’請參閱第3圖’沿著硬遮幕層13〇敍刻後所遺留 之輪廓,蝕刻矽層1 2〇與矽鍺層丨丨〇至一預定深度,以形成 淺溝槽140 °其中L夕層120與石夕鍺層11G可利用混以 第6頁 0503-8059TWF ; TSMC2001-1670 ; Rita.ptd 552671 五、發明說明(4) "一"_ 多種乳體所形成之餘刻源以低、中或高密度電漿之非等向 性#,f法以移除之;而所需混入之上述蝕刻源,除須包 含有氧氣外、,更需混入氯氣、溴化氫或至少其中之一,同 時亦:在所述混合氣體中選擇性地混入氟化氮(評3 )、峡氣化物氣體(Cx Fx )等氣體增加蝕刻速率或有效控 制#刻之》朱度及輪廓,亦可以加入氦氣、氬氣或氮氣作為 載氣’例如在車父佳實施例中,可以利用高密度電漿蝕刻, 依下表之芩數,混合蝕刻源氣體: 參數 流量比 流量(seem) 功率(W) 壓力〇Torr) 监度(V) 氣體種類\^ HBr:Cli:〇2 150:30:40 150:30:4 200-1500 5-150 20-80 HBr:02 30~1〇 30:1-10:1 200-1500 5-150 20~80 Ch:〇2 20-5 20:1-5:1 200-1500 5-150 20~80 I虫刻碎層1 2 0與石夕錯層丨丨〇達到預定深度完成後,形成淺溝 槽140,深度範圍約可以為2500〜5000人。 完成後之淺溝槽1 4 0,接著,如第4圖所示,在溝槽 140内壁形成概塾層(lining layer)150,其中此概塾層 1 5 0可以施行一熱氧化程序,用以成長一薄的熱氧化層覆 蓋在溝槽1 4 0的侧壁上,其厚度約為1 8 0 A。 接下來,如第5圖所示,填充介電層1 6 0於溝槽内,例 如,可使用03和TEOS當作反應物,施行一次常壓化學氣相 沈積(APCVD )程序,或以高密度電漿所沈積的氧化矽552671 V. Description of the invention (3) Epitaxy method of vapor deposition (CVD), for example, a gas containing Shi Xi and germanium atoms (for example, SiH4, GeH ^ l is appropriately mixed into the substrate 100) In the cavity, a relatively rolled body is formed, such as Si ", layer ". The ratio of ytterbium to germanium can be y: erroneous (for example, the rate of migration should be adjusted appropriately; then, the same,: Move the gas of Shixi, grow a layer of Shixi layer 120 in the broken germanium layer. ^: Method 'access only Shixi fault thickness range is 50 ~ 300mm and 4000: layer, and then Review the second figure, and then form a 0A with a pattern. It is used as a cover for subsequent etching steps. Among them, the hard mask layer 130 Γ: ΓΓΛ5: 0A 5 The hard mask layer 13G is preferably composed of From bottom to top, it is sequentially cut by oxygen. And the milk is composed of fossil evening // localization or oxygen cutting / nitrogen cutting / nitrogen oxygen cutting, ΐΐ =: dioxin r Q +,.... Conventional c) or low-repeated chemical vapor deposition (: r =: "position; lpcvd) is used to deposit ^ ^ ^ layers can be used low-pressure chemical vapor deposition ^, to plant chlorosilane (s 1 c 丨2%) Ammonia gas (νη3) is used as a reaction raw material, and a photoresist mask is used to cover the subsequent active elements, I, 1 nitride layer and oxide layer, and dry etching is performed to expose the subsequent shallow trench isolation. After the J, please refer to FIG. 3, following the outline left after the hard mask layer 13 is etched, the silicon layer 120 and the silicon germanium layer are etched to a predetermined depth to form a shallow trench. 140 ° Wherein the LX layer 120 and the ShiXi germanium layer 11G can be used. Page 6 0503-8059TWF; TSMC2001-1670; Rita.ptd 552671 V. Description of the invention (4) " 一 " _ formed by a variety of milk bodies In the rest of the time, the source is anisotropic #, f method of low, medium or high density plasma to remove it; and the above-mentioned etching source to be mixed must not only contain oxygen, but also chlorine, bromine Hydrogen hydride or at least one of them, and at the same time: selectively mixing nitrogen fluoride (comment 3), isthmus gas (Cx Fx) and other gases into the mixed gas to increase the etching rate or effectively control # 刻 之》 朱Degree and profile, you can also add helium, argon or nitrogen as the carrier gas. In order to use high-density plasma etching, the etching source gas is mixed according to the following table: Parameter flow ratio flow rate (seem) power (W) pressure 〇Torr) monitoring degree (V) gas type \ ^ HBr: Cli: 〇2 150: 30: 40 150: 30: 4 200-1500 5-150 20-80 HBr: 02 30 ~ 1〇30: 1-10: 1 200-1500 5-150 20 ~ 80 Ch: 〇2 20-5 20 : 1-5: 1 200-1500 5-150 20 ~ 80 I Insect fragmented layer 1 2 0 and Shixi staggered layer 丨 丨 〇 After the predetermined depth is completed, a shallow trench 140 is formed, and the depth range can be about 2500 ~ 5000 people. After the completion of the shallow trench 1 4 0, as shown in FIG. 4, a lining layer 150 is formed on the inner wall of the trench 140. The lining layer 1 50 can be subjected to a thermal oxidation process using A thin thermal oxide layer is grown on the sidewall of the trench 140, and its thickness is about 180 A. Next, as shown in FIG. 5, the dielectric layer is filled in the trench 160. For example, 03 and TEOS can be used as reactants, and an atmospheric pressure chemical vapor deposition (APCVD) process can be performed, or Silicon oxide deposited by density plasma

0503-8059TWF ; TSMC2001-1670 ; Rita.ptd 第7頁 552671 五、發明說明(5) — (HDP-SiOd,形成一氧化層16〇,以填滿淺溝槽14〇並覆蓋 在硬罩幕層1 30表面上,得到如圖中所示之元件隔離區才f 造’其具有良好的溝槽填充性質。 最後,如第6圖所示,施以一平坦化程序,例如化學 機械研磨(CMP)或回蝕(etch back)製程,移除溝槽 1 40外部多餘之介電層丨6〇,完成此淺溝槽隔離區製程。胃 本奄明之淺溝槽形成方法,利用在石夕鍺層所形成之偽 (pseudo)基底上形成矽層,而在此矽/矽鍺基底形成淺溝 槽結構,可增加電子及電洞遷移率,並已本發明之蝕刻配 方及電漿蝕刻方式可對蝕刻淺溝槽之深度及圖案得到良好 控制。 本發明雖以較佳實施例揭露如上,然其並非用以限定 士發明,任何熟習此項技藝者,纟不脫離本發明之精神和 犯圍内,當可作些許之更動與潤飾,因此 圍當視後附之申請專利範圍所界定者為準。 保。隻犯0503-8059TWF; TSMC2001-1670; Rita.ptd Page 7 552671 V. Description of the invention (5) — (HDP-SiOd, an oxide layer 16 is formed to fill the shallow trench 140 and cover the hard cover curtain layer On the surface, a device isolation region as shown in the figure is obtained, and it has good trench filling properties. Finally, as shown in FIG. 6, a planarization process such as chemical mechanical polishing (CMP) is performed. ) Or etch back process, remove the excess dielectric layer outside the trench 1 40, 60, and complete this shallow trench isolation region process. The method of forming shallow trenches, which is inherently bright, uses germanium in stone. A silicon layer is formed on a pseudo substrate formed by the layers, and a shallow trench structure is formed on the silicon / silicon-germanium substrate, which can increase electron and hole mobility, and the etching formula and plasma etching method of the present invention can be used. The depth and pattern of the etched shallow trenches are well controlled. Although the present invention is disclosed above in the preferred embodiment, it is not intended to limit the invention of the scholar. Anyone skilled in this art will not depart from the spirit and guilty of the present invention. Inside, when you can make a few changes and retouching, so Subject to the scope of the attached patent application.

552671 圖式簡單說明 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂,下文特舉出較佳實施例,並配合所附圖式,作詳 細說明如下: 第卜6圖係本發明實施例製造流程剖面示意圖。 符號說明: 100〜基底; 1 1 0〜砂鍺層; 1 2 0〜矽層; 1 3 0〜硬罩幕層; 140〜溝槽; 1 5 0〜概塾層; 1 60〜介電層。552671 Brief description of the drawings In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments and the accompanying drawings in detail, as follows: FIG. 6 It is a schematic cross-sectional view of a manufacturing process according to an embodiment of the present invention. Explanation of symbols: 100 ~ substrate; 1 10 ~ sand germanium layer; 120 ~ silicon layer; 130 ~ hard cover curtain layer; 140 ~ trench; 150 ~ general layer; 1 60 ~ dielectric layer .

0503-8059TWF ; TSMC2001-1670 ; Rita.ptd 第9頁0503-8059TWF; TSMC2001-1670; Rita.ptd page 9

Claims (1)

552671 六、申請專利範圍 1 · 一種具矽/矽鍺層基底的 包括下列步驟·· 溝匕隔離區形成方法 (a) 提供一依序形成有矽鍺芦 形成前述之矽/矽鍺層基底;9 夕層之半導體基底 以 (b) 提供一圖案化=硬罩幕 定義出該矽/矽鍺層A %^…亥矽/矽鍺層基底, ,N 对增基底之淺溝槽隔離區;以爲 (c) 蝕刻該矽/矽鍺層基底形成一及^^ 氣混合(Π )溴化氫氣體、氯氣或 ^ 以(1 ) ^ 漿蝕刻。 上口為蝕刻源,施行電 一 2·如申請專利範圍第丨項所述之矽/矽鍺芦 槽隔離區形成方法,更包括下列步驟: 曰土 -、欠/ (d )在該溝槽側壁形成襯墊層; (e)沉積一介電層,將該溝槽填滿;以及 (f )施行一平坦化製程,移除該等溝槽外部之介電 層’完成一具矽/矽鍺層基底的淺溝槽隔離區。 3. 如申請專利範圍第2項所述之矽/矽鍺層基底的淺溝 槽隔離區形成方法,其中該平坦化製程為化學機械研磨 (CMP)或回蝕(etch back)製程。 4. 如申請專利範圍第1項所述之矽/矽鍺層基底的淺溝 槽隔離區形成方法,其中該半導體基底為矽基底或絕緣層 上有矽之基底。 5 ·如申請專利範圍第1項所述之石夕/石夕鍺層基底的淺溝 槽隔離區形成方法,其中該矽鍺層係以化學氣相沉積 (CVD)之磊晶(epitaxy)方式’將混合含有矽與鍺原子552671 6. Scope of patent application 1. A silicon / silicon-germanium substrate includes the following steps. A trench isolation region forming method (a) provides a silicon-germanium reed in order to form the aforementioned silicon / silicon-germanium substrate; 9 The semiconductor substrate of the layer is provided with (b) a patterned = hard mask to define the silicon / silicon-germanium layer A% ^ ... silicon / silicon-germanium layer substrate, N increases the shallow trench isolation area of the substrate; It is thought that (c) the silicon / silicon germanium layer substrate is etched to form a mixed gas (Π) hydrogen bromide gas, chlorine gas or etched with (1) ^ slurry. The upper mouth is an etching source. The method of forming a silicon / silicon germanium reed tank isolation area as described in item 丨 of the patent application scope is performed, further including the following steps: soil-, under / (d) in the trench A liner layer is formed on the sidewall; (e) a dielectric layer is deposited to fill the trench; and (f) a planarization process is performed to remove the dielectric layer outside the trenches to complete a silicon / silicon A shallow trench isolation region on a germanium layer substrate. 3. The method for forming a shallow trench isolation region of a silicon / silicon germanium layer substrate as described in item 2 of the patent application scope, wherein the planarization process is a chemical mechanical polishing (CMP) process or an etch back process. 4. The method for forming a shallow trench isolation region of a silicon / silicon-germanium substrate as described in item 1 of the patent application scope, wherein the semiconductor substrate is a silicon substrate or a substrate with silicon on an insulating layer. 5. The method for forming a shallow trench isolation region of a shixi / shixi germanium layer substrate as described in item 1 of the scope of patent application, wherein the silicon germanium layer is epitaxy by chemical vapor deposition (CVD) 'Will mix containing silicon and germanium atoms 0503-8059TWF ; TSMC2001-1670 ; Rita.ptd0503-8059TWF; TSMC2001-1670; Rita.ptd 552671 六 申請專利範圍 _ ^氣體,導人置有該半導體基 層。 一 I内,沉積形成矽鍺 6 ·如申請專利範圍第5項 槽隔離區形成方法,並由田、^ 夕/石夕鍺層基底的淺溝 SlH4或GeH4。 其中用以化學氣相沉積之氣體包含 7.如申請專利範圍第丨項所述之 槽隔離區形成方法,1Φ兮Ar ώ y錯層基底的淺溝 8 ^矽層厚度範圍為50〜300 A。 槽P ϋ 弟項所述之矽/矽鍺層基底的淺溝 入。 亥矽鍺層厗度靶圍為4000〜20000 9.如申請專利範圍第丨項所述之矽/矽鍺層基底的淺溝 槽隔離區形成方法,其中該硬罩幕層包含氧化矽、氮化 發、氮氧化矽或其組合。 、10·如申請專利範圍第1項所述之矽/矽鍺層基底的淺 溝槽隔離區形成方法,其中(C )步驟以低、中或高密度 電漿餘刻該石夕/石夕錯層。 11 ·如申請專利範圍第丨0項所述之矽/矽鍺層基底的淺 溝槽隔離區形成方法,其中蝕刻源之氣體流量比為c 12 : 〇2 二 2 0 〜5。 1 2 ·如申請專利範圍第1 〇項所述之石夕/石夕鍺層基底的淺 溝槽隔離區形成方法,其中蝕刻源之氣體流量比為HBr :〇2二30〜10。 1 3 ·如申請專利範圍第1 〇項所述之石夕/ =錯層基底的淺 溝槽隔離區形成方法,其中蝕刻源之氣體流量比為c “ :552671 VI Scope of patent application _ ^ Gas, the semiconductor substrate is placed. Silicon germanium is deposited to form a semiconductor layer 6 in accordance with the method of claim 5, the trench isolation region forming method, and a shallow trench SlH4 or GeH4 on the substrate of the germanium / shixi germanium layer. The gas used for chemical vapor deposition includes the method for forming a trench isolation region as described in item 1 of the scope of the patent application. The thickness of the shallow trench of the 1 ar layer is 8 ^ The thickness of the silicon layer ranges from 50 to 300 A. . Slot P 的 The shallow trench in the silicon / silicon-germanium substrate described in the previous item. The silicon germanium layer has a target range of 4000 to 20000. 9. The method for forming a shallow trench isolation region of a silicon / silicon germanium layer substrate as described in item 丨 of the patent application scope, wherein the hard mask layer includes silicon oxide and nitrogen. Chemical hair, silicon oxynitride, or a combination thereof. 10. The method for forming a shallow trench isolation region of a silicon / silicon-germanium layer substrate as described in item 1 of the scope of the patent application, wherein the step (C) is to etch the stone Xi / Shi Xi with a low, medium or high density plasma. Split level. 11. The method for forming a shallow trench isolation region of a silicon / silicon-germanium layer substrate as described in item 丨 0 of the scope of the patent application, wherein the gas flow ratio of the etching source is c 12: 02 2 0 5. 1 2. The method for forming a shallow trench isolation region of a shixi / shixi germanium layer substrate as described in Item 10 of the scope of patent application, wherein the gas flow ratio of the etching source is HBr: 02 to 30 ~ 10. 1 3 · The method of forming a shallow trench isolation region of a split-layer substrate as described in item 10 of the scope of patent application, wherein the gas flow ratio of the etching source is c ": 0503-8059TWF ; TSMC2001-1670 ; Rita.ptd 第11頁 552671 /、、申清專利範圍 HBr:〇2 二 1 5 0:3 0:40。 1 4·如申請專利範圍第丨〇項所述之矽/矽鍺層基底的淺 溝槽隔離區形成方法,其中蝕刻之功率範圍為2 0 0〜1 5 0 0W 、1 5 ·如申請專利範圍第1 〇項所述之矽/矽鍺層基底的淺 溝槽隔離區形成方法,其中蝕刻時之溫度範圍為2 0〜8 0 °C。 、1 6 ·如申請專利範圍第1 〇項所述之矽/矽鍺層基底的淺 溝槽隔離區形成方法,其中蝕刻時之壓力範圍為 5〜150mTorr 〇 、13 ·如申請專利範圍第1項所述之矽/矽鍺層基底的淺 溝槽隔離區形成方法,其中蝕刻該矽/矽鍺層基底之製程 f體更包含氛氣、氬氣、氮氣、氟化氮(NF3)、碳氟化 物氣體(CxFx )或其混合。 、、# 如申請專利範圍第1項所述之矽/矽鍺層基底的淺 ^。曰隔離區形成方法,其中該溝槽深度範圍為2 5 0 0〜50 0 0 ^ α丨9· 一種具矽/矽鍺層基底的淺溝槽隔離區形成方法, 包括下列步驟: (a) 提供一絕緣層上有矽之基底; (b) 依序形成矽鍺層及矽層於該絕緣層上有矽之基 氐,形成^前述之矽/矽鍺層基底; —提供一圖案化之硬罩幕層於該矽/矽鍺層基底,以 疋、该矽/矽鍺層基底之淺溝槽隔離區,其中該硬罩幕 第12頁 0503-8059TWF ; TSMC2001-1670 ; Rita.ptd 552671 六、申請專利範圍 --- 層包含氧化矽、氮化矽、氮氧化矽或其組合; (d) I虫刻該石夕/石夕錯層基底形成一溝槽甘 ♦ “ 曰其中用以蝕刻 该矽/矽鍺層基底之蝕刻氣體包含: (I )氧氣; 或其組 (Π)溴化氫、氯氣或其組合;以及 (m)氟化氮(nfs )、碳氟化物氣體(c F 合 (e)在該溝槽侧壁形成襯墊層; (f )沉積一介電層,將該溝槽填滿;以及 (g)施行一平坦化製程,移除該溝槽外邱+人+ a I叶之介電層, 元成一具石夕/石夕鍺層基底的淺溝槽隔離區。 20.如申請專利範圍第19項所述之矽/矽錯層基底的、淺 溝槽隔離區形成方法,其中該矽鍺層係以化學ϋ沉積/ (CVD)之磊晶(epitaxy)方式,將混合含有石夕與錯原子 之氣體,導入置有該半導體基底之空腔内,沉積形成石夕鍺 層。 2 1 ·如申請專利範圍第20項所述之矽/矽鍺層基底的淺 溝槽隔離區形成方法,其中用以化學氣相沉積之氣體包含 SiH4 或GeH4。 2 2 ·如申請專利範圍第1 9項所述之矽/矽鍺層基底的淺 溝槽隔離區形成方法,其中該矽層厚度範圍為5 〇〜3 0 0 A。 2 3 ·如申請專利範圍第1 9項所述之矽/矽鍺層基底的淺 溝槽隔離區形成方法,其中該矽鍺層厚度範圍為4 0 0 0〜 20000 A 〇0503-8059TWF; TSMC2001-1670; Rita.ptd Page 11 552671 /, Patent application scope HBr: 02 2 15 0: 3 0:40. 14 · The method for forming a shallow trench isolation region of a silicon / silicon germanium layer substrate as described in item No. 丨 0, wherein the power range of the etching is in the range of 2 0 ~ 1 5 0 0 W, 1 5 The method for forming a shallow trench isolation region of a silicon / silicon germanium layer substrate according to the range of item 10, wherein a temperature range during etching is 20 to 80 ° C. 1, 16 · The method for forming a shallow trench isolation region of a silicon / silicon-germanium substrate as described in item 10 of the scope of patent application, wherein the pressure range during etching is 5 to 150 mTorr 〇, 13 · As the scope of patent application No. 1 The method for forming a shallow trench isolation region of a silicon / silicon germanium layer substrate according to the item, wherein the process of etching the silicon / silicon germanium layer substrate further includes an atmosphere, argon, nitrogen, nitrogen fluoride (NF3), carbon Fluoride gas (CxFx) or a mixture thereof. ,, # As described in the patent application for item 1 of the silicon / silicon germanium substrate. A method for forming an isolation region, wherein the depth of the trench is in the range of 2500 to 50 0 0 ^ α 丨 9. A method for forming a shallow trench isolation region with a silicon / silicon germanium layer substrate includes the following steps: (a) Provide a substrate with silicon on the insulating layer; (b) sequentially form a silicon germanium layer and a silicon layer with a silicon substrate on the insulating layer to form the aforementioned silicon / silicon germanium substrate;-provide a patterned substrate The hard mask layer is on the silicon / silicon-germanium substrate, and the trench is a shallow trench isolation region of the silicon / silicon-germanium substrate. The hard mask is on page 12 0503-8059TWF; TSMC2001-1670; Rita.ptd 552671 Sixth, the scope of patent application --- the layer contains silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof; (d) I engraved the Shi Xi / Shi Xi interlayer substrate to form a trench. The etching gas used to etch the silicon / silicon germanium layer substrate includes: (I) oxygen; or a group thereof (Π) hydrogen bromide, chlorine gas, or a combination thereof; and (m) nitrogen fluoride (nfs), a fluorocarbon gas (c F (e) forming a liner layer on the sidewall of the trench; (f) depositing a dielectric layer to fill the trench; and (g) performing a flat In the manufacturing process, the dielectric layer of the outer layer of Qiu + Ren + a I leaves is removed, and a shallow trench isolation region with a Shixi / Shixi germanium substrate is formed. 20. As described in item 19 of the scope of patent application Method for forming a shallow trench isolation region on a silicon / silicon layer, wherein the silicon germanium layer is introduced by a chemical epitaxial deposition / (CVD) epitaxy method, and a gas containing a stone and a stray atom is introduced into the silicon germanium layer. A silicon germanium layer is deposited in the cavity in which the semiconductor substrate is placed. 2 1 · A method for forming a shallow trench isolation region of a silicon / silicon germanium layer substrate as described in item 20 of the patent application scope, in which a chemical gas is used The phase-deposited gas includes SiH4 or GeH4. 2 2 · The method for forming a shallow trench isolation region of a silicon / silicon-germanium substrate as described in item 19 of the patent application scope, wherein the thickness of the silicon layer ranges from 50 to 30 0 A. 2 3 · The method for forming a shallow trench isolation region of a silicon / silicon-germanium layer substrate as described in item 19 of the scope of patent application, wherein the thickness of the silicon-germanium layer ranges from 4 0 0 to 20000 A 〇 0503-8059TWF ; TSMC2001-1670 ; Rita.ptd 第13頁 552671 六、申請專利範圍 、24·如申請專利範圍第1 9項所述之矽/矽鍺層基底的淺 溝槽隔離區形成方法,其中蝕刻該矽/矽鍺層基底之-氣體 更包含氦氣、氬氣或至少其中之/。 、2 5 ·如申請專利範圍第1 9項所述之矽/矽鍺層基底的淺 溝槽隔離區形成方法,其中該平坦化製程為化學機械研磨 (CMP )或回蝕(etch back )製稃。 、26·如申請專利範圍第1 9項所述之矽/矽鍺層基底的淺 屢槽隔離區形成方法,其中該溝槽深度範圍為2 5 0 0〜5 0 0 0 A 〇 、2 7 ·如申請專利範圍第1 9項所述之矽/矽鍺層基底的淺 溝槽隔離區形成方法,其中(d )夕驟以低、中或高密度 電聚餘刻該矽/矽鍺層。 、28·如申請專利範圍第27項所述之石夕/矽鍺層基底的淺 溝槽隔離區形成方法,其中蝕刻源之氣體流量比為Cl2 : 〇2 二 2 0 〜5。 2 9.如申請專利範圍第27項所述之石夕/矽鍺層基底的淺 溝槽隔離區形成方法,其中蝕刻源之氣體流量比為HBr: 〇2 二 3 0 〜1 〇 〇 30·如申請專利範圍第27項所述之石夕/矽鍺層基底的淺 溝槽隔離區形成方法,其中蝕刻源之氣體流量比為Cl2 : HBr: 02 = 150:30:4。 31 ·如申請專利範圍第2 7項所述之石夕/矽鍺層基底的淺 溝槽隔離區形成方法,其中蝕刻之功率範圍為2 〇 〇〜 1500W 。0503-8059TWF; TSMC2001-1670; Rita.ptd Page 13 552671 VI. Patent application scope, 24. Method for forming a shallow trench isolation region of a silicon / silicon germanium layer substrate as described in item 19 of the patent application scope, wherein The gas for etching the silicon / silicon-germanium substrate further comprises helium, argon, or at least one of them. 2. 25. The method for forming a shallow trench isolation region of a silicon / silicon germanium layer substrate as described in item 19 of the scope of the patent application, wherein the planarization process is a chemical mechanical polishing (CMP) or etch back process Alas. 26. The method for forming a shallow trench isolation region of a silicon / silicon germanium layer substrate as described in item 19 of the scope of the patent application, wherein the trench depth ranges from 2 500 to 5 0 0 A 〇, 2 7 The method for forming a shallow trench isolation region of a silicon / silicon-germanium layer substrate as described in item 19 of the patent application scope, wherein (d) the silicon / silicon-germanium layer is etched with low, medium, or high-density electropolymerization . 28. The method for forming a shallow trench isolation region of a shixi / silicon-germanium substrate as described in item 27 of the scope of the patent application, wherein the gas flow ratio of the etching source is Cl2: 〇2 220 ~ 5. 2 9. The method for forming a shallow trench isolation region of a shixi / silicon-germanium substrate as described in item 27 of the scope of patent application, wherein the gas flow ratio of the etching source is HBr: 〇2 230 ~ 1 〇〇30 · According to the method for forming a shallow trench isolation region of a shixi / silicon-germanium substrate as described in item 27 of the scope of the patent application, wherein the gas flow ratio of the etching source is Cl2: HBr: 02 = 150: 30: 4. 31. The method for forming a shallow trench isolation region of a shixi / silicon-germanium substrate as described in item 27 of the scope of patent application, wherein the power range of the etching is in the range of 2000-1500W. 0503-8059TWF ; TSMC2001-1670 ; Rita.ptd 第14頁 552671 六、申請專利範圍 32·如申請專利範圍第27項所述之矽/矽鍺層基底的淺 曰^離區形成方法,其中蝕刻時之溫度範圍為2 〇〜8 〇 C。 、4 _3ρ3·μ如申請專利範圍第27項所述之矽/矽鍺層基底的淺 溝槽隔硪區形成方法,其中蝕刻時之壓力範圍為 5〜1 50mT〇rr。 句 、、聋样3p4·齙如Λ請/利範圍第19項所述之石夕/石夕鍺層基底的淺 溝才曰Pwj離區形成方、、支 rh / 氣體更包入气 其中蝕刻該鍺層基底之製程 更匕3虱乳、氮氣、氦氣或其組合。0503-8059TWF; TSMC2001-1670; Rita.ptd Page 14 552671 VI. Patent application scope 32. A method for forming a shallow separation region of a silicon / silicon-germanium layer substrate as described in item 27 of the patent application scope, wherein during etching The temperature range is from 20 to 80 ° C. 4_3ρ3 · μ The method for forming a shallow trench barrier region of a silicon / silicon-germanium layer substrate as described in item 27 of the patent application scope, wherein the pressure during etching ranges from 5 to 150 mT0rr. Sentence, deaf-like 3p4 · 龅 As described in ΛPlease / Professional scope of item 19, the shallow trench of the Shixi / Shixi germanium layer substrate is said to form the Pwj away zone, and the rh / gas is more enclosed in the gas, which is etched The manufacturing process of the germanium layer substrate further includes milk, nitrogen, helium, or a combination thereof. 第15頁Page 15
TW91118657A 2002-08-19 2002-08-19 Formation method of shallow trench isolation structure with Si/SiGe substrate TW552671B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW91118657A TW552671B (en) 2002-08-19 2002-08-19 Formation method of shallow trench isolation structure with Si/SiGe substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW91118657A TW552671B (en) 2002-08-19 2002-08-19 Formation method of shallow trench isolation structure with Si/SiGe substrate

Publications (1)

Publication Number Publication Date
TW552671B true TW552671B (en) 2003-09-11

Family

ID=31713653

Family Applications (1)

Application Number Title Priority Date Filing Date
TW91118657A TW552671B (en) 2002-08-19 2002-08-19 Formation method of shallow trench isolation structure with Si/SiGe substrate

Country Status (1)

Country Link
TW (1) TW552671B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9966312B2 (en) 2015-08-25 2018-05-08 Tokyo Electron Limited Method for etching a silicon-containing substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9966312B2 (en) 2015-08-25 2018-05-08 Tokyo Electron Limited Method for etching a silicon-containing substrate

Similar Documents

Publication Publication Date Title
TWI442448B (en) Methdos to fabricate mosfet devices using selective deposition processes
CN100459160C (en) Semiconductor device
US7553717B2 (en) Recess etch for epitaxial SiGe
US8258576B2 (en) Method of manufacturing a semiconductor device including epitaxially growing semiconductor epitaxial layers on a surface of semiconductor substrate
KR100855977B1 (en) Semiconductor device and methods for manufacturing the same
US7985641B2 (en) Semiconductor device with strained transistors and its manufacture
JP4361880B2 (en) Manufacturing method of semiconductor integrated circuit device
TWI404210B (en) Semiconductor structure and fabrication method thereof
US7713834B2 (en) Method of forming isolation regions for integrated circuits
US20080213952A1 (en) Shallow trench isolation process and structure with minimized strained silicon consumption
TW202038379A (en) Methods of forming semiconductor devices
US20080105899A1 (en) Semiconductor device with epitaxially grown layer and fabrication method
US6673696B1 (en) Post trench fill oxidation process for strained silicon processes
KR20010009810A (en) Trench-type isolation method using Si-Ge epitaxial layer
JP3586268B2 (en) Semiconductor device and manufacturing method thereof
US20070066023A1 (en) Method to form a device on a soi substrate
TW552671B (en) Formation method of shallow trench isolation structure with Si/SiGe substrate
KR100671563B1 (en) A method for forming contact of semiconductor device using the epitaxial process
CN100477151C (en) Trench isolation technology and method
US6962857B1 (en) Shallow trench isolation process using oxide deposition and anneal
KR100638422B1 (en) A method for filling contact-hole of semiconductor device using the epitaxial process
CN105304491B (en) The method for being used to form embedded germanium silicon
CN105206576B (en) Method for forming embedded germanium silicon source/drain structure
KR100638988B1 (en) A semiconductor device using the epitaxial process, and a method of forming a polishing thereof
TWI222700B (en) Method for forming shallow trench isolation on SiGe substrate

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MK4A Expiration of patent term of an invention patent