550738 A7 B7 五、發明説明（） 發明領域： (請先閲讀背面之注意事項再塡寫本頁) 本發明係有關於自我對準浮置閘極之淺溝渠隔離結構 之製造方法，特別是有關於具有自我對準浮置閘極之淺溝 渠隔離結構之快閃記憶體之製造方法。 發明背景： 隨著積體電路技術的高度發展’元件線寬日益縮小。 因此淺溝渠隔離（Shallow Trench Isolation ; STI)技術製作 主動區域之間的絕緣結構，已逐漸普遍被採用。淺溝渠隔 離的製造方法’常被應用於快閃記憶體的製作，因為其所 製作出的記憶胞具有最小尺寸（Minimized Size)，可使得快 閃記憶體的分佈具有較高之密度，以降低位元之成本。然 而，此種快閃記憶體因其浮置閘極層（Floating Gate)與淺溝 渠轉角（Shallow Trench Corner)重疊而產生的場增強效應 (Field Enhancement Effect)之情況下，無可避免的將降低閘 極氧化層之崩潰電壓。 ， 經濟部智慧財產局員工消費合作社印製 為了改善此種現象，自我對準（Self-aligned)浮置閘極 之淺溝渠隔離結構因而被提出。自我對準浮置閘極之淺溝 渠隔離結構，因為使用相同的罩幕（Mask)以蝕刻浮置閘極 及淺溝渠結構，所以彼此之間可形成自我對準的情況。因 本紙張又度適用中國國家標準(CNS)A4規格(210X297公釐) 550738 A7 B7 五、發明説明（） 此消除了浮'置閘極及淺溝渠結構產生重疊的現象’更進一 步改善了閘極氧化層崩潰的情況。 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 但是此種自我對準浮置閘極之淺溝渠隔離結構，依然 存在著一些問題。請參見第一 A至一 D圖’為一使用自我 對準浮置閘極之淺溝渠隔離結構之記憶體之淺溝渠製造方 法的製程示意圖。如第一 A圖中所示，在一基材1 〇 〇之上， 依序形成穿遂氧化層102、多晶矽層1 〇4及已圖案化之氮 化矽層1 〇6及其開口 10 8。接著請參照第一 B圖，以氮化 石夕層106為罩幕，由開口 108使用非等向性蝕刻多晶矽層 1 04、穿遂氧化層及基材100，進而形成一淺溝渠1 10 之結構。第一 C圖，以熱氧化法在淺溝渠110内壁、穿遂 氧化層1 02及多晶矽層1 04上，形成一襯氧化層1 1 2。接 著請參照第一 D圖，再以氧化矽材質沈積並填滿襯氧化層 1 1 2之内側並南於氮化石夕層1 〇 6，形成氧化層1 1 6。如圖中 所示，由於以熱氧化法，在淺溝渠1 1 〇内壁、穿遂氧化層 1 02及多晶矽層1〇4上，形成一襯氧化層1 12時，因為氧 4匕的關係，連接淺溝渠Π 0内壁及多晶矽層1 04之襯氧化 層112，會較連接穿遂氧化層102之襯氧化層112略微突 出。也就是說，連接穿遂氧化層102之襯氧化層Π2會較 為凹陷。故當氧化矽材質沈積並填滿襯氧化層1 1 2之内側 時，小的孔洞（Void) 1 14極易在此形成。 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 550738 A 7 B7 五、發明說明（） 如何消除此種孔洞的產生，以改善自我對準浮置閘極 之淺溝渠隔離結構積體電路之電性，實為半導體製程發展 一個重要的課題。 發明目的及概述： 鑒於上述之發明背景中，自我對準浮置閘極之淺溝渠 隔離結構常存在小的孔洞，因而影響積體電路之電性。 本發明的目的之一，係利用具有階梯狀之淺溝渠結 構’使沈積氧化層中之孔洞發生機率降低，使改善自我對 準浮置閘極之淺溝渠隔離結構積體電路之電性。 本發明的再一目的，係利用一多晶矽蝕刻機，並於其 中連續完成敍刻，產生局分子聚合物之犧牲層，形成淺溝 渠造型，並清除上述之犧牲層，而無須更換機台。使自我 對準浮置閘極之淺溝渠隔離結構之生產及良率提升。 it 根據以上所述之目的，本發明係一種改善自我對準浮 置閘極之淺溝渠隔離結構之製造方法，包含下列步驟：提 供一基材’其中此基材上已依序堆登一穿遂氧化層、一多 晶矽層，及一已圖案化氮化矽層。再使用已圖案化氮化矽 層為罩幕，餘刻多晶石夕層至穿遂氧化層時停止，同時並產 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) .............. (請先閲讀背面之注意事項再填寫本頁) 訂· 經濟部智慧財產局員Η消費合作社印製 550738 A7 B7 五、發明説明（ ） (請先閲讀背面之注意事項再填寫本頁) 生一犧牲層覆蓋於上述之多晶矽層之内側。利用同一蝕刻 機台，調整触刻電漿蝕刻上述之基材，至形成該淺溝渠。 使用灰化製程及水洗製程清除上述之犧牲層，以熱氧化法 形成一襯氧層，最後再以，如高密度電漿化學氣相沈積 (High Density Plasma Chemical Vapor Deposition ； HDP CVD)製程等方式，形成一沈積氧化層填充於淺溝渠之中及 覆蓋於氮化石夕層之上。 圖式簡單說明： 本發明的較佳實施例將於往後之說明文字中輔以下列 圖形做更詳細的闡述，其中： 第一 A--D圖為習知的自我對準浮置閘極之淺溝渠 隔離結構之記憶體之淺溝渠製造方法的製程示 意圖；及 第二A〜二F圖為本發明之自我對準浮置閘極之淺溝 渠隔離結構之記憶體’淺溝渠製造方法的製程 示意圖。 經濟部智慧財產局員工消費合作社印製 圖號對照說明： 1 00基材 102穿遂氧化層 104多晶矽層 106 氮化矽層 本紙張尺L度適用中國國家標準(CNS)A4規格(2丨0X297公釐) 55〇738 A7550738 A7 B7 V. Description of the invention () Field of invention: (Please read the notes on the back before writing this page) The present invention relates to a method for manufacturing a shallow trench isolation structure with self-aligned floating gates, especially A method for manufacturing a flash memory with a shallow trench isolation structure with self-aligned floating gates. Background of the Invention: With the development of integrated circuit technology, the component line width is becoming smaller and smaller. Therefore, Shallow Trench Isolation (STI) technology has been gradually used to make insulation structures between active areas. The manufacturing method of shallow trench isolation is often used in the production of flash memory, because the memory cells produced by it have a minimum size, which can make the distribution of flash memory have a higher density to reduce the bit The cost of yuan. However, the field enhancement effect caused by the overlapping of the floating gate and the shallow trench corner of this flash memory will inevitably decrease the field enhancement effect. The breakdown voltage of the gate oxide. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs To improve this phenomenon, a self-aligned floating trench isolation structure with shallow trenches was proposed. Self-aligned shallow trench isolation structures of floating gates can self-align with each other because the same mask is used to etch the floating gate and shallow trench structures. Because this paper is again applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 550738 A7 B7 V. Description of the invention () This eliminates the floating 'overlapping of the gate electrode and shallow trench structure' and further improves the gate Case of extreme oxide layer collapse. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs However, there are still some problems with this type of shallow trench isolation structure with self-aligned floating gates. Please refer to FIGS. 1 to 1D ′ for a schematic diagram of a manufacturing process of a shallow trench manufacturing method using a shallow trench isolation structure of a self-aligned floating gate. As shown in FIG. 1A, a through oxide layer 102, a polycrystalline silicon layer 104, and a patterned silicon nitride layer 106 and openings 10 8 are sequentially formed on a substrate 100. . Next, please refer to the first figure B, using the nitrided layer 106 as a mask, and anisotropically etch the polycrystalline silicon layer 104, the through oxide layer, and the substrate 100 through the opening 108, thereby forming a shallow trench 1 10 structure. . In the first figure C, a thermal oxidation method is used to form a liner oxide layer 12 on the inner wall of the shallow trench 110, the tunnel oxide layer 102 and the polycrystalline silicon layer 104. Next, please refer to the first figure D, and then deposit and fill the inner side of the liner oxide layer 1 12 with the silicon oxide material and south of the nitride layer 106 to form the oxide layer 1 16. As shown in the figure, when a thermal oxidation method is used to form a liner oxide layer 12 on the inner wall of the shallow trench 110, the tunneling oxide layer 102, and the polycrystalline silicon layer 104, because of the relationship between oxygen and oxygen, The liner oxide layer 112 connecting the inner wall of the shallow trench Π 0 and the polycrystalline silicon layer 104 may be slightly more prominent than the liner oxide layer 112 connecting the tunneling oxide layer 102. In other words, the liner oxide layer Π2 connected to the tunneling oxide layer 102 is relatively depressed. Therefore, when the silicon oxide material is deposited and fills the inside of the liner oxide layer 1 12, small pores (Void) 1 14 are easily formed here. This paper scale applies Chinese National Standard (CNS) A4 specification (210X297 mm) 550738 A 7 B7 V. Description of the invention () How to eliminate the generation of such holes to improve the self-aligned floating gate insulation structure of shallow trenches The electrical property of the body circuit is an important issue for the development of semiconductor processes. Object and summary of the invention: In view of the above background of the invention, the shallow trench isolation structure of self-aligned floating gates often has small holes, thus affecting the electrical properties of the integrated circuit. One of the objects of the present invention is to reduce the probability of occurrence of holes in the deposited oxide layer by using a shallow trench structure with a stepped shape, so as to improve the electrical properties of the integrated circuit of the shallow trench isolation structure with self-aligned floating gates. Still another object of the present invention is to use a polycrystalline silicon etching machine and continuously perform engraving in it to generate a sacrificial layer of local molecular polymer to form a shallow trench shape and remove the aforementioned sacrificial layer without replacing the machine. The production and yield of shallow trench isolation structures with self-aligned floating gates are improved. it According to the above-mentioned purpose, the present invention is a manufacturing method for improving a shallow trench isolation structure for self-aligned floating gates, including the following steps: providing a substrate, wherein the substrate is sequentially stacked and penetrated. An oxide layer, a polycrystalline silicon layer, and a patterned silicon nitride layer. The patterned silicon nitride layer is used as a mask, and the polycrystalline silicon layer is stopped until the tunneling oxide layer is formed. At the same time, the paper size is in accordance with the Chinese National Standard (CNS) A4 specification (210X297 mm) .. ............ (Please read the notes on the back before filling out this page) Order · Printed by the Intellectual Property Office of the Ministry of Economic Affairs and Consumer Cooperatives 550738 A7 B7 V. Description of the invention () (Please read first Note on the back side, please fill in this page again.) A sacrificial layer is formed to cover the inside of the above polycrystalline silicon layer. The same etching machine is used to adjust the etching plasma to etch the above substrate to form the shallow trench. An ashing process and a water washing process are used to remove the aforementioned sacrificial layer, an oxygen-lined layer is formed by thermal oxidation, and finally, such as a High Density Plasma Chemical Vapor Deposition (HDP CVD) process, etc. A deposited oxide layer is formed to fill the shallow trench and cover the nitrided layer. Brief description of the drawings: The preferred embodiment of the present invention will be described in more detail in the following explanatory text with the following figures, where: The first A-D diagram is a conventional self-aligned floating gate The schematic diagram of the manufacturing process of the shallow trench manufacturing method for the memory of the shallow trench isolation structure; and the second A to F are diagrams of the method of manufacturing the shallow trench isolation structure of the self-aligned floating gate shallow trench isolation structure of the present invention Process schematic diagram. Contrast description of printed numbers printed by employees ’cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs: 1 00 base material 102 tunneling oxide layer 104 polycrystalline silicon layer 106 silicon nitride layer The paper rule L degree is applicable to China National Standard (CNS) A4 specification (2 丨 0X297 (Mm) 55〇738 A7
11 〇淺溝渠 1 1 4孔洞 202穿遂氧化層 2 06氮化石夕層 2 1 〇淺溝渠 2 1 4犧牲層 218階梯狀輪廟 1 0 8 開口 1 1 2襯氡化層 1 16氧化層 2α〇基材 2〇4多晶矽屑 2 〇8 開口 2 1 2襯氧化層 2 1 6氧化層 發明詳細說明 本發明之自我對準浮置閘極之淺溝渠隔離結構，不僅 消除了浮置鬧極及淺溝渠結構產生重®的現象，改善閘極 氧化層崩潰的情況。更進一步消除淺溝渠結構中之孔洞的 產生，使積體電路之電性因而改善，為半導體製程發展提 供一更為穩定及優質的生產方式。更由於本發明之製造方 法，利用非等向性蝕刻程序蝕刻出淺溝渠隔離結構開口， 並形成階梯狀的淺溝渠結構’因而改良習知製造方法造成 淺溝渠隔離結構内部形成孔洞的情況。 .............I (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 以11 〇 Shallow ditch 1 1 4 Hole 202 Pass through oxide layer 2 06 Nitride layer 2 1 〇 Shallow ditch 2 1 4 Sacrificial layer 218 Stepped wheel temple 1 0 8 Opening 1 1 2 Lining layer 1 16 Oxidation layer 2α 〇Substrate 2 04 Polycrystalline silicon chips 2 0 8 Opening 2 1 2 Lining oxide layer 2 1 6 Oxide layer Detailed description of the invention The shallow trench isolation structure of the self-aligned floating gate of the present invention not only eliminates the floating anode and the Shallow trench structure produces heavy phenomenon, which improves the breakdown of gate oxide layer. Furthermore, the generation of holes in the shallow trench structure is further eliminated, thereby improving the electrical properties of the integrated circuit, and providing a more stable and high-quality production method for the development of semiconductor processes. Furthermore, the manufacturing method of the present invention uses a non-isotropic etching process to etch the openings of the shallow trench isolation structure to form a stepped shallow trench structure ', thereby improving the situation in which holes are formed inside the shallow trench isolation structure by the conventional manufacturing method. ............. I (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs
A 參開 請置 。浮 點準 優對 及我 法 自 方之 之明 明發 發本 本為 ， 示 明所 說中 細 圖 詳 ’ 例圖 圖以將A Please open. The floating-point quasi-optimal pair and the method of our own self-published version are published, showing the medium and detailed drawings in detail.
F 適 度 尺 張 紙 本 釐 公 97 2 X 10 2 規 4 A S) N C標 家 國 國 550738 A7 B7 五、發明説明（） 極之淺溝渠隔離結構之記憶體之淺溝渠製造方法的製程示 意圖。請參見第二A圖，如圖中所示，在一基材200之上， 依序形成穿遂氧化層202、多晶矽層204及已圖案化之氮 化矽層206及其開口 208。其中，穿遂氧化層202的厚度 約在80埃（Angstrom)至120埃，多晶石夕層204的厚度約為 4〇〇埃至1000埃及氮化石夕層20 6之厚度約為150〇埃至25〇〇 埃。 第二B圖，以氮化石夕層206為罩幕，由開口 208使用 与择等向性触刻方法進行多晶石夕層204餘刻，並停止在穿遂 氧化層2 0 2之上。此時使用的非等向性蝕刻方法，係利用 具有對氧化矽及矽有高選擇性的電漿所進行。在此同時， 電漿反應氣體，一面進行多晶矽層204之蝕刻，另一方面 進行高分子聚合（polymerization)反應，以沉積高分子聚合 物於多晶矽層204及氮化矽層206之内側，進而形成一犧 牲層2 1 4，覆蓋在其表面。此犧牲層2 1 4的厚度約被控制 在50埃至3 00埃之間，可由實際蝕刻時的條件加以調整。 此種蝕刻的方法，一般可由多晶石名蝕刻機（Poly Etcher)，例 如：應用材料之DPS或東京電子之84DD钱刻機等，以含 有氣（Ch)，溴化氫（HBr*)及氧（〇2)的氣體來進行。當使用應 用材料之D P S蝕刻機時，較佳的參數設定為： 壓 力：4-10毫托爾（mtorr) ’ 電漿能量：250-500瓦（W) ’ 本紙張只L度適用中國國家標準(CNS)A4規格(210x297公釐) .............. (請先閲讀背面之注意事項再塡寫本頁) 、一一" 經濟部智慧財產局員工消費合作社印製 M〇738 A7F Moderate paper size cm 97 2 X 10 2 gauge 4 A S) N C standard country 550738 A7 B7 V. Description of the invention () The manufacturing method of the shallow trench manufacturing method for the memory of the extremely shallow trench isolation structure is shown. Referring to FIG. 2A, as shown in the figure, a through oxide layer 202, a polycrystalline silicon layer 204, a patterned silicon nitride layer 206, and an opening 208 are sequentially formed on a substrate 200. Among them, the thickness of the tunneling oxide layer 202 is about 80 Angstroms (Angstroms) to 120 Angstroms, and the thickness of the polycrystalline stone layer 204 is about 400 Angstroms to 1,000 Angstroms. To 2500 Angstroms. In the second diagram B, the nitrided layer 206 is used as a mask, and the polycrystalline stone layer 204 is etched by the opening 208 using the isotropic etching method and stopped on the tunneling oxide layer 202. The anisotropic etching method used at this time is performed using a plasma having high selectivity to silicon oxide and silicon. At the same time, the plasma reactive gas is used to etch the polycrystalline silicon layer 204 on one side and a polymerization reaction on the other to deposit a polymer on the inside of the polycrystalline silicon layer 204 and the silicon nitride layer 206 to form A sacrificial layer 2 1 4 covers its surface. The thickness of this sacrificial layer 2 1 4 is controlled between about 50 angstroms and 300 angstroms, and can be adjusted by the conditions during actual etching. This etching method is generally performed by a polycrystalline etcher (Poly Etcher), for example: DPS of applied materials or 84DD coin engraving machine of Tokyo Electron, etc., to contain gas (Ch), hydrogen bromide (HBr *) and Oxygen (〇2) gas. When using the DPS etching machine of applied materials, the preferred parameter settings are: Pressure: 4-10 mtorr 'Plasma energy: 250-500 watts (W)' This paper only applies to Chinese national standards for L degree (CNS) A4 size (210x297 mm) .............. (Please read the precautions on the back before writing this page), one by one " Consumption by Intellectual Property Bureau, Ministry of Economic Affairs Printed by the cooperative M〇738 A7
氣氣流量：每分鐘每標準立方公分（seem)， (請先閲讀背面之注意事項再填寫本頁) >臭彳匕氫流量：100-200 seem，及 氧氣流量’· 1 〇-50 seem。 當使用東京電子之8 4 D D 14刻機時，較佳的參數設定 為： 壓 力：1 0-3 0 mtorr， 電衆能量：4 0 0 - 8 0 0 W， 氣氣流量：〇 - 5 0 s c c m， 溴化氫流量：6 0 -1 5 0 s c c m，及 氧氣流量·· 1 〇 - 5 0 s c c m。 參見第2C圖，繼續使用多晶矽蝕刻機（Poly Etcher)， 例如：應用材料之DPS或東京電子之84DD蝕刻機等，以 含有氣（Ch)，溴化氫（HBr)及氧（〇2)的氣體來進行基材200 的蝕刻。當使用應用材料之D P S蝕刻機時，較佳的參數設 定為： 壓 力：4-10mtorr， 電漿能量：250-500 W， 經濟部智慧財產局員工消費合作社印製 偏壓能量：90- 1 80 W， 氣氣流量：1 〇 - 5 0 s c c m， 漠化氫流量：1 〇 〇 - 2 0 0 s c c m，及 氧氣流量：- 3 0 s c c m。 8 本紙張尺L度適用中國國家標準(CNS)A4規格(210X297公爱) 550738 A7 B7 五、發明說明（） 當使用東京電子之8 4DD蝕刻機時，較佳的參數設定 為 · {請先閲讀背面之注意事項再填寫本頁> 壓 力：1 0- 3 0 mtorr， 電漿能量：40〇-800 W， 氣氣流量：20_60 sccm， 溴化氫流量：60-150 seem ’及 氧氣流量：〇-30 sccm。 蝕刻至淺溝渠2 1 〇形成深度約2500埃至4000埃之間。 當完成等向性姓刻之後，接下來則進行灰化處理及濕、式清 洗製程。因此，為了形成本發明之淺溝渠2 10之形狀，而 產生之犧牲層 2 1 4，在此時亦被加以清除，進而形成一帶 有階梯狀輪廓2 1 8之造型，如第二D圖中所示。在淺溝渠 2 10形成後，基材2〇〇的溝渠内緣較穿遂氧化層202的溝 渠内緣略微突出。 經濟部智慧財產局員工消費合作社印製 參見第二E圖，如圖中所示，加熱氧化基材20 0及多 晶矽層204並與穿遂氧化層202步成一襯氧化層212，其 厚度約為1 00埃至300埃。接著再沈積氧化矽於淺溝渠210 及氮化矽層 2 0 6之上，以形成氧化層2 1 6。一般而言，使 用高密度電漿化學氣相沈積（High Density plasma Chemical Vapor Deposition; HDP CVD)以形成此一氣化層 2 1 6。如第二F圖所示，由於使用本發明之自我對準浮置閘 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公楚) 550738 A7 B7 五、發明說明（） 極之淺溝渠結構製造方法，其在形成淺溝渠2 1 〇時，同時 在淺溝渠2 1 0側壁上形成高分子聚合物及氧化物所形成之 犧牲層2 1 4，故使淺溝渠2 1 0内部輪廓形成一階梯狀。♦ 氧化層2 1 6沈積於此淺溝渠2 1 0時，將使形成内部空孔的 機率大幅降低。故使用本發明之自我對準浮置閘極之淺溝 渠結構製造方法，所生產之積體電路之電性將更為穩定， 而產品的品質也將更為優良。熟知此項技藝者，當容易發 現本發明之方法，在触刻多晶石夕層2 0 4、穿遂氧化層 2 〇 2 及基材200，乃至於形成犧牲層214及去除犧牲層214，這 些製程均可使用相同之設備來進行，例如：應用材料之DPS 及東京電子之84DD蝕刻機等，而不必更換其他製程設備。 如此，一方面節省設備轉換時所消耗的時間，另一方面也 減少晶元遭受污染的機率。故本發明更可說是一種具有節 省生產成本及簡化生產流程之自我對準浮置閘極之淺溝渠 隔離結構製造方法。 如熟悉此技術之人員所瞭解的’以上所述僅為本發明 之較佳實施例而已，並非用以限定本發明之申請專利範 圍；凡其它未脫離本發明所揭示之精神下所完成之等效改 變或修飾，均應包含在下述之申請專利範圍内。 .............. (請先閲讀背面之注意事項再填寫本頁) 訂- 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210χ 297公釐)Air flow: Seem per standard cubic centimeter per minute (please read the precautions on the back before filling this page) > Stinky hydrogen flow: 100-200 seem, and oxygen flow '· 1 〇-50 seem . When using Tokyo Electron's 8 4 DD 14 engraving machine, the preferred parameter settings are: pressure: 1 0-3 0 mtorr, electric energy: 4 0 0-8 0 0 W, air flow: 0-5 0 sccm, hydrogen bromide flow: 6 0 -1 5 0 sccm, and oxygen flow · 1 0-5 0 sccm. See Figure 2C. Continue to use a polysilicon etcher (Poly Etcher), for example: DPS of Applied Materials or 84DD Etching Machine of Tokyo Electron, etc. The substrate 200 is etched using a gas. When using the DPS etching machine of applied materials, the preferred parameters are set as follows: Pressure: 4-10mtorr, Plasma energy: 250-500 W, Energy consumption printed by the Intellectual Property Bureau Staff Consumer Cooperative of the Ministry of Economic Affairs: 90- 1 80 W, gas flow rate: 10-50 sccm, desertification hydrogen flow rate: 100-200 sccm, and oxygen flow rate:-30 sccm. 8 This paper rule applies the Chinese National Standard (CNS) A4 specification (210X297 public love) 550738 A7 B7. 5. Description of the invention () When using Tokyo Electron's 8 4DD etching machine, the better parameter setting is · {Please first Read the notes on the back and fill in this page again> Pressure: 1 0- 3 0 mtorr, Plasma energy: 40-800 W, Air flow: 20_60 sccm, Hydrogen bromide flow: 60-150 seem 'and oxygen flow : 0-30 sccm. Etching the shallow trench 2 10 to a depth of about 2500 Angstroms to 4000 Angstroms. After the completion of the isotropic surname engraving, the ashing treatment and the wet-washing process are performed next. Therefore, in order to form the shape of the shallow trench 2 10 of the present invention, the sacrifice layer 2 1 4 is also removed at this time, thereby forming a shape with a stepped profile 2 1 8 as shown in the second D figure. As shown. After the shallow trench 210 is formed, the inner edge of the trench of the substrate 200 is slightly more prominent than the inner edge of the trench passing through the oxide layer 202. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, see Figure 2E. As shown in the figure, the substrate 20 and the polycrystalline silicon layer 204 are heated and oxidized with the tunneling oxide layer 202 to form a liner oxide layer 212. 100 angstroms to 300 angstroms. Next, silicon oxide is deposited on the shallow trench 210 and the silicon nitride layer 206 to form an oxide layer 2 1 6. Generally, a high density plasma chemical vapor deposition (HDP CVD) is used to form this vaporized layer 2 1 6. As shown in Figure 2F, because the self-aligned floating sluice of the present invention is used, the paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297). 550738 A7 B7 5. Description of the invention () Extremely shallow trench structure In a manufacturing method, when a shallow trench 2 1 0 is formed, a sacrificial layer 2 1 4 formed of a polymer and an oxide is simultaneously formed on a side wall of the shallow trench 2 10, so that the inner contour of the shallow trench 2 1 0 is formed into a Stepped. ♦ When the oxide layer 2 1 6 is deposited in the shallow trench 2 1 0, the probability of forming internal voids will be greatly reduced. Therefore, using the method for manufacturing the shallow trench structure of the self-aligned floating gate of the present invention, the electrical property of the integrated circuit produced will be more stable, and the quality of the product will be more excellent. Those skilled in the art, when it is easy to find the method of the present invention, touches the polycrystalline stone layer 204, the tunneling oxide layer 200, and the substrate 200, and even forms the sacrificial layer 214 and removes the sacrificial layer 214. These processes can be performed using the same equipment, such as: Applied Materials' DPS and Tokyo Electron's 84DD etcher without having to replace other process equipment. In this way, on the one hand, it saves the time consumed when the equipment is switched, and on the other hand, it reduces the chance of the wafer being contaminated. Therefore, the present invention can be said to be a method for manufacturing a shallow trench isolation structure with self-aligned floating gates that saves production costs and simplifies the production process. As understood by those familiar with this technology, 'The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application for the present invention; all other things that are completed without departing from the spirit disclosed by the present invention, etc. Effective changes or modifications should be included in the scope of patent application described below. .............. (Please read the precautions on the back before filling out this page) Order-Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs This paper is sized for China National Standard (CNS) A4 Specifications (210χ 297 mm)