經濟部中央標準局員工消費合作社印製 548821 030414-91042專利說明書B.DOC - 2/10 B7 五、發明説明（f ) 【技術領域】 本發明係關於一種藉由ITO走線方式與阻值規範 達到靜電防治功效之設計方法，特別是指一種在LCD 做ITO設計時，同時考慮最佳化阻抗值，使走線佈局 5 方式符合提高ESD防護功能，並大幅減少製程及材料 的使用成本。 【先前技術】 有鑑於LCD Driver 1C的設計需要考量到靜電防護， 因此習用之靜電防治技術及其缺點，如下所述： 10 ⑴在玻璃上加電容或抗靜電元件，其缺點係於製 程上不易達成，因在機台上Bonding元件時，易造成玻 璃脆裂，且COG上要預留走線空間，使得原本設計空 間變的更加狹小； (2) 在FPC上設計ESD防護裝置，其缺點為不能完全 15 防止靜電的危害，因為靜電並非完全由FPC進入，也 有可能從玻璃上的ITO進入1C内部； (3) 單純提高走線阻抗值，其缺點是因未明確規範 走線方式，使功率轉換成熱能時，易因走線粗細的 改變，產生熱量集中不易散熱而燒毁短路； 20 (4)阻抗值過低或過高，其缺點係在於若阻值過 低，則無法達到靜電防護功能；若阻抗值過高，則 會因阻抗過高造成數位、類比訊號衰減，影響1C工作 效能。 因此，有鑑於LCD Driver 1C的設計需要考量到靜電 -2- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 83. 3.10,000 --------JP-批衣-- (請先閱讀背面之注意事項再填寫本頁) 訂 -¾. 548821 Α7 Β7 030414-91042專利說明書BO〇c 〇/1〇 % 五、發明説明（：） — 防4所以須加入靜電防護電路或元件，造成忙體積 因電路增加而使單價提高，若以現有的COG模組加入 靜電防護設計，除可達到靜電防護，同時可降低採 購成本’增加產品競爭力。在輔助保護技術中將走 5線變細並增加長度來提高重置腳位離值，防 止外部雜訊干擾正“作，但並未規範走線阻值和 走線方式。 由此可見，上述習用技術仍有諸多缺失，實非一 良善之设什者’而亟待加以改良。 1〇 本案發明人鑑於上述習用靜電防治方法所衍生的 各項缺點，乃亟思加以改良創新，並經多年苦心孤 言旨潛心研究後’終於成功研發完成本件一種藉由ιτ〇 走線方式與阻值規範達到靜電防治功效之設計方 (請先閱讀背面之注意事項再填寫本頁) ▼項再4 裝· 訂 經濟部中央標準局員工消費合作社印製 15【發明目的】本發明之目的係在於提供一種藉由IT〇走線方式 與阻值規範達到靜電防治功效之設計方法，係可避 免因ΙΤΟ走線方法失當，而造成靜電防護能力失效，而使靜電破壞IC、其他元件，或外來突波雜訊的干 20 擾。本發明之次一目的係在於提供一種藉由ιτ〇走線 方式與阻值規範達到靜電防治功效之設計方法，只 藉ΙΤΟ在COG的走線方式來增加靜電防護力，比一般靜電防護裝置’減少設計及製作成本。 83. 3. 10,000548821 030414-91042 Patent Specification B.DOC-2/10 B7 printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the Invention (f) [Technical Field] The present invention relates to a wiring method and resistance specification by ITO The design method to achieve the effect of static electricity prevention, especially refers to an ITO design of the LCD, while considering the optimization of the impedance value, so that the layout of the 5 ways of line conforms to improve the ESD protection function, and greatly reduce the cost of process and materials. [Previous technology] In view of the need to consider static electricity protection in the design of LCD Driver 1C, the conventional static electricity prevention technology and its shortcomings are as follows: 10 加 Adding capacitors or antistatic components to glass, its shortcomings are not easy in the manufacturing process Achieved, because the bonding component on the machine is easy to cause glass brittleness, and the routing space on the COG should be reserved, so that the original design space becomes narrower. (2) The ESD protection device on the FPC has the disadvantages of Can't completely prevent the harm of static electricity, because static electricity is not completely entered by FPC, and it is possible to enter the interior of 1C from ITO on glass; (3) Simply increasing the resistance value of the wiring, the disadvantage is that the power of the wiring is not clearly regulated to make power When converted into thermal energy, it is easy to burn the short circuit due to the change in the thickness of the wiring, which is difficult to dissipate heat. 20 (4) The resistance value is too low or too high. The disadvantage is that if the resistance value is too low, the electrostatic protection cannot be achieved. Function; if the impedance value is too high, the digital and analog signals will be attenuated due to the high impedance, which will affect the 1C work efficiency. Therefore, in consideration of the design of LCD Driver 1C, static electricity needs to be taken into account. -2- This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X297 mm) 83. 3.10,000 -------- JP-Approved -(Please read the precautions on the back before filling this page) Order-¾. 548821 Α7 Β7 030414-91042 Patent Specification BO〇c 〇 / 1〇% 5. Description of the invention (:) — Anti-static 4 Circuits or components, causing the busy volume to increase due to the increase in the unit price. If the existing COG module is added to the electrostatic protection design, in addition to achieving electrostatic protection, it can reduce procurement costs and increase product competitiveness. In the auxiliary protection technology, the 5th line is thinned and the length is increased to increase the reset pin off value to prevent external noise interference, but it does not standardize the resistance and the way of the line. It can be seen that the above There are still many shortcomings in conventional technology, and it is not a good design. It needs to be improved. 10 In view of the various shortcomings derived from the above-mentioned conventional static electricity prevention methods, the inventor of this case is eager to improve and innovate, and after years of hard work After meticulous research, he finally successfully developed a designer who achieves the effect of static electricity prevention through ιτ〇 wiring method and resistance value specification (please read the precautions on the back before filling this page) ▼ Item 4 Packing · Ordered by the Consumer Standards Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. 15 [Objective] The purpose of the present invention is to provide a design method to achieve static electricity prevention and control effects through IT0 wiring method and resistance value specification. Improper method will cause the static electricity protection ability to fail, and cause static electricity to damage IC, other components, or interference of external surge noise. A second object of the present invention is In order to provide a design method that achieves the effect of static electricity prevention through the ιτ〇 wiring method and resistance value specification, only the ITO cable routing method in COG is used to increase the electrostatic protection force, which reduces the design and manufacturing costs compared to ordinary electrostatic protection devices. 83 . 3. 10,000
15 548821 五 '發明説明（今） 本發明之另一目的即在於提供一種藉由ITO走線 方式與阻值規範達到靜電防治功效之設計方法，係 不需外加任何元件，以減少增加元件所造成的其他 效應。 本發明之又一目的係在於提供一種藉由IT0走線 方式與阻值規範達到靜電防治功效之設計方法，係 可簡化製作流程及複雜性。 【技術内容】 可達成上述發明目的之一種藉由ΙΤ0走線方式與 阻值規範達到靜電防治功效之設計方法，其特徵是IC 和玻璃接觸的ITO走線，以特殊出PIN腳的阻值設計， 使欲進入1C之靜電，可藉由特殊的IT〇塗佈設計有效 地疏導消散，提高1C對靜電的防護能力，減少供給IC 月b里的消耗，本發明作法如下所述： ⑴重置指令控制接腳(Reset pin)的走線規範：在IT0 走線方式，在轉折處以圓弧角設計，而角度設計列 入規範，而此繞線方式以符合適當的阻抗值。 (2) 重要類比電路腳位的走線繪製規範··類比腳位 不因空間利用問題，因此以最低功率消耗為優先考 量’減少電源運送間的消耗。 (3) 其餘腳位走線方式採由粗漸細規範，以避免面 積急遽變化：其餘腳位走線方式（同時考量利用面 積），改採1C腳位端到連接端最小間距為設計要點。 (4) 重置品令控制接腳（Reset ρίη)阻值規範··考量π --------0^------1T------ (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 83. 3.10,000 -4 - 548821 a ' 030414-91042專利說明書B.DOC - 5/10 _ B7__ 五、發明説明（4) 設計時是否加入南阻抗’如未加入南阻抗時’設計 一最佳串接阻抗抗雜訊干擾，若已加入則數值直接 納入考量。 【圖式簡單說明】 5 請參閱以下有關本發明一較佳實施例之詳細說明 及其附圖，將可進一步瞭解本發明之技術内容及其 目的功效；有關該實施例之附圖為： 圖一為IT0導線電路製程之流程圖； 圖二為以WI-C1402X改善前走線製造圖； 10 圖三為以WI-C1402X改善後走線製造圖； 圖四為以WI-C1402X改善後重置腳位規範一示意 圖； 圖五為以WI-C1402X改善後重置腳位規範二示意 圖； 15 圖六為以WI-C1402X改善後重置腳位規範三示意 圖， 圖七為以WI-C1402X改善後重置腳位規範四示意 圖； 圖八為高壓靜電燒毁鄰近腳位之示意圖； 20 圖九為WD-G0906V3改善後走線製造圖； 圖十為連接端之轉折處快速由粗變細造成燒毁實 例示意圖； 圖十一為轉角處以直角轉折造成燒毀實例一示意 圖；以及 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 則 --------裝-- (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局員工消費合作社印製 83. 3. 10,000 經濟部中央標準局員工消費合作社印製 548821 ηί 030414-91042專利說明書 B.DOC - 6/10 _________ 五、發明説明（$) 圖十二為轉角處以直角轉折造成燒毀實例二示意 圖。 【較佳實施例】 請參閱圖一，為ιτο導線電路製程之流程圖，由 5圖中可知，本發明ITO線路走線方式設計乃於電路圖 案設計與Layout設計階段211實施，進而形成一電路圖 案22，再經光罩製程23，在ITO導線電路玻璃製程1中 之微影步驟16中使用，進而提供一 1C在COG製程上使 用。 10 本發明之一種藉由ITO走線方式與阻值規範達到 靜電防治功效之設計方法，其特徵是1C和玻璃接觸的 ιτο走線，以特殊出PIN腳的阻值設計，使欲進入IC之 靜電，可藉由特殊的ITO塗佈設計有效地疏導消散， 提高1C對靜電的防護能力，減少供給IC能量的消耗； I5本發明作法如下所述： (1) 重置指令控制接腳（Reset Pin)的走線規範··在ιτο 走線方式，在轉折處以圓弧角設計，而角度設計列 入規範，而此繞線方式以符合適當的阻抗值。 (2) 重要類比電路腳位的走線繪製規範：類比腳位 20不因空間利用問題，因此以最低功率消耗為優先考 量’減少電源運送間的消耗。 (3) 其餘腳位走線方式採由粗漸細規範，以避免面 積急遽變化：其餘腳位走線方式（同時考量利用面 積），改採1C腳位端到連接端最小間距為設計要點。 --------0^-- (請先閱讀背面之注意事項再填寫本頁)15 548821 Five 'invention description (today) Another object of the present invention is to provide a design method to achieve static electricity prevention and control effect through ITO wiring method and resistance specification, which does not require any additional components to reduce the damage caused by adding components. Other effects. Another object of the present invention is to provide a design method for achieving static electricity prevention and control effects by using the IT0 routing method and resistance value specification, which can simplify the manufacturing process and complexity. [Technical content] A design method that can achieve the above-mentioned purpose of the invention to achieve the effect of static electricity prevention through the ITO routing method and resistance value specification, which is characterized by the ITO wiring of the IC and glass contact, and the resistance value design of the special PIN pin To make the static electricity entering 1C, it can effectively dissipate and dissipate through the special IT0 coating design, improve the protection ability of 1C against static electricity, and reduce the consumption in IC b. The method of the present invention is as follows: ⑴ Reset The wiring specifications of the reset pin: In the IT0 wiring mode, the corner design is designed at the turning point, and the angle design is included in the specification, and this winding method is in accordance with the appropriate impedance value. (2) Specifications for drawing traces of important analog circuit pins · Analogue pins Because of space utilization problems, the lowest power consumption is a priority consideration 'to reduce the consumption of power supply transportation. (3) The remaining pin routing methods are standardized by thickness and thickness to avoid sudden changes in area: the remaining pin routing methods (while considering the use of area), use the minimum distance from the 1C pin end to the connection end as the design point. (4) Resistance specification of reset control pin (Reset ρίη) ·· Consider π -------- 0 ^ ------ 1T ------ (Please read the Please fill out this page again) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 83. 3.10,000 -4-548821 a '030414-91042 Patent Specification B.DOC-5/10 _ B7__ V. Description of Invention (4) Design Whether to add south impedance when it is not used. If no south impedance is added, design an optimal series impedance to resist noise interference. If it is added, the value is directly taken into consideration. [Brief description of the drawings] 5 Please refer to the following detailed description of a preferred embodiment of the present invention and the accompanying drawings to further understand the technical content of the present invention and its purpose and effect; the drawings related to this embodiment are: The first is the flow chart of the IT0 wire circuit manufacturing process; Figure two is the wiring diagram before the improvement with WI-C1402X; 10 Figure three is the wiring diagram after the improvement with WI-C1402X; Figure four is the reset after improvement with WI-C1402X Schematic diagram of pin specifications 1. Figure 5 is a schematic diagram of resetting the pin specifications after improvement with WI-C1402X; 15 Figure 6 is schematic diagram of the resetting pin specifications after improvement with WI-C1402X. Figure 7 is a schematic diagram after resetting with WI-C1402X Schematic diagram 4 of reset pin specifications; Figure 8 is a schematic diagram of high-voltage electrostatic burnout of adjacent pins; 20 Figure 9 is an improved wiring manufacturing diagram of WD-G0906V3; Figure 10 is a rapid turning of the connection end caused by coarsening and thinning Figure 11 is a schematic diagram of an example of burnout caused by a right-angle turn at a corner; and this paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm). Read the note on the back first Please fill in this page again) Order printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 83. 3. 10,000 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 548821 ηί 030414-91042 Patent Specification B.DOC-6/10 _________ V. Invention Explanation ($) Figure 12 is a schematic diagram of burnout example 2 caused by a right-angle turn at a corner. [Preferred embodiment] Please refer to FIG. 1, which is a flowchart of the process of the ιτο wire circuit. As can be seen from FIG. 5, the design of the ITO line routing method of the present invention is implemented in the circuit pattern design and layout design stages 211, thereby forming a circuit. The pattern 22 is then used in the photolithography step 16 in the ITO wire circuit glass process 1 through the mask process 23, and then a 1C is used for the COG process. 10 The design method of the present invention for achieving static electricity prevention and control effects through ITO wiring method and resistance specification, which is characterized by ιτο wiring that is in contact with glass, with a special PIN pin resistance value design, so as to enter the IC Static electricity can be effectively dissipated and dissipated by special ITO coating design, improving 1C's protection against static electricity, and reducing the consumption of IC energy; I5 The method of the present invention is as follows: (1) Reset command control pin (Reset Pin) wiring specifications · In the ιτο routing method, the arc design is used at the turning point, and the angle design is included in the specification, and this winding method is to meet the appropriate impedance value. (2) Specifications for drawing traces of important analog circuit pins: Analog pin 20 does not have space utilization issues, so the lowest power consumption is a priority consideration 'to reduce the power consumption between shipping. (3) The remaining pin routing methods are standardized by thickness and thickness to avoid sudden changes in area: the remaining pin routing methods (while considering the use of area), use the minimum distance from the 1C pin end to the connection end as the design point. -------- 0 ^-(Please read the notes on the back before filling this page)
、1T -1¾ -6-, 1T -1¾ -6-
經濟部中央標準局員工消費合作社印製 548821 030414-91042專利說明書B.DOC - 7/10 B7 五、發明説明（G ) ⑷重置指令控制接腳（Reset Pin)阻值規範：考量1C 設計時是否加入高阻抗，如未加入高阻抗時，設計 一最佳_接阻抗抗雜訊干擾，若已加入則數值直接 納入考量。 5 運用本發明所施行的案例有下列兩實例： 實例一 型號WI-C1402X，使用聯詠科技STN驅動1C : NT7651，此1C為一般驅動波型、正液晶驅動電壓，一 般ITO走線方式是利用1C腳位到連接端所有空間，如 10 圖二所示；而藉由本發明所改進ITO的走線方式，則 如圖三所示；改進後的ITO走線方式考慮三項原則： (1) IC腳位位置連接端最短距離； (2) 重要類比電壓腳位位置； (3) 重置腳位（Reset Pin)走線規範，如圖四、五、 15 六、七所示； (4) 重置腳位（Reset Pin)走線阻抗值，避免因阻抗值 的計算迷思，而使1C腳位端及連接端寬度增加、ITO 走線粗細變化率過大（造成熱量在導線收縮處散熱不 易而使ITO走線燒毁斷路）、避免走線直角設計（避免 20 熱量集中而造成ITO尖端放電效應而影響鄰近走線， 如燒燬圖八）、避免阻抗設計失當而使原本1C功能運 作失常，除以上考量外，並可使靜電測試可提高抗 靜電效力。 實例二 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 83. 3.10,000 --------^裝-- (請先閱讀背面之注意事項再填寫本頁) 訂_ 15 548821 ____B7 〇30414·91042專利說明書 b.doc .8/1〇 五、發明説明（Π ) ^~' '—'—^———一 型號WD-G_6V3，使用三星科技STN驅動 0756,此IC為一般驅動波型、正液晶形驅動電 壓，此1C在原公司以晶片模式下作靜電測試時，通過 位階，在模組設計階段，原設計走線考慮提升如姐 5 Pin阻抗值以提升靜電防護能力不足，走線方式是利 用1C腳位到連接端空間以轉折方式佈線。但由實際靜 電模擬驗證下，走線仍然燒毀，如圖十、十一、十 二所示，連接端之轉折處快速由粗變細，且以直角 方式轉折，造成轉折變化處燒毀；改變走線，如圖 十一所示。修改轉折處為圓弧及走線漸進縮收.，如 圖九所示。再作相同靜電模擬驗證，在同一腳位發 現對抗靜電能力有所提升。 【特點及功效】 一本發明所提供之一種藉由IT〇走線方式與阻值規 範達到靜電防治功效之設計方法，與其他習用技術 相互比較時，更具有下列之優點： 一、 本發明一種藉由ΙΤ0走線方式與阻值規範達 到靜電防治功效之設計方法，係不需外加任何元 件，以減少增加元件所造成的其他效應。 二、 本發明一種藉由ΙΤ0走線方式與阻值規範達 到靜電防治功效之設計方法，係可簡化增加ESD防護 元件之製作流程及複雜性。 二、本發明一種藉由IT0走線方式與阻值規範達 到靜電防治功效之設計方法，係可避免因ΙΤ0走線方 —0^------、玎------MW (請先閲讀背面之注意事項再填寫本頁) 經濟部中央榡準局員工消費合作社印製Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 548821 030414-91042 Patent Specification B.DOC-7/10 B7 V. Description of the Invention (G) ⑷Reset Command Control Pin (Reset Pin) Resistance Specification: Consider 1C design Whether to add high impedance. If high impedance is not added, design an optimal _ impedance to resist noise interference. If it is added, the value will be directly considered. 5 There are two examples of cases implemented by the application of the present invention: Example 1 Model WI-C1402X, using Novatek STN to drive 1C: NT7651, this 1C is a general driving wave type, positive liquid crystal driving voltage, the general ITO wiring method is to use 1C pin to all the space of the connection end, as shown in Figure 2 of Figure 10; and the routing method of ITO improved by the present invention is shown in Figure 3. The improved ITO routing method considers three principles: (1) IC pin position shortest distance from the connection end; (2) important analog voltage pin position; (3) reset pin (Reset Pin) wiring specifications, as shown in Figures 4, 5, 15, 6 and 7; (4) Reset pin trace resistance value to avoid the calculation of impedance value, which will increase the width of the 1C pin end and the connection end, and the rate of change of the thickness of the ITO trace will be too large (which makes it difficult to dissipate heat at the shrinkage of the wire) The ITO traces are burned and broken), avoiding the right-angle design of the traces (to avoid the ITO tip discharge effect caused by the concentration of 20 heat, which affects the adjacent traces, such as burnout Figure 8), and to prevent the improper impedance design and make the original 1C function malfunction. In addition to the above considerations, and The static test can improve the anti-static effect. Example 2: This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 83. 3.10,000 -------- ^ installed-(Please read the precautions on the back before filling this page) Order _ 15 548821 ____B7 〇30414 · 91042 Patent Specification b.doc .8 / 1〇 5. Description of Invention (Π) ^ ~ '' —'— ^ ——— A model WD-G_6V3, using Samsung Technology STN driver 0756, this The IC is a general driving wave type and a positive liquid crystal driving voltage. This 1C passed the level when the original company conducted the electrostatic test in the wafer mode. At the module design stage, the original design trace was considered to increase the resistance of the 5pin to increase static electricity. Insufficient protection capability. The wiring method is to use the 1C pin to the connection terminal space to make a twisted wiring. However, under the actual electrostatic simulation verification, the traces were still burned. As shown in Figures 10, 11, and 12, the turning point at the connection end quickly changed from thick to thin and turned at right angles, causing the turning change to burn out. Line, as shown in Figure 11. Modify the turning point to gradually shrink the arc and traces, as shown in Figure 9. After doing the same static simulation verification, it was found that the antistatic ability was improved at the same pin. [Features and effects] A design method provided by the present invention to achieve the effect of static electricity prevention through the IT0 routing method and resistance value specification has the following advantages when compared with other conventional technologies: 1. A kind of the present invention The design method of achieving static electricity prevention and control effect through the ITO routing method and resistance specification does not require any additional components to reduce other effects caused by adding components. 2. A design method for achieving static electricity prevention and control effects through the ITO routing method and resistance specification of the present invention is to simplify and increase the manufacturing process and complexity of ESD protection components. 2. A design method for achieving static electricity prevention and control effects by using the IT0 wiring method and resistance specification according to the present invention is to avoid the ITO 0 wiring side—0 ^ ------, 玎 ------ MW ( (Please read the notes on the back before filling out this page.)
83. 3.10,000 548821 A7 B7 030414-91042專利說明書B.DOC - 9/10 五、發明説明（公） 法失當，而造成靜電防護能力失效，而使靜電破壞 ic、其他元件，或外來突波雜訊的干擾。 四、本發明一種藉由ITO走線方式與阻值規範達 到靜電防治功效之設計方法，只藉IT〇在COG的走線 5方式來增加靜電防護力，比一般靜電防護裝置，減 少設計及製作成本。 上列詳細說明係針對本發明之一可行實施例之具 體說明，惟該實施例並非用以限制本發明之專利範 圍，凡未脫離本發明技藝精神所為之等效實施或變 10更，均應包含於本案之專利範圍中。 綜上所述，本案不但在技術思想上確屬創新，並 能較習用物品增進上述多項功效，應已充分符合新 穎性及進步性之法定發明專利要件，爰依法提出申 請，懇請貴局核准本件發明專利申請案，以勵發 15明，至感德便。 ^^裝 訂 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 83. 3.10,000 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇><297公釐）83. 3.10,000 548821 A7 B7 030414-91042 Patent Specification B.DOC-9/10 V. Inventive (public) law is improper, which causes the electrostatic protection ability to fail, and static electricity destroys ICs, other components, or external surges Noise interference. 4. The design method of the present invention to achieve the effect of static electricity prevention through the ITO wiring method and resistance value specification. It only uses IT0 in the 5 way of COG to increase the electrostatic protection force, which reduces the design and production than the general electrostatic protection device. cost. The above detailed description is a specific description of a feasible embodiment of the present invention, but this embodiment is not intended to limit the patent scope of the present invention. Any equivalent implementation or change without departing from the technical spirit of the present invention should be Included in the patent scope of this case. To sum up, this case is not only technically innovative, but also enhances the above-mentioned multiple effects over conventional items. It should have fully met the requirements for novel and progressive statutory invention patents, and applied in accordance with the law. We ask your office to approve this. The invention patent application should be inspired 15 minutes to the utmost. ^^ Binding (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 83. 3.10,000 This paper size applies to the Chinese National Standard (CNS) A4 specification (21〇 > < 297 mm)