TW525113B - ITO layout method capable of increasing IC step-up stability - Google Patents

ITO layout method capable of increasing IC step-up stability Download PDF

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Publication number
TW525113B
TW525113B TW90116176A TW90116176A TW525113B TW 525113 B TW525113 B TW 525113B TW 90116176 A TW90116176 A TW 90116176A TW 90116176 A TW90116176 A TW 90116176A TW 525113 B TW525113 B TW 525113B
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Taiwan
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pin
ito
stability
line impedance
boost
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TW90116176A
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Chinese (zh)
Inventor
Shing-Fa Wang
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Wintek Corp
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Priority to TW90116176A priority Critical patent/TW525113B/en
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Publication of TW525113B publication Critical patent/TW525113B/en

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Abstract

An ITO layout method capable of increasing IC step-up stability is proposed in the invention. The invention comprises the following steps. For the driver IC bonding position on LCD module (COG type) and interface position, an appropriate line impedance is designed for each pin function and application. In order to design the appropriate line impedance, an ITO width of Interface pin is made to have a thick design and a thin design. Consequently, the step-up efficiency and stability of step-up circuit in IC are increased.

Description

525113 A7 五、發明說明( B7 PA90070C.TWP - 3 / 10 10 15 經濟部智慧財產局員工消費合作社印製 20 【技術領域】本創作係關於一種可提高1C之升壓穩定度的ITO走線 方法。【先前技術】 會、片文,在這個資訊爆炸的時代裡,如何讓各種訊息以最 簡便的方或,太, 曰、、, 、在取短的時間裡,傳達至消費者身上,相信 疋消費者所重_,諸如股市行情或是睛隨地得到最新 、: '訊W等皆是,而在行動電話使用率幾乎達到人手一 、、、狀/兄下,行動電話 這個擁有顯示幕的電子機具, P為^工商界運用的最佳媒介;惟,凡熟悉此項技藝者均 A仃動電浩的顯示幕之所以可以顯示各項訊息,主要乃 係個與其顯示幕連結之1C配合以IT0走線構成之電路及 相關微電元件所連結構成。 、而自用ΙΤΟ走線因具透明度與導電性,又利於加工於 :上,知其製作成LCD Module,即可廣泛應用於各電 子^叩。例如應用於行動電話時,固利於工商業界藉由行 動私活傳輸大量複雜訊息。傳統在LCD Module(COG type)的 Intei:iaee pin腳的 ITO layout 都是使用一樣 pitch 寬度 、十,叫參考圖二。並未針對各Interface pin的用途與功 月匕,來设計適當的線阻抗。但鑑於LCDDriverIC使用内部 升疋’ ¥遇到V〇p升壓不穩定,升壓效率不彰的問題;由 糸Vop升壓不穩定,進而產生lcd畫面切換時有顯示字節 有色深色淡的情形。以及Cr〇sstalk的問題。若更換忙或是 更改外接線路的電容値,其效果有限。圯本身也可能因製 --------------裝--- (請先閱讀背面之注意事寫本頁) ,線」 525113 五、發明說明(1) A7 B7 PA90070C.TWP-4/10 程或内部設計的問題,致使升壓效率不好。在製程上的良 率也未見有效提昇,是以,如何針對電子零件之特性,以 設計出更理想之電路,即係相關業界開發之首要。 本案創作人鑑於上述習用電予電路所衍生的各項缺 5點’乃至思加以改良創新’並經多年苦心孤詣潛心研究 後,終於成功研發元成本件可提向1C之升壓穩定度的ITO 走線方法。【新型目的】 本創作所提供之一種可提高1C之升壓穩定度的IT0走 10 線方法,其主要步驟包括: 15 ------------裝--- (請先閱讀背面之注意事項寫本頁) 經濟部智慧財產局員工消費合作社印製 20 LCD Module(COG type)上的 Driver IC bonding 處與 Interface 處,針對各pin腳的功能與用途設計出適合的線阻抗;為 了設計出適合的線阻抗,而讓lnterface pin的ITO寬度有粗 有細的設計,以提高1C中昇壓電路的升壓效率及穩定度。 【技術內容】 可達成上述新型目的之一種可提高1(:之升壓穩定度的 ITO走線方法’其主要步驟包括:[CD Module(C〇G type)上 的Driver IC bonding處與Interface處,針對各pin腳的功能與 用途設計出適合的線阻抗;為了設計出適合的線阻抗,而 讓Interfacepin的ITO寬度有粗有細的設計,以提高圯中昇壓 電路的升壓效率及穩定度。【圖式簡單說明】 叫參閱以下有關本發明一較佳實施例之詳細説明及其 附圖,將可進一步瞭解本發明之技術内容及其目的功效; 4- 本紙張尺度適用中國國豕標準(CNS)A4規格(21〇 X 297公爱) 訂 525113 A7 R7 PA90070C.TWP-5 / 10 五、發明說明( 經濟部智慧財產局員工消費合作社印製 有關該實施例之附圖為: 圖一為本發明LCD MODULE中DRIVER 1C處的ITO走 線示意圖; 圖二為傳統方式ITO走線示意圖,其為一規則性的 5 INTERFACE PIN寬度;以及 圖三為本發明ITO走線示意圖,針對各INTERFACEPIN 的功能與用途而設計不同的ITO線阻抗値。【較佳實施例】 本創作所提供之一種可提高1C之升壓穩定度的ITO走 10 線方法,其主要步騾包括: 1. LCD Module(COG type)上的 Driver IC bonding 處與 Interface處,針對各pin腳的功能與用途設計出適合的線阻 抗;為了設計出適合的線阻抗,而讓Interface處pin的ITO 寬度有粗有細的設計,以提高1C中昇壓電路的升壓效率及 15穩定度;其中: 2. 電源輸入端(The Power Supply pin and Ground pin; VDD,VSS ): VDD及VSS的出PIN端要加寬,使ITO阻抗値愈小愈 佳。或於Interface處,使用一條以上的VDD或VSS Interface 20 pin,讓VSS或VDD的線阻抗形成並聯,而讓VDD及VSS的 線阻抗降低。最佳線阻抗約50Ω以下。 3. 調整 v〇p 電壓接腳(The LCD driving voltage pin and the Bias driving voltage pin ;例如 k 6,FL2〜F/ 5 ) ·· 調整vQP電壓的接腳中,至少KA6走線需加寬,使其線 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項^^寫本頁)525113 A7 V. Description of the invention (B7 PA90070C.TWP-3/10 10 15 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 20 [Technical Field] This creation is about an ITO wiring method that can improve the stability of the 1C boost voltage [Previous technology] Meetings and videos, in this era of information explosion, how to make all kinds of messages in the most convenient way, too, say ,,,,, in a short time, to the consumers, believe疋 Consumers ’attention, such as stock market quotes or getting the latest updates everywhere: 'News, W, etc. are all available, and mobile phone usage has almost reached the level of manpower, mobile phones, and mobile phones. Electronic equipment, P is the best medium used by the industrial and commercial circles; however, anyone who is familiar with this technology can display various information on the display screen of the main electric hosing, which is mainly a 1C connection with its display screen. The circuit composed of IT0 traces and related microelectronic components are connected. The self-use ITO circuit is transparent and conductive, which is also conducive to processing. It is known that it is made into an LCD Module, which can be widely used in Electronic ^ 叩. For example, when applied to mobile phones, Gu Li is used to transmit a large number of complex messages by the private industry. Traditionally, the LCD module (COG type) Intei: iaee pin ITO layout uses the same pitch width, ten, It is called refer to Figure 2. The proper line impedance is not designed for the purpose and function of each Interface pin. However, in view of the LCDDriverIC's use of internal boost 疋 ¥ encountered V volt boost instability, boost efficiency is not outstanding The problem is that the Vop boost is unstable, which causes the display byte to be colored and dark when the LCD screen is switched. And the problem of Crosstalk. If the replacement is busy or the capacitance of the external line is changed, the effect is limited. . 圯 itself may also be installed due to the system -------------- (Please read the note on the back to write this page first), line "525113 V. Description of the invention (1) A7 B7 PA90070C.TWP-4 / 10 process or internal design problems, resulting in poor boost efficiency. The yield in the process has not been effectively improved, so how to design a more ideal circuit based on the characteristics of electronic parts , Which is the primary development of related industries. In view of the above-mentioned 5 points that are derived from the conventional electric power circuit, the creators of this case have “even thought of improving and innovating” and after years of painstaking and meticulous research, they have finally successfully developed ITO, which can increase the stability of the components to 1C. Cable routing method. [New purpose] A 10-wire routing method for IT0 that can improve the boost stability of 1C is provided. The main steps include: 15 ------------ installation-- -(Please read the notes on the back first to write this page) The driver IC bonding and interface on the LCD Module (COG type) printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs are designed for the function and purpose of each pin. Suitable line impedance; In order to design a suitable line impedance, the ITO width of the lnterface pin has a thick and thin design to improve the boosting efficiency and stability of the boost circuit in 1C. [Technical content] An ITO wiring method that can improve the stability of boost voltage 1 ': The main steps include: Driver IC bonding and Interface on the [CD Module (C〇G type)] In order to design the appropriate line impedance for the function and use of each pin, in order to design a suitable line impedance, the ITO width of Interfacepin has a thick and thin design to improve the boosting efficiency Stability. [Brief description of the drawings] Please refer to the following detailed description of a preferred embodiment of the present invention and its accompanying drawings to further understand the technical content of the present invention and its purpose and efficacy; 4- This paper size is applicable to China豕 Standard (CNS) A4 specification (21〇X 297 public love) Order 525113 A7 R7 PA90070C.TWP-5 / 10 V. Description of the invention (Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs on this embodiment: Figure 1 is a schematic diagram of the ITO trace at DRIVER 1C in the LCD module of the present invention; Figure 2 is a schematic diagram of the traditional ITO trace, which is a regular 5 INTERFACE PIN width; and Figure 3 is the ITO trace of the present invention Schematic diagram, designing different ITO line impedances for each function and purpose of INTERFACEPIN. [Preferred Embodiment] A ITO 10-wire method that can improve the boost stability of 1C is provided in this creation. The main steps include: : 1. Driver IC bonding and Interface on LCD Module (COG type), design the proper line impedance for the function and use of each pin; In order to design the appropriate line impedance, let the ITO width of the pin at the Interface There are thick and thin designs to improve the boost efficiency and 15 stability of the boost circuit in 1C; Among them: 2. The Power Supply Pin and Ground Pin (VDD, VSS): The output of VDD and VSS The PIN end should be widened to make the ITO impedance as small as possible. Or at the Interface, use more than one VDD or VSS Interface 20 pin to make the VSS or VDD line impedance in parallel, and reduce the VDD and VSS line impedance. The optimal line impedance is below 50Ω. 3. Adjust the LCD driving voltage pin and the Bias driving voltage pin; for example, k 6, FL2 ~ F / 5. ·· Adjust the vQP voltage , At least KA6 routing needs Widen to make the line The size of this paper applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back first ^ Write this page)

M 裝 訂---------線^^ 525113 PA90070C.TWP - 6 / 10 A7 B7 五、發明說明(j ) 阻抗之阻値在100Ω以下,其餘匕,〜匕則至少在150Ω以下, 若其線阻抗能與&相同較佳。 . 4·升壓電路中外接電容接腳(Boosting pin ;例如C3N, ClP,ClN,C2NandC2P):升壓控制接腳ITO電阻値需約於150 5 Ω以下0 5·為了上述腳位Layout處有足夠空間來使走線加寬; 使上述腳位的ITO線阻抗愈小愈好。本設計有縮小數位信 號線的Layout寬度,使數位信號線ITO線阻抗値約 150〜1000Ω左右。(例如031.0/(:,\\^,110,00〜07,€86等) 10 圖中各代表符號的電位及功能係如下列表一所示者: - ----!!!!裝 i I (請先閱讀背面之注意事項寫本頁) 經濟部智慧財產局員工消費合作社印製 NO SYMBOL LEVEL FUNCTION 1 C86 Input VICU parallel interface selection input. 2 VSS Low Ground. A reference for the logic pins. 3 V5 Supply The most negative LCD 4 V4 Supply The LCD driving voltage levels. 5 V3 Supply The LCD driving voltage levels. 6 V2 Supply The LCD driving voltage levels. 7 VI Supply The LCD driving voltage levels. 8 CAP2+ Output When internal DC-DC voltage converter is used. 9 CAP2- Output When internal DC-DC voltage converter is used. 10 CAP1- Output When internal DC-DC voltage converter is used. 11 CAP1+ Output When internal DC-DC voltage converter is used. 12 CAP3- Output When internal DC-DC voltage converter is used. 訂·· 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 525113 PA90070C.TWP - 7 / 10 A7 B7 13 VOUT I/O The most negative voltage supply pin of the chip. 14 VSS Low Ground. A reference for the logic pins.. 15 VDD High Chip’s Power Supply pin· 16 D7 H/L Data bus to be connected to the MCU. 17 D6 H/L Data Ws to be connected to the MCU. 18 D5 H/L Data bus to be connected to the MCU. 19 D4 H/L Data bus to be connected to the MCU. 20 D3 H/L Data bus to be connected to the MCU. 21 D2 H/L Data bus to be connected to the MCU. 22 D1 H/L Data bus to be connected to the MCU. 23 D0 H/L Data bus to be connected to the MCU. 24 /RD,E I/O The MCU interface input. 25 /WR,R/W I/O The MCU interface input. 26 AO Input Data/Command control pin. 27 /RES Input Reset signal input. 28 /CS1 Input The chip select input. --------------裝—— A <請先閱讀背面之注意事項HI寫本頁) 【表一】 五、發明說明) 【特點及功效】 本創作所提供之一種可提高1C之升壓穩定度的ITO走 線方法’與習用技術相互比較時,更具有下列之優點: 經濟部智慧財產局員工消費合作社印製M binding --------- line ^^ 525113 PA90070C.TWP-6/10 A7 B7 V. Description of the invention (j) Impedance resistance is below 100Ω, the remaining daggers, ~ daggers are at least 150Ω, It is better if the line impedance can be the same as &. 4 · External capacitor pin (Boosting pin; for example, C3N, ClP, ClN, C2NandC2P) in boost circuit: boost control pin ITO resistance 値 need to be below 150 5 Ω 0 5 · For the above pin layout Sufficient space to widen the traces; the smaller the ITO line impedance, the better. In this design, the layout width of the digital signal line is reduced, so that the impedance of the digital signal line ITO line is approximately 150 ~ 1000Ω. (Such as 031.0 / (:, \\ ^, 110,00 ~ 07, € 86, etc.) 10 The potential and function of each representative symbol in the figure are as shown in the following list 1: I (Please read the notes on the back first to write this page) NO SYMBOL LEVEL FUNCTION 1 C86 Input VICU parallel interface selection input. 2 VSS Low Ground. A reference for the logic pins. 3 V5 Supply The most negative LCD 4 V4 Supply The LCD driving voltage levels. 5 V3 Supply The LCD driving voltage levels. 6 V2 Supply The LCD driving voltage levels. 7 VI Supply The LCD driving voltage levels. 8 CAP2 + Output When internal DC-DC voltage converter is used. 9 CAP2- Output When internal DC-DC voltage converter is used. 10 CAP1- Output When internal DC-DC voltage converter is used. 11 CAP1 + Output When internal DC-DC voltage converter is used. 12 CAP3- Output When Internal DC-DC voltage converter is used. The size of this paper is applicable to China National Standard (CNS) A4 (210 X 297 mm) 525113 PA90 070C.TWP-7/10 A7 B7 13 VOUT I / O The most negative voltage supply pin of the chip. 14 VSS Low Ground. A reference for the logic pins: 15 VDD High Chip's Power Supply pin · 16 D7 H / L Data bus to be connected to the MCU. 17 D6 H / L Data Ws to be connected to the MCU. 18 D5 H / L Data bus to be connected to the MCU. 19 D4 H / L Data bus to be connected to the MCU . 20 D3 H / L Data bus to be connected to the MCU. 21 D2 H / L Data bus to be connected to the MCU. 22 D1 H / L Data bus to be connected to the MCU. 23 D0 H / L Data bus to be connected to the MCU. 24 / RD, EI / O The MCU interface input. 25 / WR, R / WI / O The MCU interface input. 26 AO Input Data / Command control pin. 27 / RES Input Reset signal input. 28 / CS1 Input The chip select input. -------------- Installation—— A < Please read the note on the back first to write this page) [Table 1] 5. Description of the invention) [Features and effects] When comparing the ITO wiring method provided by this creation with the boosting stability of 1C, compared with conventional technology, Has the following advantages: Ministry of Economic Affairs Intellectual Property Office employees consumer cooperatives printed

1·只改變Driver IC bonding處的ITO走線方式,以減少設 計及製作的成本。 2. 不需外加元件,減少附加元件所造成的影響。 3. 簡化製作流程及複雜性。 4·提高Driver 1C升壓電路的效率及穩定度〇 5.改善量產日寺字節顏色深淺不穩現象。 本紙張尺度適用中國國家標準(CNS)A4規格⑽x 297公爱) 525113 五、發明說明u) 6. 顯示畫面時,能使Cross talk現象減少。 7. 減少消耗電流,增加整體效能。* 上列詳細説明係針對本發明之一可行實施例之具體説 明,惟該實施例並非用以限制本發明之專利範圍,凡未脱 5 離本發明技藝精神所為之等效實施或變更,均應包含於本 案之專利範圍中。 综上所述,本案不但在技術思想上確屬創新,並能較 習用物品增進上述多項功效,應已充分符合新穎性及進步 性之法定發明專利要件,爰依法提出申請,懇請貴局核 10 准本件發明專利申請案,以勵發明,至感德便。 (請先閱讀背面之注意事項 裝--- 寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)1. Only change the ITO wiring method at Driver IC bonding to reduce the cost of design and production. 2. No additional components are required, reducing the impact of additional components. 3. Simplify the production process and complexity. 4. Improve the efficiency and stability of the driver 1C booster circuit. 5. Improve the phenomenon of instability in the color of the Nissho byte in mass production. This paper size applies the Chinese National Standard (CNS) A4 specification ⑽ x 297 public love) 525113 V. Description of the invention u) 6. When the screen is displayed, the Cross talk phenomenon can be reduced. 7. Reduce current consumption and increase overall efficiency. * The above detailed description is a specific description of one feasible embodiment of the present invention, but this embodiment is not intended to limit the patent scope of the present invention. Any equivalent implementation or change that does not depart from the technical spirit of the present invention is Should be included in the patent scope of this case. To sum up, this case is not only technically innovative, but also enhances the above-mentioned multiple effects compared with conventional items. It should have fully met the requirements for statutory invention patents that are novel and progressive, and submitted an application in accordance with the law. This application for an invention patent will be granted to encourage inventions to the greatest extent. (Please read the precautions on the back page first --- Write this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)

Claims (1)

525113 A8 B8 C8 D8 PA90070C.TWP -9/10 經濟部中先標準局員工消費合作社印製 六、申請專利範圍 1· 一種可提高1C之升壓穩定度的ITO走線方法,其主要 步驟包括:LCD Module(COG type)上的 Driver IC bonding 處與Interface處,針對各pin腳的功能與用途設計出適 合的線阻抗;為了設計出適合的線阻抗,而讓 5 Interface處pin的ITO寬度有粗有細的設計,以提高1C中 昇壓電路的升壓效率及穩定度。 2. 如申請專利範圍第1項所述之一種可提高1C之升壓穩 定度的ITO走線方法,其中該特殊PIN腳包括電源輸入 端(The Power Supply pin and Ground pin ; VDD,VSS ): 10 VDD及VSS的出PIN端要加寬,使ITO阻抗値愈小愈 佳;亦可於Interface處,使用一條以上的VDD或VSS Interfacepin,讓VSS或VDD的線阻抗形成並聯,而讓 VDD及VSS的線阻抗降低,最佳線陴抗約50Ω以下。 3. 如申請專利範圍第1項所述之一種可提高1C之升壓穩 15 定度的ITO走線方法,其中該特殊PIN腳包括調整V()p 電壓接腳(The LCD driving voltage pin and the Bias driving Voltage pin ;例如 r/ 6,匕〜。): 調整Vop電壓的接腳中,至少匕走線需加寬,阻値在 100Ω以下,其餘j//2〜f則至少在150Ω以下,若能與j/ J L6 20 相同最佳。 4. 如申請專利範圍第1項所述之一種可提高1C之升壓穩 定度的ITO走線方法,其中該特殊PIN腳包括升壓電路 中外接電容接腳(Boosting pin ;例如 C3N,C1P,C1N,C2N 及C2P):升壓控制接腳ITO電阻値需約於150Ω以下。 -9- (請先閱讀背面之注意事項 本頁) Γ 本紙張尺度適用中國國家標準(CNS ) A4規格(210 X 297公釐) 525113 A8 B8 no PA90070C.TWP-10/10 々、申請專利範圍 5.如申請專利範圍第1項所述之一種可提高1C之升壓穩 定度的ITO走線方法,其中包括為了上述腳位Layout 處有足夠空間來使走線加寬;使上述腳位的ITO線阻 抗値愈小愈好,其具有縮小數位信號線的Layout寬 5 度,使數位信號線ITO線阻抗値在150〜1000Ω之間(例 如 €81.0/(:;\\01,103,00〜07,。86等)。 (請先閲讀背面之注意事項寫本頁) .裝· 訂 線 經濟部中央標準局員工消費合作社印製 10- 本纸張尺度適用中國國家標準(CNS ) A4規格(210X297公釐)525113 A8 B8 C8 D8 PA90070C.TWP -9/10 Printed by the Consumers' Cooperative of the China Standards Bureau of the Ministry of Economic Affairs 6. Application for patent scope 1. An ITO wiring method that can improve the stability of the boost of 1C. The main steps include: On the LCD Module (COG type), the driver IC bonding and interface are designed with suitable line impedance for the function and purpose of each pin. In order to design a suitable line impedance, the ITO width of the pin at 5 Interface is thick. Has a fine design to improve the boost efficiency and stability of the boost circuit in 1C. 2. As described in item 1 of the scope of the patent application, an ITO wiring method capable of improving the step-up stability of 1C, wherein the special PIN pin includes a power input terminal (The Power Supply pin and Ground pin; VDD, VSS): 10 The PIN terminals of VDD and VSS should be widened to make the ITO impedance as small as possible. It is also possible to use more than one VDD or VSS Interface pin at the Interface to make the VSS or VDD line impedance in parallel, and let VDD and The line impedance of VSS is reduced, and the optimal line impedance is less than about 50Ω. 3. As described in item 1 of the scope of the patent application, an ITO wiring method capable of improving 1C step-up stability by 15 degrees, wherein the special PIN pin includes an adjustment V () p voltage pin (The LCD driving voltage pin and the Bias driving Voltage pin; for example, r / 6, DJ ~.): Among the pins that adjust the Vop voltage, at least the DJ wiring should be widened, the resistance should be below 100Ω, and the rest j // 2 ~ f should be at least 150Ω. It is best if it is the same as j / J L6 20. 4. An ITO wiring method that can improve the boost stability of 1C as described in item 1 of the scope of patent application, wherein the special PIN pin includes an external capacitor pin (Boosting pin; for example, C3N, C1P, C1N, C2N and C2P): The ITO resistance of the boost control pin should be below 150Ω. -9- (Please read the note on the back page first) Γ This paper size is applicable to Chinese National Standard (CNS) A4 size (210 X 297 mm) 525113 A8 B8 no PA90070C.TWP-10 / 10 范围, patent application scope 5. An ITO wiring method that can improve the boost stability of 1C as described in item 1 of the scope of the patent application, which includes that for the above-mentioned pin layout, there is enough space to widen the wiring; The smaller the ITO line impedance 小, the better. It has a 5 degree reduction in the layout of the digital signal line, so that the ITO line impedance of the digital signal line is between 150 and 1000 Ω (for example, € 81.0 / (:; \\ 01, 103,00). (~ 07, 86, etc.) (Please read the notes on the back to write this page). Printing and binding. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 10- This paper size applies to China National Standard (CNS) A4. (210X297 mm)
TW90116176A 2001-06-27 2001-06-27 ITO layout method capable of increasing IC step-up stability TW525113B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8730214B2 (en) 2008-05-22 2014-05-20 Silicon Works Co., Ltd. COG panel system arrangement

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8730214B2 (en) 2008-05-22 2014-05-20 Silicon Works Co., Ltd. COG panel system arrangement

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