TW389912B - Method of power supply design for embedded memory - Google Patents

Abstract

This invention is related to the method of power supply design for use in the embedded memory. Three sets of power supply are independently designed for the DRAM, logic unit, and the test mode circuit and I/O port in the chip-design stage. The first set is for the DRAM, the second for the logic unit and the third for the test mode circuit and I/O port. While at the package stage, these three sets of power supply stated above are connected together. As a result, during the chip test stage, the problem of test error or instability due to the DC current generated by the floating node is avoided. The potential problem of latch-up after the package stage is also prevented.

Description

The number of cotton in the Jing Department,-? Ding > Elimination 赀 合 it3691twf.doc / 008 A7 _B7_ V. Description of the invention (I) '~~ " The present invention relates to an embedded memory This invention relates to the design of an internal power supply for an embedded memory to improve the occurrence of instability and mis-testing during testing. The semiconductor industry has been working to increase the efficiency of components while still maintaining or even reducing the cost of such components. The ability to micro-miniaturize or manufacture sub-micron semiconductor components' allows smaller semiconductor wafers to be produced, with the goal of reducing costs. And the use of sub-micron technology can also effectively improve performance. Because under sub-micron technology, smaller density wafers can still provide functions similar to those of higher density wafers, so more wafers can be produced on a semiconductor substrate of a certain size, which reduces process costs and has Other functions. In addition, the other direction taken by the semiconductor industry is to integrate the accumulation of logic elements and memory elements on the same semiconductor chip, in order to reduce the cost of the pair and further exert the component performance. Accumulation can improve gastric performance by reducing the delay between the memory elements of one semiconductor chip and the logic elements of another chip. In addition, if the memory and components are integrated on the same semiconductor wafer, the process cost can also be reduced 'because they can be achieved by sharing specific process steps. For example, the so-called embedded memory is an integrated circuit (1C) that forms a dynamic random access memory (dram) circuit and a logic circuit (logic circintry) on the same semiconductor substrate. This kind of embedded dynamic random access memory can access a large amount of data at high speed. 'It is very helpful for the application of integrated circuits, such as a microprocessor or a digital signal processor. It is an integrated circuit using embedded memory. 3 ____________ --- — — '* ~ This paper size is Shizhou Chinese National Standard Date (C, NS) Λ4 specification (210X297 mm) (Please read the note on the back before filling this page) Order 3691twf.doc / 008 A7 B7 V. Description of the Invention (Work) The structure of a conventional embedded memory is shown in Figure 1. The embedded memory 10 in the figure includes a dynamic random access memory 12 (DRAM), a logic unit 14 and test mode circuit and I / O port 16, among which DRAM12, logic unit 14 and test mode circuit and I / O port 16 all use the same power Vcc to maintain the internal operation of the embedded memory 10. During the test, for the same power source Vcc, the floating element will cause DC power to be generated internally, which will affect the environment and conditions of the DRAM test, resulting in mis-measurement or instability. In addition, it is impossible to measure. The DRAM part actually consumes the current, or whether it exceeds the specification. Therefore, the main purpose of the present invention is to address the above-mentioned shortcomings, including dynamic random access memory, logic cells, and The test mode circuit and the same common power supply of the input and output ports are designed as independent power supplies, so when testing the chip, as long as the test part is connected to the independent power supply, there will be no interference and interference. According to the purpose of the present invention, an embedded memory power supply design method is provided, which is installed in an embedded memory, wherein the embedded memory includes a dynamic random access memory, a logic unit, and a test mode circuit. And I / O, the embedded memory power supply design method includes: designing a first set of power supplies, a first set of power supplies for dynamic random access memory, logic units, and test mode circuits and input / output ports at the chip stage Two sets of power supplies and one third set of power supplies, and the Γ group of power supplies, the second set of power supplies, and the third set of power supplies are independent of each other; and during the packaging stage, the first set of power supplies, the second set of power supplies, and the first Three sets of power are connected together. 4 This paper is in the national standard of China. (CNS) Λ4 specification (2 丨 0χ297 mm) ( (Please read the precautions on the back before filling this page)-* Member of the Manchuria Forestry Bureau h Consumer Cooperative Cooperative Indo 3691twf.doc / 008 A7 B7 Manchurian Department Shirong Standard- " Bureau β Industry Consumer Cooperative Cooperative Yin y 5. Description of the invention (3) Therefore, the main feature of the present invention is the dynamic random access memory, logic unit, and test mode circuits and I / O ports of the embedded memory. When testing at the stage, it can effectively prevent mismeasurement or instability. In addition, in order to avoid potential latch-up problems, the three sets of power supplies are connected during the packaging stage. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1 shows FIG. 2 is a structural diagram of a conventional embedded memory; and FIG. 2 is a structural diagram of an embedded memory according to the embedded memory power supply design method of the present invention. Brief description of the labels: 10, 20: embedded memory 12, 22: dynamic random access memory 14, 24: logic unit 16, 26: test mode circuits and I / O ports

Vcc, Vccl, Vcc2, Vcc3: Power

Vssl, Vss2, Vss3: Power supply 28, 30, 32, 34, 36, 38: Power pad 40, 42: Connection point embodiment, please refer to FIG. 2, which shows the design method of the embedded memory power supply according to the present invention. Structure diagram of embedded memory. The embedded memory 20 in the figure includes a dynamic random access memory 22, 5 (Please read the precautions on the back before filling this page)

This paper is based on the national standard of China ((: NS) Λ4 specification (2 丨 0X297) 嫠 3691twf.doc / 008 A7 B7 printed by the Ministry of Economic Affairs of the Ministry of Economic Affairs and printed by the Consumer Cooperatives " V. Description of the invention (( /) A logic unit 24, and a test mode circuit and I / O port 26. In addition, a power pad 28, 30, 32, 34, 36, 38 is designed in the test mode circuit and I / O 26 respectively. In order to cooperate with the chip stage, the dynamic random access memory 22, logic unit 24 ', and the test mode circuit and the input / output port 26 are respectively designed to design an independent first power supply (vcci and Vssl) and a second power supply (Vcc2 and Vcc2 and Vss2) and a third set of power supplies (vcc3 and Vss3). The first set of power supplies (Vccl and Vssl) 'the second set of power supplies (vcc2 and Vss2) and the third set of power supplies (Vcc3 and Vss3) are, for example, a high power supply and a It can be composed of a low power supply, and the low power supply can be a ground power supply. For testing the dynamic random access memory at the chip stage, as long as the first group of power supplies (Vccl and Vssl) and the third group of power supplies (Vcc3 and Vss3) are connected ). When testing the logic unit, just connect the second group of power ( Vcc2 and Vss2) and the third set of power supplies (Vcc3 and Vss3). To test the entire embedded memory, you need to connect the first set of power supplies (Vccl and Vssl) 'The second set of power supplies (Vcc2 and Vss2) and the third group of power supplies (Vcc3 and Vss3). During the packaging stage, the first group of power supplies (Vcc 1 and Vss 1), the second group of power supplies (Vcc2 and Vss2), and the third group of power supplies (Vcc3 and Vss3) Vss3) Connected Together 'As shown, connect Vccl, Vcc2, and Vcc3 at a connection point 40, and connect Vssl, Vss2, and Vss3 at a connection point 42. This avoids potential latching issues. Therefore, The method of the embedded power meter of the present invention uses independent power supplies to overcome the interference during the test at the wafer stage, and then connects the independent power supplies together at the packaging stage, thereby avoiding the problem of latching. 6 This paper is a standard of Chengzhou China National Standards (CNS) Λ4 specification (21〇 × 297 mm) (Please read the notes on the back before filling this page), τ 3691twf.doc / 008 A7 B7 V. Description of the invention (i ) Although the present invention has been disclosed as above with a preferred embodiment, It is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouching without departing from the spirit of the present invention and beer. Therefore, the protection scope of the present invention should be regarded as the scope of the attached patent. The definition shall prevail. (Please read the notes on the back before filling this page)

, 1T Printed by the Ministry of Education, Tianjin, Tianjin, Tianjin and Bei-τ Consumer Cooperatives. The paper size is suitable for the national standard apple (('NS) Λ4 size (210X 297 cm))

Claims (1)

/ () Article ufl 1. Doc / 0 0 2 -sYuGko Patent Range Amendment A8 B8 C8 D8 ^ TF Η Rfl / i π / if; 1 曹明 # Is there any change to the original fisrii; Revealed: 涔 is 4 to repair JE-e Intellectual Property Bureau of the Ministry of Economic Affairs employee consumer cooperatives 6. Application for patent scope 1. An embedded memory power supply design method, installed in an embedded memory, where the embedded The memory includes a dynamic random access memory, a logic unit, and a test mode circuit and an input / output port. The embedded memory power design method includes: at a chip stage, the dynamic random access memory is separately , The logic unit, and the test mode circuit and the input / output port, design a first group of power supplies, a second group of power supplies, and a third group of power supplies, and the first group of power supplies, the second group of power supplies, and the third group of power supplies The groups of power supplies are independent; and in a packaging stage, the first group of power supplies, the second group of power supplies, and the third group of power supplies are connected together. 2. The embedded memory power supply design method described in item 1 of the scope of patent application, wherein the first group of power supplies, the second group of power supplies, and the third group of power supplies are respectively composed of a low power supply and a high power supply. . 3. The method for designing the power supply of the embedded memory according to item 1 of the scope of patent application, wherein at the chip stage, when the dynamic random access memory is tested, as long as the first group of power supplies and the third group are connected The power is sufficient. 4. The embedded memory power supply design method described in item 1 of the scope of the patent application, wherein at the chip stage, the logic unit only needs to be connected to the second group of power supplies and the third group of power supplies for testing. 5. The embedded memory power supply design method described in item 1 of the scope of patent application, wherein at the chip stage, when testing the entire embedded memory, the first group of power supplies, the second Group power and this third group of power. 6. The embedded memory power supply device IIIIII1 as described in item 1 of the scope of patent application — — — — — — · I (Please read the precautions on the back before filling this page) 丨 tr '·· -line · // This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) / () Article ufl 1. Doc / 0 0 2 Amendment of Patent Scope -sYuGko A8 B8 C8 D8 ^ TF Η Rfl / i π / if ； 贞 1 曹明 # Whether the original version has changed fisrii; Totsuki β said: 涔 是 4 予 修 JE-e Intellectual Property Bureau of the Ministry of Economic Affairs Employees Consumer Cooperatives printed 6. Application for patent scope 1. An embedded A memory power design method is installed in an embedded memory. The embedded memory includes a dynamic random access memory, a logic unit, and a test mode circuit and an input / output port. The embedded memory power The design method includes: designing a first group of power supplies, a second group of power supplies, and a third group of the dynamic random access memory, the logic unit, and the test mode circuit and the input / output ports during a chip stage. Group power, and this The first group of power supplies, the second group of power supplies, and the third group of power supplies are independent; and during a packaging stage, the first group of power supplies, the second group of power supplies, and the third group of power supplies are connected together. 2. The embedded memory power supply design method described in item 1 of the scope of patent application, wherein the first group of power supplies, the second group of power supplies, and the third group of power supplies are respectively composed of a low power supply and a high power supply. . 3. The method for designing the power supply of the embedded memory according to item 1 of the scope of patent application, wherein at the chip stage, when the dynamic random access memory is tested, as long as the first group of power supplies and the third group are connected The power is sufficient. 4. The embedded memory power supply design method described in item 1 of the scope of the patent application, wherein at the chip stage, the logic unit only needs to be connected to the second group of power supplies and the third group of power supplies for testing. 5. The embedded memory power supply design method described in item 1 of the scope of patent application, wherein at the chip stage, when testing the entire embedded memory, the first group of power supplies, the second Group power and this third group of power. 6. The embedded memory power supply device IIIIII1 as described in item 1 of the scope of patent application — — — — — — · I (Please read the precautions on the back before filling this page) 丨 tr '·· -line · // This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) A8 B8 C8 D8 3691twfl.doc / 002, and the method of applying for the scope of specialty, in which during the packaging stage, the first group of power supplies, the The second group of power supplies and the third group of power supplies are connected together externally using a package connection. 7. An embedded memory, comprising: a dynamic random access memory with a first group of power supplies; a logic unit with a second group of power supplies; and a test mode circuit and input / output terminals with a first Three sets of power supplies; where the chip is designed to separate the first set of power supplies, the second set of power supplies, and the third set of power supplies separately, and when packaged, the first set of power supplies, the second set of power supplies, and The third group of power supplies are connected together. 8. The embedded memory according to item 7 of the scope of patent application, wherein the first group of power supplies, the second group of power supplies, and the third group of power supplies are respectively composed of a low power supply and a high power supply. 9. The embedded memory according to item 8 of the patent application scope, wherein the low power source is a grounded power source. 10. The embedded memory according to item 7 of the scope of patent application, wherein when the dynamic random access memory is tested at the time of the chip, only the first group of power supplies and the third group of power supplies need to be connected. 11. The embedded memory according to item 7 of the scope of patent application, wherein when the logic unit is tested during the chip, only the second group of power supplies and the third group of power supplies need to be connected. 12. The embedded memory according to item 7 of the scope of patent application, wherein when testing the entire embedded memory at the time of the chip, the first group of power supplies, the second group of power supplies, and the The third group of power supplies. 9 -------------- Order --- IIIII (Please read the notes on the back before filling in this page) Employees' cooperation of Intellectual Property Bureau of the Ministry of Economic Affairs Du printed This paper is applicable to China Standard (CNS) A4 specification (210 X 297 mm) A8 B8 C8 D8 3691twfl.doc / 002, apply for a specialist range metering method, where the first group of power supplies, the second group of power supplies, and The third group of power supplies are connected together and are externally connected using a package connection method. 7. An embedded memory including: a dynamic random access memory having a first group of power supplies; a logic unit having a first Two sets of power supplies; and a test mode circuit and output input and output, with a third set of power supplies; where the chip is designed to separate the first set of power supplies, the second set of power supplies, and the third set of power supplies separately, in a package When designing, connect the first group of power supplies, the second group of power supplies, and the third group of power supplies together. 8. The embedded memory according to item 7 of the scope of patent application, wherein the first group of power supplies, This second set of power supplies starts with The third group of power supplies is composed of a low power supply and a high power supply. 9. The embedded memory as described in item 8 of the patent application scope, wherein the low power supply is a grounded power supply. The embedded memory according to item 7, wherein when the dynamic random access memory is tested at the time of the chip, only the first group of power supplies and the third group of power supplies need to be connected. The embedded memory according to item 7, in which the logic unit is tested when the chip is connected, as long as the second group of power supplies and the third group of power supplies are connected. The embedded memory mentioned above, in the chip, when testing the entire embedded memory, you need to connect the first group of power, the second group of power and the third group of power. 9 ---- ---------- Order --- IIIII (Please read the precautions on the back before filling out this page) The consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs Du printed this paper. The paper standard is applicable to China National Standard (CNS) A4 Specifications (210 X 297 mm)