TWI387922B - System of burning chips - Google Patents

Description

Wafer programming system

The present invention relates to a burning system, and more particularly to a burning system for burning a wafer mounted on a motherboard.

In the computer system architecture, a plurality of different functions of the chip are usually mounted on the motherboard to realize the smooth operation of the computer system, such as a basic input/output system chip, a network card chip, and the like. Generally, in the manufacturing process of the motherboard, the BIOS (Basic Input Output System) program and the MAC (Media Access Control) address are respectively burned into the corresponding chips on the motherboard. Generally, the wafer is first burned, and then the wafer is mounted on a motherboard, such as a programmable wafer burner, which includes a programming unit on which the programmable wafer is mounted. However, the burner can only burn unprinted wafers, and the burning module for burning is costly, and the situation of human leakage is often occurred, thus increasing the testing cost.

In addition, the conventional burning system generally transmits the burning data in the burning machine to the corresponding wafer by means of serial transmission. In this way, the data transmission speed is fast, and the data transmission flow is small, and the data can only be one bit. The bit is transferred to the chip to be burned, and the burning mode affects the working efficiency of the burning line. The traditional burning system also transmits the burning data in the burning machine to the corresponding wafer by means of parallel transmission. Although the data transmission method has a large amount of data transmission process, the wafer to be burned can receive multiple bits at the same time. The data, however, that the method of directly feeding the parallel data to the wafer to be burned reduces the accuracy of the burning.

In view of the above, it is necessary to provide a burning system for burning wafers mounted on a motherboard at a relatively fast speed.

A wafer burning system for burning a wafer to be burned mounted on a motherboard, comprising a burner having a burn-in data and a control wafer, the printer being borrowed from the control wafer Connected by the parallel interface, the programming system further includes a programmable logic device having a parallel serial data conversion function and a tandem parallel data conversion function, the programmable logic device being connected to the control chip by a parallel interface, and by The serial interface is connected to the wafer to be burned.

The programming system utilizes the parallel serial data conversion function of a programmable logic device and the tandem parallel data conversion function to achieve the purpose of quickly burning the chip mounted on the motherboard. In the process of burning, the parallel data is converted into serial data or converted into parallel data as needed. Due to the large amount of data flow in the parallel transmission mode, the serial transmission mode is faster and the bit error rate is low. This makes the burning system faster and more stable.

Referring to the first embodiment, in a preferred embodiment of the present invention, a wafer burning system is used for programming a first wafer 40 and a second wafer 50 to be mounted on a motherboard, and includes a burning machine 10, A control chip 20 and a CPLD (Complex Programmable Logic Device) 30 are provided.

The burning machine 10 stores the burning data corresponding to the first wafer 40 and the second wafer 50, and the burning machine 10 is connected to the control crystal by a bidirectional parallel interface. The pieces 20 are connected.

The control chip 20 has a parallel data output interface 22 and a parallel data input interface 24 connected to the complex programmable logic device 30. The control chip 20 further has an output data transmission control signal LOWC (active low) to the complex a control line of the programming logic device 30, an output read/write control signal R/W (high level corresponding write data, low level corresponding read data) to the control line of the complex programmable logic device 30, an output chip The signal CS1 (active high) is selected to the control line of the complex programmable logic device 30 and an output chip select signal CS0 (active high) to the control line of the complex programmable logic device 30.

The complex programmable logic device 30 includes a parallel data input interface 32 and a parallel data output interface 34. The parallel data input interface 32 is connected to the parallel data output interface 22 of the control chip 20. The parallel data output interface 34 and the control The parallel data input interface 24 of the wafer 20 is connected. The complex programmable logic device 30 includes two sets of pins respectively connected to the first to-be-recorded wafer 40 and the second to-be-recorded wafer 50. The first set of pins includes an output clock signal pin BSCK, one. The data of the output serial data is written into the pin BSI (serial data write interface), the pin BCE of the output chip select signal, and the data read pin BSO (which receives the feedback data of the first chip 40). The serial data read interface, the first set of pins is connected to the first chip 40; the second set of pins includes an output clock signal pin NSCK, and an output serial data burn data is written. a pin NSI (serial data writing interface), an output chip select signal pin NCE, and a data readout pin NDO (serial data readout interface) for receiving feedback data of the second chip 50, the second The group pins are connected to the second wafer 50.

Referring to the second figure, the data transmission process of the burning system of the present invention is: the burning machine 10 outputs the burning data corresponding to the first wafer 40 or the second wafer 50 to the control wafer 20 through the parallel interface; After receiving the burned data, the control chip 20 outputs the burned data to the complex programmable logic device 30 in parallel; the complex programmable logic device 30 performs parallel serial data conversion on the burned data and outputs the burned data in series. To the first wafer 40 or the second wafer 50.

Referring to the third figure, the data receiving process of the burning system of the present invention is: after the first wafer 40 or the second wafer 50 receives the burning data, the feedback data is serially transmitted back to the complex programmable logic device 30; The complex programmable logic device 30 performs parallel serial-to-parallel conversion on the received feedback data, and then transmits the data to the control chip 20 in parallel; the control chip 20 outputs the received feedback data to the burning machine 10 in parallel. Compare the original burning data and feedback data to determine whether the burning is successful.

Please refer to the fourth figure. The fourth figure is a schematic diagram of the complex programmable logic device 30. The complex programmable logic device 30 includes a parallel/serial data conversion module 301, a serial/parallel data conversion module 302, and a plurality of A buffer register 303 (303a, 303b, 303c, 303d, 303e, 303f, 303g, 303h, 303i, 303j, 303k) for speeding up data transmission, each of the buffer registers has an input end and a control end And an output terminal), two inverters 304 (304a, 304b), a crystal oscillator 305 and a frequency divider 306 connected to the crystal oscillator 35.

The input end of the parallel/serial data conversion module 301 is a parallel interface connected to the parallel data input interface 32, and the output end is a serial interface connected to the input end of the buffer register 303b, which can receive the serial interface. The parallel data is converted into serial data and output to the first wafer 40 or the second wafer 50 by the buffer register 303.

The input end of the serial/parallel conversion module 302 is a serial interface connected to the output end of the buffer register 303c, and the output end is a parallel interface connected to the parallel data output interface 34, which can receive the string The column data is converted into parallel data for output to the control wafer 20.

The buffer register 303a has an input terminal for introducing the read/write control signal R/W, a control terminal for introducing the data transmission control signal LOWC, and an input terminal of the inverter 304a and the buffer register. The output of the control terminal connected to 303b.

The buffer register 303b has an input terminal connected to the output end of the parallel/serial conversion module 301, a control terminal connected to the output end of the buffer register 303a, and a buffer register 303e. And an output connected to the input end of the buffer register 303i.

The buffer register 303c has an input terminal connected to the buffer register 303g and the output terminal of the buffer register 303k, a control terminal connected to the output end of the inverter 304a, and a string/ And the output end of the conversion module 302 is connected to the output end.

The buffer register 303d includes an input terminal connected to the frequency divider 306, a control terminal connected to the output terminal of the inverter 304b, and an output terminal BSCK for outputting a clock signal.

The buffer register 303e includes an input terminal connected to the output end of the buffer register 303b, a control terminal connected to the output end of the inverter 304b, and an output programming data to the first wafer 40. Output BSI.

The buffer register 303f includes an input terminal for introducing the chip select signal CS1, a control terminal connected to the output terminal of the inverter 304b, and an output terminal BCE for outputting a chip select signal.

The buffer register 303g includes an input end for receiving the output data of the first chip 40, a control end connected to the output end of the inverter 304b, and a connection end connected to the buffer register 303c. Output.

The buffer register 303h includes an input terminal connected to the frequency divider 306, a control terminal for introducing a CS0 signal, and an output terminal NSCK for outputting a clock signal.

The buffer register 303i includes an input terminal connected to the output terminal of the buffer register 303b, a control terminal for introducing a CS0 signal, and an output terminal NSI for outputting the burned data to the second wafer 50.

The buffer register 303j includes an input terminal for introducing the chip select signal CS1, a control terminal for introducing a CS0 signal, and an output terminal NCE for outputting a chip select signal.

The buffer register 303k includes an input for receiving feedback data of the second chip 50, a control terminal for introducing a CS0 signal, and an output terminal connected to the input terminal of the buffer register 303c.

The input end of the inverter 304a is connected to the output end of the buffer register 303a, and the output end is connected to the control end of the buffer register 303c.

The input end of the inverter 304b introduces a CS0 signal, and the output terminal is simultaneously connected to the control terminals of the buffer register 303d, the buffer register 303e, the buffer register 303f, and the buffer register 303g.

The crystal oscillator 305 is used to generate a clock signal SCK, and the frequency divider 306 is used to divide the clock signal SCK to obtain an appropriate frequency for system operation.

The parallel/serial conversion module 301, the buffer register 303b, and the buffer register 303e are serially connected to form a burn data transmission channel of the first programming chip 40, the buffer register 303g, the buffer register 303c, and The serial/parallel conversion module 302 is connected in series to form a feedback data receiving channel of the first programming wafer 40. The parallel/serial conversion module 301, the buffer register 303b, and the buffer register 303i are serially connected to form a burn data transmission channel of the second programming chip 40, the buffer register 303k, the buffer register 303c, and The serial/parallel conversion module 302 is connected in series to form a feedback data transmission channel of the second programming wafer 40.

When the data transmission control signal LOWC signal is low, the read/write control signal R/W introduced by the buffer register 303a may be output to the buffer register 303b or outputted to the buffer by the inverter. The 303c, at this time, the data transmission channel or the data receiving channel is turned on (equivalent to allowing data writing or allowing data reading); when the data transmission control signal LOWC is high, the buffer register 303a is introduced to read/ The write control signal R/W stops outputting, and the programming data transmission channel and the feedback data receiving channel are both disconnected (equivalent to prohibiting both writing data and reading data instructions).

When the data transmission control signal LOWC is low level and the R/W signal is high level, the buffer register 303a outputs a high level to the buffer register. 303b, outputting a low level to the buffer register 303c (corresponding to allowing write/disable read data instructions), at this time, the buffer register 303b can output the burned data to the buffer register 303e or the The buffer register 303i stops transmitting the feedback data. When the data transmission control signal LOWC is low level and the R/W signal is low level, the buffer register 303a outputs a high level to the buffer register 303c, and outputs a low level to the buffer register 303b. (corresponding to the permission to read/disable the write data command), at this time, the buffer register 303c can output the feedback data transmitted by the buffer register 303g or the buffer register 303k to the serial/parallel data conversion. The module 302, the buffer register 303b stops transmitting the burned material.

When the CS1 signal is high, the first to-be-recorded wafer 40 and the second to-be-recorded wafer 50 are selected.

When the CS0 signal is low, the control end of the first group of buffer registers is connected to the low level by the inverter, that is, the first group of buffer registers is connected to the high level, and the first buffer is temporarily stored. The device can normally output the signal sent from the input terminal; the control terminals of the second group of buffer registers are directly connected to the low level, and the second group of buffer registers stop outputting the data. When the CS0 signal is high, the control terminal of the first group of buffer registers is connected to the high level by the inverter, that is, the first group of buffer registers is connected to the low level, and the first group of buffers is temporarily suspended. The memory stops outputting the signal; the control terminals of the second group of buffer registers are directly connected to the high level, and the second group of buffer registers can normally output the signal sent by the input terminal.

It can be seen from the above that when the programming system transmits or receives data, the data transmission control signal LOWC signal is at a low level, and the CS1 signal is at a high level. The first wafer 40 is lifted before the above data transmission and reception conditions are satisfied. The corresponding programming data transmission condition is: the R/W signal is high level, the CS0 signal is low level; the feedback data receiving condition of the first chip 40 is: the R/W signal is low level, CS0 The signal is low. Before the above data transmission and reception conditions are satisfied, the second wafer 50 corresponds to the programming data transmission condition: the R/W signal is at a high level, and the CS0 signal is at a high level; the second wafer 50 The feedback data receiving condition is: the R/W signal is low level, and the CS0 signal is high level.

The effective level of the control signal can also be flexibly set to the opposite level. At this time, the working principle of the programming system is unchanged, and only the control conditions are changed.

The complex programmable logic device 30 can be designed using a Verilog HDL (Verilog Hardware Description Language) input method, and the EDA (Electronic Design Automatic) tool is used to convert the language description circuit into a practical one. The circuit can be used, and the development cost is low and convenient. In addition, since the serial/parallel data conversion module 301 and the parallel/serial data conversion module 302 are simultaneously integrated in the complex programmable logic device 30, the resource utilization ratio of the complex programmable logic device 30 is higher, and further Reduced costs. The complex programmable logic device 30 can be other types of programmable logic device PLD, such as a field programmable gate array FPGA, a field programmable interconnect circuit FPIC, and the like.

In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art of the present invention should be included in the following claims.

10‧‧‧ burning machine

20‧‧‧Control wafer

30‧‧‧CPLD

40‧‧‧First chip

50‧‧‧second chip

22,34‧‧‧Parallel data output interface

24,32‧‧‧Parallel data input interface

301‧‧‧/string data conversion module

302‧‧‧Serial/parallel data conversion module

303‧‧‧Buffer register

304‧‧‧ reverser

230‧‧‧ crystal oscillator

306‧‧‧divider

The first figure is a schematic diagram of the composition of a wafer burning system according to a preferred embodiment of the present invention.

The second figure is a flow chart for transmitting the burned data of the wafer burning system according to the preferred embodiment of the present invention.

The third figure is a flow chart of receiving feedback data of the wafer burning system according to the preferred embodiment of the present invention.

The fourth figure is a schematic diagram of the complex programmable logic device in the first figure.

10‧‧‧ burning machine

20‧‧‧Control wafer

30‧‧‧CPLD

40‧‧‧First chip

50‧‧‧second chip

22,34‧‧‧Parallel data output interface

24,32‧‧‧Parallel data input interface

Claims (9)

A wafer burning system for burning a wafer to be burned mounted on a motherboard, comprising a burner having a burn-in data and a control wafer, wherein between the burner and the control wafer The programming system further includes a programmable logic device having a serial parallel data conversion function and a parallel serial data conversion function, the programmable logic device being connected to the control chip by a parallel interface, and borrowing Connected to the chip to be burned by a serial interface, the control chip has a control line for outputting a read/write control signal to the programmable logic device and a control chip for outputting a chip select signal to the programmable logic device. The wafer burning system of claim 1, wherein the to-be-burned wafer comprises a first wafer and a second wafer, the programmable logic device having a first set of pins connected to the first wafer And a second set of pins connected to the second chip, the first set of pins and the second set of pins each comprise a clock signal output pin, a data write pin, a data read pin and a piece Select pin. The wafer programming system of claim 2, wherein the programmable logic device comprises a data transmission channel, the input end of the data transmission channel is connected to the control chip by a parallel interface, and the output terminal and the first The wafer and the second wafer are respectively connected by a serial interface. The wafer burning system of claim 3, wherein the data transmission channel comprises a parallel data input interface and a serial data output interface, and a serial data conversion module and a first buffer register. And a second buffer register, the parallel data input interface is connected to the control chip, and the serial data output interface is simultaneously connected to the first buffer register and the second buffer The input end of the register is connected, the output end of the first buffer register is connected to the first chip, and the output end of the second buffer register is connected to the second chip. The wafer programming system of claim 4, wherein the first buffer register has a control terminal for introducing the chip select signal by an inverter, and the second buffer register has a chip select The control end of the signal. The chip burning system of claim 3, wherein the programmable logic device further comprises a data receiving channel in an on/off state opposite to the data transmission channel, the input end of the data receiving channel and the first A chip and the second chip are respectively connected by a serial interface, and the output end is connected to the control chip by a parallel interface. The chip burning system of claim 6, wherein the data receiving channel comprises a serial/parallel data conversion module having a serial data input interface and a parallel data output interface, and a third buffer register and a fourth buffer register, the parallel data output interface of the serial/parallel data conversion module is connected to the parallel interface of the control chip, and the serial data input interface of the serial/parallel conversion module is simultaneously connected with the third buffer The register is connected to the output of the fourth buffer register, the input end of the third buffer register is connected to the first chip, and the input end of the fourth buffer register is connected to the second chip. The wafer programming system of claim 7, wherein the third buffer register has a control terminal for introducing the chip select signal by an inverter, the fourth buffer register having a chip select The control end of the signal. The wafer burning system of claim 2, further comprising a crystal oscillator and a frequency divider, the frequency divider having one end connected to the crystal oscillator and the other end connected to the first wafer and the second wafer.