TW548654B - Read only memory sensing circuit and the sensing method - Google Patents

Abstract

The present invention provides a new read only memory (ROM) sensing circuit and the sensing method, which can be operated at a high-speed and satisfy a low power consumption requirement. For the sensing method, when the data stored in the memory is in a logic high level, the process that pulls up the output terminal OUT to the first voltage level is divided into two stages. In the first stage, the output terminal OUT is pulled up to a voltage level obtained by subtracting Vt from the first voltage (where Vt is the threshold voltage of transistor). In the second stage, the output terminal OUT is pulled up from a voltage level obtained by subtracting Vt from the first voltage to the voltage level of the first voltage. Additionally, in order to effectively shorten the required time of the first stage, a dual path structure composed of the first and the second current supply path is designed in the first stage, in which the first current supply path provides the supply earlier than the second current supply path. While in the second stage, only the second current supply path is reserved.

Description

548654

[Field of the Invention] I ^ The sun and the moon are related to a kind of self-confidence, especially a combination of ancient, * π 1 L, body sensing circuit and sensing method, body sensing circuit and sensing method. Xiao Consumption and Power-Effective Read-Only Memory [Background of the Invention] In Use: The speed and integration of the device-a steady increase in the number of devices, which must be steadily increased; the pen: the increased use of type computers, semiconductor memory devices-internal Electrical traceability: 臛: f rate / Xiao consumption. Generally, the 'conductor memory chip includes a thunder source :: a mouth coffee, a supply voltage generator receiving-from the chip "outside the ministry ^ f MIVC1 \ E1CT ^ 1 ^ ® ^ ^ ^ t #. ^ VC, the internal power supply voltage IVC is used for the main circuit of semiconductor memory devices to reduce power consumption. Read-only memory (ROM) is a nonvolatile semiconductor memory /, which is suitable for applications that require high density And high-fixed-memory systems. Because the characteristics of read-only memory are readable but not writable, the characteristics of the stored data are permanent and will not be erased. Therefore, general household appliances, recreational instruments, Or microprocessor controllers, which often use read-only memory to store data. The data stored in read-only memory is read by a sense amplifier circuit (sense amp 1 ifi er), which will The weak current in the read-only memory is amplified and output. The conventional sense amplifier circuit is shown in the first figure, and the sense amplifier circuit includes an N M 0 S transistor M N1, ~ PM qs transistor.

548654 V. Description of the invention (2) The body MP1, a reverse OR gate NOR and a first and second inverters NOT1 and N0T2 'wherein the source terminal of the PM0S transistor MP1 and the reverse OR gate nor, the The power supply terminals of the first and second inverters NOT0 and Y1 are both connected to the external power supply voltage £ ¥ (:. The potential of Lu Jiyi's body is floating (f 1 oat i ng) and low potential (vss) In two states, when the memory potential is low (VSS), the OR gate NOR will output a high level of the external power supply voltage EVC to the transistor MΓΠ and turn it on (ON). This memory The low potential of the body is transmitted to the node A ′ through the transistor MN1 and amplified by the first and second inverters NOT1 and rib 2 to output vss ′, and the sensing of the low potential state is completed. When the memory When the potential is floating (f 1 〇ati ng), the transistor MN1 is turned off (0FF). At this time, the transistor MP1 constitutes a pull-high electrical external power supply voltage EVC, which will make the transistor MPl on (0N). And pull the potential of the node to the external power supply voltage EVC, and then pass the first and second inverters N0T1 and N0T2 is amplified to output EVC, which completes the sensing of floating state energy. ~ The conventional sensing amplifier circuit shown in the first figure is an external power supply voltage with a voltage level higher than the internal F power supply voltage IV C EVC as a supply voltage, although it achieves the effect of high-speed operation, but it increases the power consumption, which is not conducive to the use of notebook computers. Li. ~ A conventional sense amplifier circuit is shown in the second figure, in addition to ==, except for the source supply voltage IVC as the supply voltage, the constituent components are the same as the conventional sense amplifier circuit not shown in the figure, so the description of the work is omitted. / Λ · / · ^ ^ But the custom shown in the second figure Although the sense amplifier circuit can be reduced

548654 V. Description of the invention (3) The effect of power consumption, but it is difficult to operate at high speed. Other known sense amplifier circuits are, for example, US Patent Nos. US465 1 3 02, US4 75 8748, US482 1 239, and US5543 738 and ROC Application Nos. 84121371, 84207807, and 8 9 2 0 2 5 8 As disclosed in Patent No. 3, when it is applied to the internal power supply voltage IVC as the supply voltage, it has a problem of difficulty in high-speed operation. In view of this, the main purpose of the present invention is to propose a novel read-only memory sensing circuit and sensing method, which can not only pursue high-speed operation of the memory, but also meet the demand for low power consumption.

[Invention Brief]

According to the above purpose, the present invention proposes a novel read-only memory sensing circuit and sensing method. The sensing circuit includes: an invertor OR gate NOR 'which is used to receive the internal node B signal and the chip. Enable signal (CE) 'and its power supply terminal is connected to the first voltage; a first PM0S transistor is good 1, its source is connected to the first voltage, the drain is connected to the internal node A, and the gate is connected to Ground voltage;-the first NMOS transistor MN1, whose source is connected to internal node B, the drain is connected to internal node A, and the gate is connected to the output of the FF OR gate N0R; an inverter NOT, which The input terminal is connected to the internal = two points A, and the output terminal is connected to the internal node (:, and the power supply terminal is connected to the voltage of the mountain; a second NM0S transistor MN2, the source of which is connected to the output to the A0 OUT, drain The pole is connected to the second voltage, and the gate is connected to the internal section: ~ the third NM0S transistor MN3, the source is connected to the ground voltage, the drain is connected to the output terminal ουτ, and the gate is connected to the internal node c; as well as

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-The source of the second PMOS transistor MP2 is connected to the first voltage to the output terminal out, and the gate is connected to the internal node c. The level of the second voltage is higher than the level of the first voltage, the drain Even among them, at this time, the voltage at the stage will output a voltage between the two paths to the path to the path. The data stored in the memory by the sensing method is pulled to the first voltage at the logic high potential output terminal OUT. The level process is divided into two. The first stage is to pull the output terminal OUT to the first voltage deduction vt level (where V t represents the threshold voltage of the transistor), and the second stage is that the terminal OUT is deducted by the first voltage. The reduced voltage level is then pulled up to the first and the second voltage levels. Among them, in order to shorten the first stage, first and second current supply path structures are designed in the first stage, and the first A current supply path is provided earlier than the second current supply; and in the second stage, only the second current is reserved for the purpose of [invention embodiment] The read-only memory sensing circuit proposed by the present invention is shown in the first Three figures, including: OR gate N0R, which is used to accept the number of the internal node 6 and the chip enable signal (CE); the _PM0S transistor MP1, whose source electrode is connected to the internal power supply voltage 1 vc, and the drain electrode is connected to the internal node A, and the gate is connected to the ground voltage; the first-NMOS transistor MΓΠ, whose source is connected to the internal node B, the drain is connected to the internal node A, and the gate is connected to the output of the anti-OR gate NOR; The inverter N0T has its input terminal connected to internal node t, its output terminal connected to internal node C, and its power supply terminal connected to the internal power supply voltage IVC;-the second NM0S transistor MN2, whose source is connected to the wheel ^

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Terminal OUT, the drain is connected to the external power supply voltage Evc, cap [point A;-the third NM0S transistor, its source, the drain is connected to the output terminal 〇υτ, and the gate is connected to the internal point, C And—the second PM0S transistor MP2, whose source is connected to the internal power supply voltage ivc, the drain is connected to the output terminal ουτ, and the gate is connected to the internal dump point C 〇σ "here 'when the memory potential is low When the potential (vss), the OR gate N0R will output a high potential of the internal power supply voltage IVC to the _NM0S transistor MN1 and turn it on (ON). The low potential of this memory is via the _NM0S voltage. The crystal MN1 is transmitted to the internal node a. This low potential internal node A on the one hand makes the second NMOS transistor MN2 in an OFF state, and on the other hand, L outputs a high potential to the internal node after being inverted by the inverter NOT. This high-potential internal node C then turns off the second PM0S transistor MP2 (OF!? / State, and makes the third NMOS transistor MN3 in a conducting (ON) state, so the output terminal ουτ can be effectively pulled down to Low-potential state to complete the sensing of the low-potential state. When the potential is floating (f 1 oat i ng), the first NM0S transistor MN1 is turned off (0FF). At this time, the first PM0S transistor MP1 forms a pul 1-high circuit. The internal power supply voltage IVC will The first PM0S transistor MP1 is turned on (0N), and the potential of the internal node A is pulled up to the internal power supply voltage IVC. This high potential of the internal node A makes the second NMOS transistor MN2 in a conductive (0N) state. Therefore, the output terminal OUT can be quickly pulled up to the voltage level of IVC-Vt (where Vt represents the threshold voltage of the second pass transistor MN2), and on the other hand, the output is low after being inverted by the inverter NOT. Potential to I! I 1 1 η 1 I 1 II 11 Page 8 548654 V. Description of the invention

Internal node C, this low-potential internal node C then causes the second pM0s transistor M P 2 to be in an on state (ON) and the third N M 0 S transistor M N 3 to be in an OFF state. Therefore, the output terminal OUT can be effectively pulled up to the level of the internal power supply voltage I VC to complete the sensing of the floating state. μ Because the process of pulling out the output terminal out to the level of the internal power supply voltage Ivc is divided into two stages, the first stage is to pull the output terminal 0υτ to the voltage level of IVC-Vt (where Vt represents the third voltage). Show a picture of the guide two NMOS or have a mention. The first to the internal closed state first picture path. Threshold of transistor MN2

At this time, the second NM0S transistor MN2 and the second pM0s transistor Mp2 are in the ON state, so they have a dual current supply path, and because the second transistor MN2 is directly driven by the internal node a, compared to the first The prior art of the second figure, the effect of the second turn-on transistor of the present invention, the early turn-on effect of the transistor 2 can effectively shorten the time required for the first stage. The second stage is to set the output terminal ουτ from the voltage level of vc_vt. At the standard level, today Tiantian Chuyi M can, but JM0S electric power said: the second MP2 is still in a conducting state, so it is the same as the first technique in the first picture, 'only has a single current Supply the watch and the above-mentioned 'the read-only memory of the present invention with a dipole m added to the second pole to connect to an external power supply voltage = = it can quickly and effectively pull the output terminal OUT to the vc position; at the same time Because the standard of the output terminal OUT t is equal to the standard of the internal power supply voltage ivc, the voltage swing (V0 Uage swing) position, therefore, the only position of the present invention is the standard voltage A of the power supply voltage EVC fe body sensing circuit can not only track

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V. Description of the invention (7) The high-speed operation of the memory is required, and it can also meet the requirements of low power consumption. Here, in order to pursue higher-speed operation of the memory, the second NMOS transistor MN2 can be designed to have a large channel width-to-length ratio W / L to increase its current driving capability, and the second PMOS transistor MP2 is designed to Has a small channel width to length ratio W / L to save chip area. [Effect of the invention] Since the read-only memory sensing circuit of the present invention is further provided with an NMOS transistor MN2 having a large channel width-length ratio W / L, and the source of the NMOS transistor MN2 is connected to the output terminal OUT, The pole is connected to the external power supply voltage evc, and the gate is connected to the internal node A before the inverter NOT. Therefore, when the output terminal OUT is charged from a low potential to a high potential, its operation can be completed early and quickly. Therefore, the present invention With high-speed operation. At the same time, because the voltage swing of the output terminal OUT is equal to the internal power supply voltage IVC level rather than the external power supply voltage Evc level, the present invention can also effectively reduce power consumption.

Those that are not disclosed by Zheng Qiyou are the demonstration of the preferred embodiment. For example, the partial changes or repairs are derived from the idea of the case of Wisdom + Wii, and the person who is familiar with the skill The corpse juice is easy to deduce, / 目 · ^ ⑽ 丄 + has the scope of exclusivity of this case. To sum up, this case was not done in Zhong Rizhang Kaiweigan # M t M H… means or effect, in the sign i ㈣ requirements, pray for an early grant of a patent, to benefit the society, real sense

Page 10 548654 V. Description of the invention (8) llliiil 548654 Brief description of the diagram The first diagram is a circuit diagram showing a read-only memory sensing circuit with a conventional external power supply voltage; the second diagram shows an internal power source of the conventional instrument A circuit diagram of a read-only memory sensing circuit that supplies a voltage; the third diagram is a circuit diagram of a read-only memory sensing circuit according to an embodiment of the present invention. Chip enable signal External power supply voltage Internal power supply voltage PM0S transistor NM0S transistor

[Description of component symbols CE EVC IVC MP1, MP2 MN1, MN2, MN3 NOT, N0T1, N0T2 Inverter NOR OR gate OUT output terminal VSS ground

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Claims (1)

2 · 3. 4. 5. NjJi application ί! Scope 2 types of read-only memory sensing circuits, the read-only memory sensing circuit package-reverse OR? NOR, which is used to receive the signal of the internal node B and the chip enable signal (CE), and its power supply terminal is connected to the first voltage;-the -PM0S transistor MP1, the source of which is connected to the -th voltage, the pole It is connected to internal node A, and the middle pole is connected to the ground voltage. The first NM0S electrical system is connected to the body node 1. Its source is connected to the internal node ^, the drain is connected to the internal node A ', and the intermediate pole is connected to the reverse OR gate. Followed by an inverted phase NOT, its input terminal is connected to internal node A, the output terminal is connected to internal point C, and the power supply terminal is connected to the first voltage;-the second NMOS transistor MN2, whose source is connected To the output terminal ⑽,; and the pole is connected to the second voltage, and the gate is connected to the internal node A;-the third NM0S transistor MN3, the source is connected to the ground voltage, the drain is connected to the output terminal OUT, and The gate is connected to the internal node c; and-the first P MOS transistor M P 2 whose source is connected to the first voltage, the drain is connected to the output terminal OUT, and the gate is connected to the internal node c. In the read-only memory sensing circuit described in item 1 of the patent application scope, the level of the second voltage is higher than the level of the first voltage. In the read-only memory sensing circuit described in item 2 of the patent application scope, the first voltage is the internal power supply voltage IVC. In the read-only memory sensing circuit described in item 2 of the patent application scope, the second voltage is the external power supply voltage EVC. As described in item 2 of the patent application, the read-only memory sensing circuit is installed in the JL. Page 13 548 Short 1. In the scope of the patent application, the second voltage is the voltage after the first voltage is boosted. 6. The read-only memory sensing circuit described in item 1 of the scope of the patent application, in #, the second NMOS transistor MN2 is designed to have a large channel width-to-length ratio 'W / L to increase its current driving capability In addition, the second PMOS transistor MP2 is designed to have a small channel width-to-length ratio W / L to save chip area. 7 · A sensing method of read-only memory, the data stored in the read-only memory is read through a sensing circuit, the sensing circuit includes: an inverting OR gate NOR, which is used to receive internal nodes β signal and chip enable signal (CE), and its power supply terminal is connected to the first voltage;-the first PM0S transistor MP1, its source is connected to the first voltage, and its drain is connected to the internal point A 'and The gate is connected to the ground voltage;-the source of the first N M 0 S transistor M N1 is connected to the internal node β, the drain is connected to the internal node A, and the gate is connected to the reverse OR gate NOR Output; One Han and Christine Wi, whose input is connected to internal node A, the output is connected to internal node C, and the power supply terminal is connected to the first voltage; "the second NM0S transistor MN2 '丨 the source is connected to the output terminal · , And the gate is connected to the internal node A; the transistor MN3 has its source connected to the ground voltage, the drain connected to the output terminal OUT, and the intermediate electrode connected to the inside—the second PM0S Transistor MP2, its source is connected to the factory and connected to the output Child OUT, and ask pole J 2 brother,? And pole, and when the data stored in the memory is point C, the output terminal OUT is pulled up to the highest level of the first electric dust, the output is rich. The process is divided into two stages Page 14 6. In the 3rd paragraph of Shen Zhenzhuan, the first stage is to raise the output terminal OUT to the voltage level of the first voltage minus Vt (where Vt represents the threshold voltage of the second NM0S transistor MN2), the first In the stage, the output terminal 0 U τ is deducted from the voltage level of vt by the first voltage and then raised to the voltage level of the first voltage; where 'in order to shorten the time required for one stage, so in this first stage A dual circuit structure of the first and second current supply paths is designed therein, and the first current supply path is supplied earlier than the second current supply path; and in the second stage, only the second current supply path is retained. 8. The sensing method according to item 7 in the scope of patent application, wherein the first current supply path is provided by a second NMOS transistor MN2. 9. The sensing method according to item 7 in the scope of the patent application, wherein the second current supply path is provided by a second pMOS transistor MP2. I 0 · The sensing method as described in item 9 of the scope of patent application, wherein the second NMOS transistor MN2 is designed to have a large channel width-to-length ratio W / L to increase its current driving capability, and the second The PM0S transistor MP2 is designed with a small channel aspect ratio W / L to save chip area. II. The sensing method as described in item 7 of the scope of patent application, wherein the second The voltage level is higher than the voltage level. 1 2 · The sensing method according to item 11 in the scope of the patent application, wherein the first voltage is the internal power supply voltage IVC ° 1 3. The sensing method according to item 11 in the scope of the patent application, wherein the first voltage The second voltage is the external power supply voltage EVC ° 1 4. The sensing method described in item 11 of the scope of patent application, wherein the first Page 15 54 ^ 65425 The second voltage is the voltage after the first voltage is boosted. 11IH1 Page 16