TW543209B - Field-emission type electron source and method of manufacturing the same - Google Patents

Field-emission type electron source and method of manufacturing the same Download PDF

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TW543209B
TW543209B TW91108459A TW91108459A TW543209B TW 543209 B TW543209 B TW 543209B TW 91108459 A TW91108459 A TW 91108459A TW 91108459 A TW91108459 A TW 91108459A TW 543209 B TW543209 B TW 543209B
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Taiwan
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layer
electron source
electric field
semiconductor
film
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TW91108459A
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Chinese (zh)
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Takuya Komoda
Koichi Aizawa
Yoshiaki Honda
Tsutomu Ichihara
Yoshifumi Watabe
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Matsushita Electric Works Ltd
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Priority claimed from JP2001145526A external-priority patent/JP3478279B2/en
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Publication of TW543209B publication Critical patent/TW543209B/en

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Abstract

A field-emission type electron source (10) is provided with a strong field drift layer (6) and a surface electrode (7) composed of a thin gold film on an n-type silicon substrate (1). An ohmic electrode (2) is provided on the back surface of the n-type silicon substrate (1). A direct current voltage is applied between the surface electrode (7) and the ohmic electrode (2) such that the surface electrode (7) has a positive potential against the ohmic electrode (2). In consequence, electrons, which have been injected from the ohmic electrode (2) into the strong field drift layer (6) through the n-type silicon substrate (1), drift in the strong field drift layer (6), and then emitted outward through the surface electrode (7). The strong field drift layer (6) has many fine semiconductor crystals (63) of nano meter order formed in a portion of the semiconductor layer constituting the strong field drift layer (6), and many insulating films (64) formed on the surfaces of the fine semiconductor crystals (63). Each of the insulating films (64) has a thickness which can cause a tunneling phenomena of the electrons.

Description

543209 A7 B7 五、發明説明（1 ) 〔技術領域〕 (請先閲讀背面之注意事項再填寫本頁) 本發明是有關利用半導體材料，藉由電場放射來放射 電子線之電場放射型電子源及其製造方法，且於電場放射 型電子源的製造時’供以在半導體結晶的表面上形成絕緣 薄膜之方法及裝置。 〔背景技術〕 就習知的電場放射型電子源而言（以下稱爲「電子源 」），例如有揭不於美國專利3 6 6 5 2 4 1號公報的 Spindt型電極。Spindt型電極具備：配置多數個微小三角錐 狀的射極片的基板，及對具有使射極片的前端部露出的放 射孔之一方射極片而言爲絕緣的閘極層。又，Spindt型電極 會在真空中以射極片對閘極層而言能夠形成負極之方式來 施加高電壓，而使得以從射極片的前端經由放射孔來放射 電子線。 但，Spindt型電極的製程複雜，且難以高精度製作多數 經濟部智慧財產局員工消費合作社印製 個三角錐狀的射極片。因此，在予以應用於平面發光裝置 或顯示器等時，會有難以大面積化的問題發生。並且，在 Spindt型電極中，由於電場會集中於射極片的前端，因此當 射極片前端周圍的真空度低且有殘留氣體存在時，殘留氣 體會因所放射的電子而離子化成正離子。而且，因爲此正 離子會衝突於射極片的前端，所以射極片的前端會受損（ 因離子衝擊而損傷）。因此，所被放射之電子的電流密度 或放出效率等會形成不安定，射極片的壽命會變短。爲了 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -4 - 543209 A7 B7 五、發明説明（2 ) (請先閱讀背面之注意事項再填寫本頁) 防範於此，Spindt型電極必須在高真空（約1 〇 - 5 P a〜 約1 〇_6P a )下使用。其結果，成本會變高，處理上會 很麻煩。 爲了改善此問題，而提案：Μ I M(Metal Insulator Metal)型或Μ 〇 S (Metal Oxide Semiconductor)型的電子源。 前者爲具有金屬-絕緣膜-金屬的層疊構造之平面型的電 子源，後者爲具有金屬-氧化膜-半導體的層疊構造之平 面型的電子源。在此種的電子源中，爲了提高電子的放出 效率（亦即，使更多的電子放射），而必須弄薄絕緣膜或 氧化膜的膜厚。但，若絕緣膜或氧化膜的膜厚太薄，則當 電壓施加於層疊構造的上下電極間時，會有破壞絕緣之虞 。因爲必須防止如此的絕緣破壞，所以絕緣膜或氧化膜的 薄膜化會有其限度。因此，某程度上無法提高電子源的放 出效率（引出效率）。 經濟部智慧財產苟員工消費合作社印製 所以，近年來，如日本特開平8 - 2 5 0 7 6 6號公 報所揭示，提案一電子的放出效率高的電子源（半導體冷 電子放出效率），亦即在半導體基板與表面電極之間施加 電壓，而使電子能夠放出者。在此電子源中，是使矽基板 等的單結晶半導體基板的一表面陽極氧化，藉此來形成多 孔質半導體層（多孔矽層）。然後，在此多孔質半導體層 上形成由金屬薄膜（導電性薄膜）所構成的表面電極。 但，就揭示於日本特開平8 - 2 5 0 7 6 6號公報的 電子源而言，在電子放出時會容易發生跳動現象，且電子 的放出量會容易發生不均一。因此，若予以應用於平面發 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 543209 Α7 Β7 五、發明説明（3 ) 光裝置或顯示器等時會有發光不均一的問題發生。 爲了解決這樣的問題，本發明者在日本特願平1 〇 - (請先閱讀背面之注意事項存填寫本頁) 272340號公報及日本特願平10 — 272342號 公報等中提案：在導電性基板與金屬薄膜（表面電極）之 間設置一從導電性基板注入的電子會飄移的強電場飄移層 (以下簡稱爲「飄移層」）之電子源。此飄移層是由氧化 的多孔質多結晶矽層所構成。 例如，第3 8圖所示，就此種的電子源1 〇 /而言， 是在導電性基板之η型矽基板1的主表面側形成有··由氧 化的多孔質多結晶砂層（被多孔質化的多結晶砂層）所構 成的飄移層6。在飄移層6上形成有由金屬薄膜（例如， 金薄膜）所構成的表面電極7。並且，在η型矽基板1的 背面形成有歐姆電極2。以η型矽基板1及歐姆電極2來 構成下部電極1 2 (導電性基板）。在第3 8圖所示的電 子源例子中，雖是在下部電極1 2與飄移層6之間介設一 無摻雜質的多結晶矽層3，但亦可直接在下部電極1 2上 形成飄移層6。 經濟部智慧財產苟員工消費合作社印製 又，對向於表面電極7配設有：例如由透明導電膜（ I Τ ◦膜）所構成的集極電極2 1。在使電子從電子源 10 放出時，是在使表面電極7與集極電極21之間形 成真空狀態下，以表面電極7能夠對導電性層1 2形成高 電位之方式，在表面電極7與導電性層1 2之間施加直流 電壓V p s，及以集極電極2 1能夠對表面電極7形成高 電位之方式，在集極電極2 1與表面電極7之間施加直流 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） - 6 - 543209 hi ______ _B7_ 五、發明説明（4 ) (請先閱讀背面之注意事項再填寫本頁) 電壓V c。只要適當的設定各直流電壓νρ s ，Vc ，則 由導電性層1 2注入的電子便會飄移於飄移層6內，經由 表面電極7而釋放出（第3 8圖中的一點鎖線是表示通過 表面電極7而放出之電子e -的流向）。並且，表面電極7 的厚度是被設定於3〜1 5 n m的程度範圍。 飄移層6是在下部電極1 2上形成無摻雜質的多結晶 砂層後，以陽極氧化處理來使該多結晶矽層多孔質化，藉 此來形成多孔質多結晶矽層，且藉由急速熱氧化法，例如 以9 0 0 °C來急速熱氧化該多孔質多結晶矽層。 經濟部智慧財產局員工消費合作社印製 如第3 9圖所示，飄移層6是至少由：柱狀多結晶矽 的晶粒5 1，及薄絕緣膜5 2，及多數個奈米單位的微結 晶矽6 3，及多數的氧化矽膜6 4等所構成。其中，晶粒 5 1是列設於η型矽基板1的主表面側（亦即，下部電極 1 2的表面電極7側）。絕緣膜5 2是形成於晶粒5 1的 表面。微結晶矽6 3是介於晶粒5 1之間。絕緣膜6 4是 形成於各微結晶矽6 3的表面，具有比微結晶矽6 3的結 晶粒徑還要小的膜厚。總而言之，在飄移層6中，多結晶 砂層的各晶粒5 1的表面會形成多孔質化，在各晶粒5 1 的中心部份會維持結晶狀態。並且，各晶粒5 1是延伸於 下部電極12的厚度方向。而且，各絕緣膜52，64是 由氧化矽膜所構成。 在電子源1 0 ’中，可想像爲以下所述的模式來引起電 子放出。亦即，在電子放出時，在表面電極7與下部電極 1 2之間，施加表面電極7爲高電位的直流電壓V p s， 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） ~ ' 543209 經濟部智慧財產局員工消費合作社印製 A7 _B7 _五、發明説明（5 ) 以及在集極電極2 1與表面電極7之間，施加集極電極 2 1爲高電位的直流電壓V c。若直流電壓V p s達到預 定値（臨界値），則電子e _會藉由熱勵起來從下部電極 1 2注入飄移層6。另一方面，大部分施加於飄移層6的 電場會加諸於絕緣膜6 4。因此，所被注入的電子e —會藉 由加諸於絕緣膜6 4的強電場而被加速。然後，電子e —會 在飄移層6內使晶粒5 1間的領域朝向表面而飄移於第 3 9圖中箭頭A的方向，穿過表面電極7而放出於真空中 〇 如此一來，在飄移層6中，從下部電極1 2注入的電 子在微結晶矽6 3中幾乎不會散亂，在施加於絕緣膜6 4 的電場中會被加速而飄移。然後，經由表面電極7而放出 (彈道型電子放出現象）。此刻，在飄移層6產生的熱會 經由晶粒5 1而釋放出。因此，電子放出時不會有電子跳 動現象產生，可安定的釋放出電子。並且，到達飄移層6 表面的電子爲熱電子，容易穿過表面電極7而放出於真空 中。 就電子源1 0 >而言，雖是以η型矽基板1與歐姆電 極2來構成下部電極1 2，但如第4 0圖之電子源1 〇 〃 所示，亦可在絕緣性基板1 1 (例如由玻璃基板所構成） 的一表面上形成由金屬材料所構成的下部電極1 2。在第 4 0圖中，對與第3 8圖所示之電子源1 0 /共同的構成 要素賦予同一符號，並省略其說明。在第40圖所示之電 子源1 0 〃中，同樣可利用與第3 8圖所示之電子源 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Α4規格（210'乂 297公釐） -8- PR209 A7 B7 五、發明説明（6 ) 1 0 /相同的製程來使電子放出。 在電子源1 0 /， 1 0 〃中，通常是將流動於表面電 (請先閱讀背面之注意事項再填寫本頁) 極7與下部電極1 2之間的電流稱爲二極體電流I p S， 以及將流動於集極電極2 1與表面電極7之間的電流稱爲 放射電流（放出電子電流）I e。在此，放射電流I e對 二極體電流I p s的比率（I e/I p s )越大，電子放 出效率（（I e/I sp)x 100 〔％〕）越高。在電 子源1 0 /， 1 0 〃中，即使施加於表面電極7與下部電 極1 2之間的直流電壓V p s爲1 〇〜2 0 V程度的低電 壓，還是能夠使電子放出。並且，直流電壓V p s越大， 放射電流I e會形成越大。 在電子源1 0 >， 1 0 〃的製程中，形成飄移層6的 經濟部智慧財產局員工消費合作社印製 過程是由：成膜過程，及陽極氧化處理過程，及氧化過程 所構成。在成膜過程中，在下部電極1 2的一表面側形成 有無摻雜質的多結晶矽層（半導體層）。在陽極氧化處理 過程中，利用陽極氧化處理來使多結晶矽層形成多孔質化 ，藉此來形成包含多結晶矽的晶粒5 1及微結晶矽6 3的 多孔質多結晶矽層。並且，在陽極氧化處理過程中，使用 以1比1方式來混合氟化氫水溶液與乙醇之混合液，作爲 陽極氧化用的電解液。在氧化過程中，是藉由高溫製程的 急速熱氧化法來急速熱氧化多孔質多結晶矽層，分別在晶 粒5 1及微結晶矽6 3的表面形成薄絕緣膜（氧化矽膜） 5 2，6 4。 又，如第4 1圖所示，在氧化過程中，例如使用燈退 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -9 - 543209 經濟部智慧財產^7¾工消費合作社印製 A7 B7五、發明説明（7 ) 火裝置，在乾燥氧氣中以短時間來使基板溫度從室溫上升 至預定的熱處理溫度（例如，9 0 0 °C )。之後，在此熱 處理溫度下使基板溫度只保持於預定的熱處理時間（例如 ，1小時），藉此來氧化多孔質多結晶矽層。然後，使基 板溫度下降至室溫。 又，電子源並非只限於飄移層6爲氧化後的多孔質多 結晶矽層，亦可爲氮化後的多孔質多結晶矽層，或者爲氧 化或氮化後的多孔質單結晶矽層。 就具備如此的飄移層之習知的電子源而言，可大面積 化及低成本化。並且，在將此類的電子源作爲顯示器的電 子源用時，只要適當的形成表面電極及下部電極（導電性 基板）的圖案等即可。但，就此類的電子源而言，會有以 下所述的問題點發生。 (問題1 ) 就以往的此類電子源而言，在製造後各批間的電子放 出效率，絕緣耐壓，及壽命等的特性會有顯著不均一的問 題發生。經詳細考察結果，其原因乃絕緣膜（氧化矽膜） 的厚度不均一所致。 (問題2 ) 如前述，在氧化過程中雖使用急速熱氧化法，但爲了 在所有的晶粒5 1及微結晶矽6 3的表面形成良好膜質的 氧化矽膜5 2， 6 4，亦可利用所謂的氧化過程，亦即在 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -10- 543209 Α7 Β7 五、發明説明（8 ) 由硫酸，硝酸等的水溶液所構成的電解液（電解質溶液） 中，藉由電氣化學性的氧化法來氧化多孔質多結晶矽層。 (請先閱讀背面之注意事項再填寫本頁) 該電氣化學性的氧化法與急速熱氧化法相較下，可使 製程溫度低溫化。因此，可減少對基板材料的限制，在使 用玻璃基板時，可使用與石英玻璃相較下耐熱溫度低且價 格便宜的無鹼玻璃基板或低鹼玻璃基板。因此，具有可有 效地謀求電子源1 0 /， 1 0 〃的大面積化及低成本化之 優點。 但，使用電氣化學性的氧化法來氧化多孔質多結晶矽 層而製成的以往電子源，與使用急速熱氧化法所製成者相 較下，會有絕緣耐壓低的問題發生。這是因爲利用電氣化 學性的氧化法所形成的S i 0 2膜，水分及應變較多所致。 即使在使用急速熱氧化法來氧化多孔質多結晶矽層而製成 的電子源1 0 /， 1 0 〃中也會期望能夠更爲提升電子放 經濟部智慧財產笱員工消費合作社印製 出效率，絕緣耐壓及壽命。但，有關飄移層6方面，經由 種種分析評價（例如，光學發光測定，剖面T E Μ觀察， 及根據X P S的組成分析等）的結果發現，越接近飄移層 6的表面，氧化矽膜6 4的膜厚越會變大，微結晶矽6 3 會被破壞，在飄移層6的表面近旁不會有微結晶矽6 3存 在。因此，在以往的電子源1 〇 >， 1 0 〃中，被注入飄 移層6的電子的一部份有可能會被散亂或被捕捉於比產生 電子的穿隧現象的膜厚（電子的平均自由行程程度）還要 厚的氧化矽膜6 4。此情況，電子放出效率，絕緣耐壓及 壽命等會有降低之虞。 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） -11 - 543209 A7 ______B7 五、發明説明（9 ) (問題3 ) (請先閲讀背面之注意事項再填寫本頁) 在陽極氧化處理中，電解液是利用氟化氫水溶液與乙 醇的混合液。因此，如第4 2圖所示，藉由陽極氧化處理 而开>成的多孔質多結晶砂層，最上表面爲氫原子。並且， 水分會吸附於多孔質多結晶矽層的表面。 右以桌41圖所不的溫度分布來使藉由陽極氧化處理 而形成的多孔質多結晶矽層氧化，則如第4 3圖所示，氫 原子會殘留，或者發生S i -〇Η的結合。因此，難以形 成緻密的氧化膜（由S i〇2所形成的構造），且絕緣耐壓 會降低。甚至，除了氫原子以外，氟原子也有可能會殘留 於飄移層6中。並且，在飄移層6中的氫含量會形成較多 。因此，飄移層6中的氫分布會時效變化（例如，氫原子 會從飄移層6的表面脫離），電子放出效率的時效安定性 會有變差之虞。 (問題4 ) 經濟部智慧財產局員工消費合作社印製 若電子源1 0 〃的絕緣性基板1 1爲使用比石英玻璃 基板還要便宜的玻璃基板（例如，無鹼玻璃基板，低鹼玻 璃基板，鹼石灰玻璃基板等），則雖絕緣性基板1 1的耐 熱溫度會降低，但可謀求低成本化。在此，可考量降低多 結晶矽層的形成溫度（例如，6 0 0 °C以下）。 但，以較低溫來形成多結晶矽層時，與以較高溫來形 成多結晶砂層時相較下，多結晶砂層的結晶性會變差，缺 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -12- 543209 A7 B7 五、發明説明（1〇) (請先閲讀背面之注意事項再填寫本頁) 陷也會變多。其結果，飄移層6中所含的缺陷會增加，電 子放出效率會變差，且可靠度會降低。例如，若在飄移層 6的各氧化矽膜5 2，6 4中存在缺陷，則各氧化矽膜 5 2，6 4的絕緣耐壓會變低，進而導致電子源的絕緣耐 壓會降低。或者，因電子散亂，所以電子放出效率會降低 (問題5 ) 在以往的電子源1 0 >， 1 ◦〃中，在長時間連續驅 動時，二極體電流I P s會減少，放射電流I e也會隨之 減少。其原因乃電子會被捕捉於絕緣膜6 4中，加諸於絕 緣膜6 4的電場會被緩和，而造成電子的穿透確率會降低 所致。 經濟部智慧財產局8工消費合作社印製 並且，就上述的製造方法而言，由於在氧化過程中必 須採用較高熱處理溫度（例如，9 0 0 °C )及較長熱處理 時間（例如，1小時）的製程，因此製程時間會變長。而 且，絕緣性基板1 1無法使用比石英玻璃基板還要便宜且 耐熱溫度較低的無鹼玻璃基板或低鹼玻璃基板。 (問題6 ) 在以往的電子源1 〇 >， 1 0 〃中，雖可安定高效率 地來放出電子，但更期望能夠提升電子放出效率等的電子 放出特性或絕緣耐壓等的可靠性。然而，在電子源1 〇 > ，1 〇 〃中，有可能在飄移層6中存在製程中所引起的缺 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） fR209 Μ B7______ 五、發明説明（Μ) (請先閱讀背面之注意事項再填寫本頁) 陷。當在微結晶矽6 3及氧化矽膜5 2，6 4等中存在缺 陷時，會因電子散亂而造成電子放出效率降低，以及導致 絕緣耐壓降低。 〔發明之揭示〕 本發明是供以解決上述以往的問題而硏發者，其一目 的是在於提供一種可利用於平板顯示器元件，平面光源， 及固體真空裝置等，可藉由適當的電場放射來放射電子源 之高效率且高可靠度的電子源及其製造方法。 本發明之另一目的是在於提供一種絕緣耐壓及壽命的 設計容易之電子源及其製造方法。 又，本發明之另一目的是在於提供一種比以往還能夠 形成絕緣耐壓高的絕緣薄膜之絕緣薄膜的形成方法或形成 裝置，或者提供一種比以往還能夠長壽命化之電子源。 又，本發明之另一目的是在於提供一種可謀求低成本 化，可提高電子放出效率等的電子放出特性及可靠度之電 子源的製造方法。 經濟部智慧財產局員工消費合作社印製 本發明之電子源（電場放射型電子源）具備： 導電性基板；及 形成於導電性基板上的飄移層（強電場飄移層）；及 形成於飄移層上的表面電極。 並且，飄移層具有： 形成於構成該飄移層的半導體層的一部份之奈米單位 的多數個半導體微結晶；及 本紙張尺度適用中國國家標準（ CNS ) Α4規格（210X297公釐） "一 543209 A7 B7 五、發明説明（12) 形成於各半導體微結晶的表面，具有比半導體微結晶 的結晶粒徑還要小的膜厚之多數的絕緣膜。 在此，形成於各半導體微結晶的表面之絕緣層具有會 產生電子的穿隧現象的膜厚（電子的平均自由行程程度） 〇 而且，在表面電極與導電性基板之間，以表面電極會g 夠形成高電位之方式來施加電壓，藉此從導電性基板注入 飄移層的電子會飄移於飄移層內，經由表面電極而放出。 就此電子源而言，可減少各絕緣膜的電子散亂，且會g 夠縮小飄移層中之絕緣膜厚度的不均一。藉此，電子源之 絕緣耐壓及壽命的設計會更加容易。 在此電子源中，形成於各半導體微結晶的表面之絕緣 膜中所含的水分最好實質爲0 (實質上不含水分）。此情 況，由於影響電子源的電氣特性的缺陷或應變等會被緩和 ，因此可形成絕緣耐壓高且長壽命的絕緣膜。 經濟部智慧財產局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁)/ 在此電子源中，在構成飄移層的半導體層與導電性基 板的界面最好介在有由半導體與金屬所構成的化合物層或 合金層。並且，在構成飄移層的半導體層與導電性基板的 界面’最好半導體層幾乎被結晶化。該等情況，由於半導 體層與導電性基板間的阻擋層或高阻抗層會低減，因此電 子放出效率及可靠度會提升。 本發明之電子源的製造方法是供以製造本發明之上述 電子源的方法。此電子源的製造方法是藉由電氣化學性方 法’急速熱氧化法，急速熱氮化法及急速熱氧化·氮化法 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） -15- 543209 A7 B7 五、發明説明（13) (請先閲讀背面之注意事項再填寫本頁) 的其中之一，或其組合來進行往半導體微結晶表面之絕緣 膜的形成。藉此製造方法，可使絕緣膜的膜厚形成產生電 子的穿隧現象之厚度（電子的平均自由行程程度）。 在此電子源的製造方法中，最好在往半導體微結晶表 面之絕緣膜的形成後，在真空中，惰性氣體中，形成氣體 中，或氮化氣體中進行7 0 0°C以下的溫度之退火處理。 此情況，可使形成於各半導體微結晶的表面之絕緣膜中所 含的水分實質爲〇 (實質上不含水分）。又，由於半導體 層與導電性基板間的阻擋層或高阻抗層會低減，因此電子 放出效率及可靠度會提升。 在此電子源的製造方法中，最好在往半導體微結晶表 面之絕緣膜的形成後，在含氧化類或氮化類的環境中，以 6 0 0 °C以上的溫度來進行急速加熱法之熱處理。此情況 ，可更爲確實的使絕緣膜的膜厚形成產生電子的穿隧現象 之厚度。又，由於半導體層與導電性基板間的阻擋層或高 阻抗層會低減，因此電子放出效率及可靠度會提升。 經濟部智慧財產笱員工消費合作社印製 在此電子源的製造方法中，最好在往半導體微結晶表 面之絕緣膜的形成後，在惰性氣體的環境中，以6 0 0 °C 以上的溫度來進行急速加熱法之退火處理。此情況，由於 影響電子源的電氣特性的缺陷或應變等會被緩和，因此可 形成絕緣耐壓高且長壽命的絕緣膜。又，由於半導體層與 導電性基板間的阻擋層或高阻抗層會低減，因此電子放出 效率及可靠度會提升。 在此電子源的製造方法中，最好在半導體微結晶的形 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -16· 543209 A7 B7 五、發明説明（14) (請先閱讀背面之注意事項再填寫本頁) 成後’在真空中或惰性氣體中進行退火處理。此情況，與 在陽極氧化處理後馬上在水分等吸附於多孔質半導體層的 狀態下使多孔質半導體層氧化時相較下，較能夠降低因飄 移層中所含的氫或氟等雜質而引起的缺陷。藉此，可行程 緻密的氧化層，進而能夠取得電子放出效率的時效變化少 ，絕緣耐壓高，且可靠度高的電子源。又，由於半導體層 與導電性基板間的阻擋層或高阻抗層會低減，因此電子放 出效率及可靠度會提升。 在此電子源的製造方法中，最好在導電性基板上形成 半導體層後，在真空中或惰性氣體中進行退火處理。此情 況，可在半導體層與導線性基板的界面，介在有由半導體 與金屬所構成的化合物層或合金層，或者可使半導體層幾 乎形成結晶化。藉此，由於半導體層與導電性基板間的阻 擋層或高阻抗層會低減，因此可使電子放出效率及可靠度 提升。 又，在此電子源的製造方法中，可分別進行1次或複 數次下列3個處理過程的其中至少2個處理過程； 經濟部智慧財產局員工消費合作社印製 (a )在真空中，惰性氣體中，或形成氣體中進行 7 0 0 t以下的溫度之退火處理； (b )在含氧化類或氮化類的環境中，以6 0 0 °C以 上的溫度來進行急速加熱法之熱處理； (c )在惰性氣體的環境中，以6 0 0 °C以上的溫度 來進行急速加熱法之退火處理。 例如，（a) — (b) ，（a)— (c) ，（a) 一 -17- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 543209 Α7 Β7 五、發明説明（15) (b)-(b) ，( a ) - ( b ) - ( c ) ’ （a) —( c ) - ( b )等。 (請先閲讀背面之注意事項再填寫本頁) 在此電子源的製造方法中，最好在形成半導體層後’ 及在形成半導體微結晶後，以及在半導體微結晶表面形成 絕緣膜後的至少其中之一時期，進行氫氣中的退火處理’ 氫基照射處理或氫基照射退火處理。此情況，由於在導電 性基板的一表面側的最上表面會被照射氫基，因此可使飄 移層中存在的缺陷鈍化（不動態化）或降低，進而能夠提 高電子源的電子放出特性及可靠度。又，由於半導體層與 導電性基板間的阻擋層或高阻抗層會低減，因此電子放出 效率及可靠度會提升。 〔供以實施發明之最佳形態〕 以下，具體說明本發明的幾個實施形態。在此，針對 各實施形態中共通的構件（亦即構成及機能上實質爲同一 構件者）賦予相同的元件符號，並省略其重複說明。 經濟部智慧財產局員工消費合作杜印製 (實施形態1 ) 以下’說明本發明之實施形態1。在實施形態1中， 導電性基板（下部電極）是使用··阻抗率較接近導體的阻 抗率之單結晶的n型矽基板（例如，阻抗率約爲0 . 0 1 Qcm 〜〇.〇2Dcm 的（1〇〇)基板）。 如第2圖所示，在實施形態1的電子源1 〇 (電場放 射型電子源）中，在導電性基板之η型矽基板1的主表面 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐） -18- 543209 Α7 Β7 五、發明説明（16) 側形成有：由氧化的多孔質多結晶矽層所構成的飄移層6 (強電場飄移層）。並且，在n型矽基板丨的背面形成有 (請先閱讀背面之注意事項再填寫本頁) 歐姆電極2。在此實施形態1中，η型矽基板1是構成導 電性基板。 表面電極7的材料是使用功函數較小的材料。表面電 極7的厚度是設定成丨〇 ^ m。但，厚度並非只限於該値 ’只要爲通過飄移層6的電子可穿過之厚度即可。因此， 表面電極7的厚度只要設定於3〜1 5 nm的程度範圍即 可° 經濟部智慧財產^員工消費合作社印製 表面電極7是由：第1薄膜層（由形成於飄移層6上 的金屬膜所構成者），及第2薄膜層（由層疊於第1薄膜 層上的金屬膜所構成者）所構成。飄移層6上的第1薄膜 層的材料，例如可使用鉻，鎳，白金，鈦，銥等與飄移層 6的密著性高’且能夠防止在第2薄膜層與飄移層6之間 的擴散之材料。又，第2薄膜層的材料，可使用阻抗低且 時效安定性高的金等材料。在實施形態1中，第1薄膜層 的材料是使用鉻（C r )。第1薄膜層的厚度是設定成2 nm。第2薄膜層的材料是使用金（Au)。第2薄膜層 的厚度是設定成8 n m。在實施形態1中，雖是以2層的 金屬膜來構成表面電極7，但亦可爲1層或3層以上的金 屬膜。 在電子源1 0中，表面電極7是配置於真空中，且對 向於表面電極7而配置有集極電極2 1。又，施加一直流 電壓Vps，而使表面電極7對η型矽基板1 (歐姆電極 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） -19- 543209 A7 B7 五、發明説明（17) (請先閲讀背面之注意事項再填寫本頁) 2 )而言能夠形成正極，且施加一直流電壓v c，而使集 極電極2 1對表面電極7而W能夠形成正極。藉此，從η 型矽基板1而注入的電子會飄移於飄移層6內，經由表面 電極7而放出（第2圖中的一點鎖線是表示通過表面電極 7而放出之電子e -的流向）。又，流動於集極電極2 1與 表面電極7之間的放射電流（放出電子電流）I e對流動 於表面電極7與η型矽基板1 (歐姆電極2)之間的二極 體電流I p s的比率（I e / I p s )越大，電子放出效 率越高。 如第1圖所示，實施形態1的飄移層6是至少由： 柱狀多結晶矽的晶粒5 1 ;及 形成於晶粒5 1的表面的薄氧化矽膜5 2 ;及 介於晶粒5 1間的多數個奈米單位的微結晶矽6 3 ; 及 形成於各微結晶矽6 3的表面，且具有比該微結晶矽 6 3的結晶粒徑還要小的膜厚的絕緣膜（多數的氧化矽膜 6 4 );等所構成。 經濟部智慧財產局員工消費合作社印製 總而言之，在飄移層6中，各晶粒5 1的表面爲多孔 質化，在各晶粒的中心部份會維持結晶狀態。在此，形成 於微結晶砂6 3的表面之氧化砂膜6 4的厚度，最好爲產 生電子的穿隧現象之膜厚（電子的平均自由行程程度）， 例如設定成1〜3 n m的程度（電子的平均自由行程程度 :S i〇2中電子的平均自由行程約爲3 n m )。 就實施形態1的電子源1 0而言，例如可使用下述模 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -20- 543209 A7 B7 五、發明説明（18) 式所引起電子放出者。亦即，將表面電極7配置於真空中 。然後，在表面電極7與η型矽基板1 (歐姆電極2 )之 (請先閱讀背面之注意事項再填寫本頁) 間’以表面電極7作爲正極，而施加一直流電壓ν p s ， 且在集極電極2 1與表面電極7之間，以集極電極2 1作 爲正極，而施加一直流電壓V c。若直流電壓Vp s達到 預定値（臨界値），則電子e -會藉由熱激勵從導電性基板 (η型砂基板1 )往飄移層6注入。另一方面，大部分施 加於飄移層6的電場會位於氧化矽膜6 4。因此，所被注 入的電子e —會藉由施加於氧化矽膜6 4的強電場而加速。 而且’電子會在飄移層6內使晶粒5 1間的領域朝向表面 而飄移於第1圖中箭頭A的方向，穿過表面電極7而放出 於真空中。如此一來，在飄移層6中，從η型矽基板1注 入的電子在微結晶矽6 3中幾乎不會散亂，在施加於氧化 矽膜6 4的強電場中會被加速而飄移，經由表面電極7而 放出（彈道型電子放出現象）。並且，在飄移層6產生的 熱會經由晶粒5 1而釋放出。因此，電子放出時不會有電 子跳動現象產生，可安定的釋放出電子。而且，到達飄移 經齊部智慧財產笱员工消費合作社印製 層6表面的電子爲熱電子，容易穿過表面電極7而放出於 真空中。 以下’一邊參照第3 Α〜3 D圖，一邊說明實施形態 1之電子源1 〇的製造方法。 首先’在η型矽基板1的背面形成歐姆電極2之後， 在η型砂基板1的主表面上形成無摻雜質的多結晶矽層3 (半導體層），而取得第3 Α圖所示的構造。就多結晶砂 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -21 - 543209 A7 B7 五、發明説明（19) 層3的成膜方法而言，例如可使用：C V D法（ (請先閱讀背面之注意事項再填寫本頁) L P C V D法，電漿C V D法，觸媒C V D法等），濺鍍 法，及 C S G ( Continuous Grain Silicon)法等。 在形成無摻雜質的多結晶矽層3之後，在陽極氧化處 理過程中使多結晶矽層3多孔質化，藉此來形成多孔質半 導體層（多孔質多結晶矽層4 )，取得第3 B圖所示的構 造，在陽極氧化處理過程中是使用放進有電解液的陽極氧 化處理槽，該電解液是由：以1比1方式來混合5 5 w t %的氟化氫水溶液與乙醇之混合液所形成。然後，以白金 電極（圖中未示）作爲負極，以η型矽基板1 (歐姆電極 2 )作爲正極，一邊對多結晶矽層3進行光照射，一邊以 定電流來進行陽極氧化。藉此來形成多孔質多結晶矽層4 。如此形成的多孔質多結晶矽層4包含多結晶矽的晶粒及 微結晶矽。並且，在實施形態1中，雖是使多結晶矽層3 全體多孔質化，但亦可只使一部份多孔質化。 經濟部智慧財/i^M工消費合作社印製 在陽極氧化處理過程終了後，以氧化過程來使多孔質 多結晶矽層4氧化，藉此來形成由氧化後的多孔質多結晶 矽層所構成的飄移層6，取得第3 C圖所示的構造。在氧 化過程中’以急速加熱法來使多孔質多結晶砂層4氧化， 藉此來形成含晶粒5 1 ，微結晶砂6 3及各氧化砂膜5 2 ，6 4的飄移層6。在急速加熱法的氧化過程中是使用燈 退火裝置。此情況，爐內爲0 2氣體環境，且以規定的升溫 速度（例如，8 0 °C / s e c )來使基板溫度從室溫上升 至預疋的氧化溫度（例如9 0 〇。(：）。並且，只使基板溫 本紙張尺度適用中國國家標準（CNS ) A4規格(210x297公釐） -- -22- 543209 Α7 Β7 五、發明説明（20 ) (請先閲讀背面之注意事項再填寫本頁) 度維持預定的氧化溫度（例如，1小時），而來進行急速 熱氧化（R T〇）。然後，使基板溫度下降至室溫。在實 施形態1中，雖是將升溫速度設定成8 0 °C / s e c ，但 亦可設定成8 0 °C / s e c以上，更理想是設定成1 5 0 t / s e c以上。之所以會如此設定升溫速度。其理由會 在往後敘述。在實施形態1中，氧化過程是供以在半導體 微結晶（微結晶矽6 3 )的表面側形成絕緣膜（氧化矽膜 6 4 )之絕緣膜形成過程。 在形成飄移層6之後，藉由電子束蒸鍍法來將由金屬 膜（在實施形態1中爲鉻膜）所構成的第1薄膜層形成於 飄移層6上。又，藉由電子束蒸鍍法來將由金屬膜（在實 施形態1中爲金膜）所構成的第2薄膜層形成於第1薄膜 層上。藉此，由第1薄膜層與第2薄膜層所構成的表面電 極7會被形成，取得第3 D圖所示構造的電子源1 0。在 實施形態1中，雖是藉由電子束蒸鍍法來形成表面電極7 ，但表面電極7的形成方法並非只限於電子束蒸鍍法，例 如亦可使用濺鍍法。 經濟部智慧財產笱員工消費合作社印製 但，本發明者的硏究結果發現，急速加熱法之氧化過 程的條件，尤其是升溫速度會影響電子放出效率，絕緣耐 壓，壽命等的特性。 在此，本發明者是針對電子源1 〇的飄移層6進行分 析評價（將急速加熱法的升溫速度設定成8 0 °C / s e c )。具體而言，是在於進行根據光致發光法（L P )之飄 移層6的表面近旁的構造評價，及根據剖面T E Μ (透過 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） -23- 543209 A7 B7 五、發明説明（21) (請先閲讀背面之注意事項再填寫本頁) 型電子顯微鏡）之飄移層表面近旁部的構造觀察及元素分 析，及有關根據X線光電子分光分析法（X p s法）之飄 移層構成元素的存在量之深度方向的分布測定。又，有關 比較例的電子源（飄移層）方面，亦進行同樣的分析評價 。比較例的電子源，是將急速加熱法的升溫速度設定成比 80°C/s e c還要低速，亦即設定成2〇°C/s e c。 其結果，就升溫速度設定成2 0 °C / s e c的比較例而言 ，會在飄移層內，從表面（與表面電極7的界面）到 1 0 0 n m爲止的深度形成有s i ◦ 2膜，但無微結晶矽存 在。相對的，在將升溫速度設定成較高速（8 0 °C / s e c )之電子源1 〇的飄移層6中，從表面到 1 0 0 n m深度爲止的領域中亦形成有微結晶矽6 3。 經濟部智慧財產局員工消費合作社印製 以下，說明各分析評價的結果。首先，分別說明有關 針對實施形態1之電子源1 〇的飄移層6與比較例之飄移 層的表面近旁構造進行剖面T E Μ (透過型電子顯微鏡） 的觀察及元素分析結果。根據剖面Τ Ε Μ的評價，在電子 源1 0的飄移層6中，多結晶矽的柱狀晶粒及奈米單位的 微結晶矽會被確認出。相對的，在比較例的飄移層中，從 表面到1 0 0 n m的深度爲止，全領域形成有S i〇2膜， 而多結晶矽的柱狀晶粒只形成於比1 〇 〇 n m還要深的領 域。 其次，一邊參照第4圖，一邊說明P L法之飄移層表 面近旁部的構造評價的結果。 第4圖是表示從H e - C d雷射照射波長爲 本紙張尺度適用中國國家標準（CNS ) M規格（2ΐ〇χ297公釐] ~ 543209 Α7 Β7 五、發明説明（22) (請先閱讀背面之注意事項再填寫本頁) 3 2 5 nm的光來進行測定的發光頻譜。第4圖中的a是 表示實施形態1之飄移層6的發光頻譜，b是表示比較例 之飄移層的發光頻譜。從H e - C d雷射照射的光侵入飄 移層6的長度爲深入飄移層6的表面1 0 〇 nm以內。因 此，第4圖中的a及b的各發光頻譜是表示來自表面近旁 的淺領域的發光頻譜。一般，來自氧化矽膜的發光被稱爲 F頻帶（band)，在4 3〇nm〜5 4 0 nm附近具有峰値。 又，來自微結晶矽的發光被稱爲S頻帶（band)，在 6 5 0 nm〜8 0 0 nm附近具有峰値。由第4圖可明確 觀測到在實施形態1中來自微結晶矽6 3的發光峰値及來 自氧化矽膜的發光峰値。相對的，在比較例的飄移層中只 有來自氧化矽膜的發光峰値會被觀測到。亦即，在從比較 例的飄移層6表面到深度1 0 0 n m爲止的領域中幾乎不 存在微結晶砂，大部分甚至全部是形成氧化砂膜。該結果 與剖面T E Μ的分析結果一致。 經濟部智慧財產笱員工消費合作社印製 其次，一邊參照第5圖，一邊說明有關XP S法之飄 移層構成元素的存在量之深度方向的分布測定結果。第5 圖的橫軸是表示來自飄移層6的表面深度。第5圖的縱軸 是表示原子濃度。第5圖中的a 1 ，a 2及a 3是表示有 關實施形態1之飄移層6的測定結果。又，b 1 ，b 2及 b 3是表不有關比較例之飄移層的測定結果。在此，a 1 及b 1是表示S i〇2的深度方向分布，a 2及b 2是表示 Si的深度方向分布，a3及b3是表示Si〇x的深度方 向分布。由第5圖可明確得知，在實施形態1的飄移層6 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） -25- 543209 A7 B7 五、發明説明（23) (請先閲讀背面之注意事項再填寫本頁) 中’在比表面深度1 0 〇 nm還要淺的領域中觀察到S i 及S i〇2。相對的，在比較例的飄移層中，在比表面深度 1 0 0 n m還要淺的領域中並未觀察到S i ，而只觀察到 5 i ◦ 2。該結果與剖面τ E Μ的分析結果一致。 由以上的各分析結果可知（如第6 Α圖及第6 Β圖所 示）’在實施形態1的飄移層6中，在飄移層6的表面近 旁亦含表面形成有氧化矽膜6 4的微結晶矽6 3。又，注 入飄移層6的電子e -會藉由加諸於氧化矽膜6 4的強電場 而加速’且在幾乎不會衝突於微結晶矽6 3的情況下漂移 至第6A圖中的箭頭方向（向右），而到達飄移層6的表 面，穿過表面電極7而放出於真空中。（第6A圖中的一 點鎖線是表示電子e -的流向）。並且，在第6 A圖的上部 所記載的「PPS」是表示飄移層6，「Me t a 1」是 表示表面電極7， 「Vacuum」是表示真空。又，第 6 B圖是供以說明電子放出原理的能帶圖。第6 B圖中的 「Si〇2」是表示氧化矽膜64，「//c — Si」是表示 經濟部智慧財產局員工消費合作社印製 奈米單位的微結晶矽6 3，「E F μ」是表示表面電極7的 費密（Fermi)位準，「Eva」是表示真空位準。 另一方面，如第7圖所示，在比較例的飄移層（以下 稱爲「飄移層6 /」）中，越接近飄移層6 >的表面，氧 化矽膜6 4的膜厚會越大，而造成微結晶矽6 3會被破壞 。並且，在表面近旁不存在微結晶矽6 3。因此，注入飄 移層6 >的電子e -的一部份會被散亂或吸收於比產生電子 的穿隧現象的膜厚（電子的平均自由行程程度）還要厚的 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -26- 543209 A7 B7 五、發明説明（24) 氧化砂膜6 4 ，因此電子放出效率會降低，或者絕緣耐壓 及壽命會降低。 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 在實施形態1的飄移層6中，連表面近旁也會有微結 晶矽6 3存在，相對的，在比較例的飄移層6 >中，微結 晶矽6 3會在表面近旁被破壞，其原因如以下所述。亦即 ，就實施形態1而言，是在陽極氧化處理過程後的氧化過 程中，如第8 A圖所示，氧分子8 0會到達微結晶矽6 3 的周圍。此刻，由於升溫速度爲較高的速度（8 0 °C / s _ e c )，因此氧化矽膜6 4會在短時間下來形成於藉由陽 極氧化而形成的微結晶矽6 3的表面側。因此，往微結晶 矽6 3的中心部之氧原子8 1的擴散會被阻止，藉此產生 電子的穿隧現象之膜厚（電子的平均自由行程程度）的氧 化矽膜6 4會被形成。相對的，就比較例而言，在陽極氧 化處理過程後的氧化過程中，如第8 A圖所示，氧分子 8 0也會到達微結晶矽6 3的周圍。但，由於升溫速度爲 較低的速度（2 0 °C / s — e c )，因此氧原子8 1會擴散 至藉由陽極氧化而形成的微結晶矽6 3的中心部，造成微 結晶矽6 3全體會被氧化。此乃爲微結晶矽6 3遭到破壞 的原因。543209 A7 B7 V. Description of the Invention (1) [Technical Field] (Please read the precautions on the back before filling out this page) The present invention relates to electric field emission type electron sources that emit semiconductor electrons through electric field radiation and The manufacturing method thereof, and a method and apparatus for forming an insulating film on a surface of a semiconductor crystal during the manufacture of an electric field emission type electron source. [Background Art] A conventional electric field emission type electron source (hereinafter referred to as an "electron source") is, for example, a Spindt electrode disclosed in U.S. Patent No. 3 6 6 5 2 4 1. The Spindt-type electrode includes a substrate on which a plurality of tiny triangular pyramid-shaped emitter pieces are arranged, and a gate layer that is insulated from one of the emitter pieces having a radiation hole that exposes the tip of the emitter piece. In addition, the Spindt-type electrode applies a high voltage in a vacuum so that the emitter sheet can form a negative electrode for the gate layer, so that electron rays are emitted from the tip of the emitter sheet through a radiation hole. However, the Spindt-type electrode has a complicated manufacturing process, and it is difficult to produce high-precision printed triangular cone-shaped emitter pieces for most of the employees' cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Therefore, when it is applied to a flat light-emitting device, a display, or the like, there is a problem that it is difficult to increase the area. Furthermore, in Spindt-type electrodes, since the electric field is concentrated on the tip of the emitter piece, when the vacuum around the tip of the emitter piece is low and residual gas is present, the residual gas is ionized into positive ions due to the emitted electrons. . Moreover, because this positive ion collides with the front end of the emitter piece, the front end of the emitter piece is damaged (damaged by ion impact). As a result, the current density and discharge efficiency of the emitted electrons are unstable, and the life of the emitter piece is shortened. In order to apply the Chinese National Standard (CNS) A4 specification (210X 297 mm) to this paper size -4-543209 A7 B7 V. Description of the invention (2) (Please read the precautions on the back before filling this page) Prevent this, Spindt The type electrode must be used under high vacuum (about 10-5 Pa to about 10-6 Pa). As a result, the cost becomes high and the processing is troublesome. In order to improve this problem, an electron source of the type MIM (Metal Insulator Metal) or the type MOS (Metal Oxide Semiconductor) is proposed. The former is a planar electron source having a metal-insulating film-metal laminated structure, and the latter is a planar electron source having a metal-oxide film-semiconductor laminated structure. In such an electron source, in order to improve the electron emission efficiency (that is, to make more electrons radiate), it is necessary to make the film thickness of the insulating film or the oxide film thin. However, if the film thickness of the insulating film or the oxide film is too thin, there is a possibility that the insulation may be broken when a voltage is applied between the upper and lower electrodes of the laminated structure. Since such insulation breakdown must be prevented, the thickness of the insulating film or the oxide film is limited. Therefore, the discharge efficiency (extraction efficiency) of the electron source cannot be improved to some extent. Printed by the Intellectual Property of the Ministry of Economic Affairs and the Consumers' Cooperative, therefore, in recent years, as disclosed in Japanese Unexamined Patent Publication No. 8-2 0 0 666, proposal 1 proposes an electron source with high electron emission efficiency (semiconductor cold electron emission efficiency), That is, a voltage is applied between the semiconductor substrate and the surface electrode, so that electrons can be emitted. In this electron source, one surface of a single crystal semiconductor substrate such as a silicon substrate is anodized to form a porous semiconductor layer (porous silicon layer). A surface electrode made of a metal thin film (conductive film) is formed on the porous semiconductor layer. However, with regard to the electron source disclosed in Japanese Patent Application Laid-Open No. 8-2 0 0 666, the phenomenon of beating easily occurs when electrons are emitted, and the amount of electrons emitted is likely to be uneven. Therefore, if it is applied to flat hair, the paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 543209 A7 B7 V. Description of the invention (3) There may be problems of uneven light emission when the light device or display is used. In order to solve such a problem, the present inventors proposed in Japanese Patent Application No. 10- (please read the notes on the back and fill in this page) 272340 and Japanese Patent Application No. 10-272342, etc .: An electron source of a strong electric field drifting layer (hereinafter referred to as "drifting layer") is provided between the substrate and the metal thin film (surface electrode). This drift layer is composed of an oxidized porous polycrystalline silicon layer. For example, as shown in FIG. 38, in the case of such an electron source 10 /, a main surface of the n-type silicon substrate 1 of the conductive substrate is formed with an oxidized porous polycrystalline sand layer (which is porous) Layer of morphological polycrystalline sand). A surface electrode 7 made of a metal thin film (for example, a gold thin film) is formed on the drift layer 6. An ohmic electrode 2 is formed on the back surface of the n-type silicon substrate 1. The n-type silicon substrate 1 and the ohmic electrode 2 constitute a lower electrode 12 (conductive substrate). In the example of the electron source shown in FIG. 38, although an undoped polycrystalline silicon layer 3 is interposed between the lower electrode 12 and the drift layer 6, it may be directly on the lower electrode 12 Forming a drift layer 6. Printed by the Intellectual Property of the Ministry of Economic Affairs and the Consumers' Cooperative, and is provided with a surface electrode 7 facing the surface electrode 7: for example, a collector electrode 21 made of a transparent conductive film (ITO film). When the electrons are released from the electron source 10, the surface electrode 7 and the collector electrode 21 are in a vacuum state, and the surface electrode 7 can form a high potential to the conductive layer 12. A DC voltage V ps is applied between the conductive layers 12 and a direct current is applied between the collector electrode 21 and the surface electrode 7 in such a way that the collector electrode 21 can form a high potential to the surface electrode 7. This paper is suitable for China National Standard (CNS) Α4 Specification (210X 297 mm)-6-543209 hi ______ _B7_ V. Description of Invention (4) (Please read the precautions on the back before filling this page) Voltage V c. As long as the DC voltages νρ s and Vc are appropriately set, the electrons injected from the conductive layer 12 will drift in the drift layer 6 and be released through the surface electrode 7 (a point of the lock line in FIG. 38 indicates the passage through The flow direction of the electrons e-emitted from the surface electrode 7). The thickness of the surface electrode 7 is set to a range of about 3 to 15 nm. The drift layer 6 is formed by forming a non-doped polycrystalline sand layer on the lower electrode 12 and then anodizing the polycrystalline silicon layer to make the polycrystalline silicon layer porous, thereby forming a porous polycrystalline silicon layer. The rapid thermal oxidation method, for example, rapidly thermally oxidizes the porous polycrystalline silicon layer at 900 ° C. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, as shown in Figure 39, the drift layer 6 is composed of at least: columnar polycrystalline silicon grains 5 1 and thin insulating films 5 2, and many nanometer units. It is composed of microcrystalline silicon 6 3 and most silicon oxide films 64. The crystal grains 51 are arranged on the main surface side of the n-type silicon substrate 1 (that is, on the surface electrode 7 side of the lower electrode 12). The insulating film 52 is formed on the surface of the crystal grain 51. The microcrystalline silicon 63 is between the grains 51. The insulating film 64 is formed on the surface of each microcrystalline silicon 63, and has a film thickness smaller than the crystal grain size of the microcrystalline silicon 63. In a word, in the drift layer 6, the surface of each crystal grain 51 in the polycrystalline sand layer becomes porous, and a crystalline state is maintained in the center portion of each crystal grain 51. Each crystal grain 51 extends in the thickness direction of the lower electrode 12. Each of the insulating films 52 and 64 is made of a silicon oxide film. In the electron source 10 ', it is conceivable that electrons are emitted in a mode described below. That is, when the electrons are emitted, a high-voltage DC voltage V ps is applied between the surface electrode 7 and the lower electrode 12, and the paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) ~ '543209 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 _B7 _ V. Description of the invention (5) and applying a collector electrode 21 1 between the collector electrode 21 and the surface electrode 7 to a high potential DC voltage V c. If the DC voltage V p s reaches a predetermined threshold (critical threshold), the electrons e _ are injected into the drift layer 6 from the lower electrode 12 by thermal excitation. On the other hand, most of the electric field applied to the drift layer 6 is applied to the insulating film 64. Therefore, the injected electron e- is accelerated by a strong electric field applied to the insulating film 64. Then, the electron e — will move the area between the grains 51 in the drift layer 6 toward the surface in the direction of the arrow A in FIG. 39, pass through the surface electrode 7 and put it in a vacuum. In this way, in In the drift layer 6, the electrons injected from the lower electrode 12 are hardly scattered in the microcrystalline silicon 63, and are accelerated and drifted in an electric field applied to the insulating film 64. Then, it is emitted through the surface electrode 7 (ballistic electron emission image). At this moment, the heat generated in the drift layer 6 is released through the crystal grains 51. Therefore, there is no electron jumping phenomenon when the electrons are emitted, and the electrons can be released stably. In addition, the electrons reaching the surface of the drift layer 6 are thermoelectrons, which easily pass through the surface electrode 7 and are released into a vacuum. As for the electron source 10 >, although the lower electrode 12 is composed of the η-type silicon substrate 1 and the ohmic electrode 2, as shown in the electron source 1 of FIG. 40, it is also possible to use an insulating substrate A lower electrode 12 made of a metal material is formed on one surface of 1 1 (for example, made of a glass substrate). In Fig. 40, the same reference numerals are given to the constituent elements common to the electron source 10 / shown in Fig. 38, and descriptions thereof are omitted. The electron source 10 0 shown in Figure 40 can also be used with the electron source shown in Figure 38 (please read the precautions on the back before filling out this page) The paper size applies to the Chinese National Standard (CNS) Α4 specification (210 '乂 297mm) -8- PR209 A7 B7 V. Description of the invention (6) 1 0 / Same process for electron emission. In the electron source 1 0 /, 10 通常, the electric current flowing on the surface is usually read (please read the precautions on the back before filling this page) The current between the electrode 7 and the lower electrode 12 is called the diode current I p S and a current flowing between the collector electrode 21 and the surface electrode 7 are referred to as an emission current (emission electron current) I e. Here, the larger the ratio of the radiation current I e to the diode current I p s (I e / I p s), the higher the electron emission efficiency ((I e / I sp) x 100 [%]). In the electron source 10 /, 10〃, even if the DC voltage V p s applied between the surface electrode 7 and the lower electrode 12 is a low voltage of about 10 to 20 V, electrons can be emitted. In addition, the larger the DC voltage V p s is, the larger the radiation current I e is formed. In the process of electron source 10 >, 10 〃, the printing process of the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, which forms the drift layer 6, is composed of a film formation process, an anodizing process, and an oxidation process. During film formation, a non-doped polycrystalline silicon layer (semiconductor layer) is formed on one surface side of the lower electrode 12. In the anodizing process, the polycrystalline silicon layer is made porous by the anodizing process, thereby forming a porous polycrystalline silicon layer containing crystal grains 51 and microcrystalline silicon 63 of polycrystalline silicon. In the anodizing process, a mixed solution of an aqueous hydrogen fluoride solution and ethanol was used in a 1: 1 manner as an electrolytic solution for anodizing. During the oxidation process, the porous polycrystalline silicon layer is rapidly and thermally oxidized by the rapid thermal oxidation method at a high temperature process, and a thin insulating film (silicon oxide film) is formed on the surface of the crystal grain 5 1 and the microcrystalline silicon 6 3 respectively. 5 2, 6 4. In addition, as shown in Figure 41, during the oxidation process, for example, the paper size of the paper used for the return of the lamp applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) -9-543209 Intellectual Property of the Ministry of Economic Affairs ^ 7¾ Industrial Consumer Cooperative Printing A7 B7 V. Description of the invention (7) The fire device raises the temperature of the substrate from room temperature to a predetermined heat treatment temperature (for example, 900 ° C) in a short time in dry oxygen. After that, the substrate temperature is kept at the predetermined heat treatment time (for example, 1 hour) at this heat treatment temperature, thereby oxidizing the porous polycrystalline silicon layer. Then, the substrate temperature was lowered to room temperature. The electron source is not limited to the drift layer 6 being an oxidized porous polycrystalline silicon layer, it may be a nitrided porous polycrystalline silicon layer, or an oxidized or nitrided porous single crystalline silicon layer. A conventional electron source having such a drift layer can be made larger in area and lower in cost. When such an electron source is used as an electron source for a display, the surface electrode and the lower electrode (conductive substrate) must be appropriately formed in a pattern or the like. However, for such an electron source, the problems described below occur. (Question 1) For such conventional electron sources, the characteristics such as the electron emission efficiency, insulation withstand voltage, and life span between batches after manufacturing have been significantly uneven. As a result of detailed inspection, the reason was the uneven thickness of the insulating film (silicon oxide film). (Question 2) As mentioned above, although a rapid thermal oxidation method is used in the oxidation process, in order to form a good silicon oxide film 5 2, 6 4 on the surface of all the crystal grains 5 1 and microcrystalline silicon 6 3, Use the so-called oxidation process, that is, (please read the precautions on the back before filling this page) This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -10- 543209 Α7 Β7 5. Description of the invention ( 8) In an electrolytic solution (electrolyte solution) composed of an aqueous solution of sulfuric acid and nitric acid, the porous polycrystalline silicon layer is oxidized by an electrochemical oxidation method. (Please read the precautions on the back before filling this page.) Compared with the rapid thermal oxidation method, this electrochemical oxidation method can lower the process temperature. Therefore, restrictions on the material of the substrate can be reduced, and when a glass substrate is used, an alkali-free glass substrate or a low-alkali glass substrate which has a lower heat resistance than quartz glass and is inexpensive can be used. Therefore, there is an advantage that the area of the electron source 10 /, 10 〃 can be effectively increased and the cost can be reduced. However, the conventional electron source produced by oxidizing a porous polycrystalline silicon layer using an electrochemical oxidation method has a problem of lower insulation withstand voltage compared to a method using a rapid thermal oxidation method. This is because the S i 0 2 film formed by the electrochemical oxidation method has a large amount of moisture and strain. Even in the electron source 10 /, 10, which is made by oxidizing the porous polycrystalline silicon layer using rapid thermal oxidation, it is expected that the intellectual property of the Ministry of Electronics and Economics, and the efficiency of printing by employee consumer cooperatives will be further improved. , Insulation withstand voltage and life. However, with regard to the drift layer 6, through various analysis and evaluation (for example, optical luminescence measurement, cross-section TEM observation, and composition analysis according to XPS, etc.), it was found that the closer to the surface of the drift layer 6, the closer the silicon oxide film 64 is As the film thickness becomes larger, the microcrystalline silicon 6 3 is destroyed, and no microcrystalline silicon 6 3 exists near the surface of the drift layer 6. Therefore, in the conventional electron source 1 0 > 10 〃, a part of the electrons injected into the drift layer 6 may be scattered or trapped in a film thickness (electron that is larger than the electron tunneling phenomenon). The average free stroke degree) is even thicker than the silicon oxide film 6 4. In this case, the electron emission efficiency, insulation withstand voltage, and life may be reduced. This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) -11-543209 A7 ______B7 V. Description of the invention (9) (Question 3) (Please read the precautions on the back before filling this page) On the anode In the oxidation treatment, the electrolytic solution is a mixed solution of an aqueous hydrogen fluoride solution and ethanol. Therefore, as shown in Fig. 42 and Fig. 4, the porous polycrystalline sand layer formed by the anodization treatment has a hydrogen atom at its uppermost surface. In addition, moisture is adsorbed on the surface of the porous polycrystalline silicon layer. On the right, the porous polycrystalline silicon layer formed by anodic oxidation is oxidized with the temperature distribution shown in Table 41. As shown in Figure 43, hydrogen atoms may remain, or S i -〇Η Combined. Therefore, it is difficult to form a dense oxide film (a structure formed by Si02), and the dielectric breakdown voltage is reduced. Furthermore, in addition to hydrogen atoms, fluorine atoms may remain in the drift layer 6. And, the hydrogen content in the drift layer 6 will be formed more. Therefore, the hydrogen distribution in the drift layer 6 may change with time (for example, hydrogen atoms may be detached from the surface of the drift layer 6), and the aging stability of the electron emission efficiency may be deteriorated. (Question 4) Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs, if the electron source is 10 〃, the insulating substrate 11 is a glass substrate that is cheaper than the quartz glass substrate (for example, alkali-free glass substrate, low-alkali glass substrate , Soda-lime glass substrate, etc.), although the heat-resistant temperature of the insulating substrate 11 is lowered, the cost can be reduced. Here, consideration can be given to lowering the formation temperature of the polycrystalline silicon layer (for example, below 600 ° C). However, when the polycrystalline silicon layer is formed at a lower temperature, the crystallinity of the polycrystalline sand layer will be lower than that when the polycrystalline sand layer is formed at a higher temperature. The Chinese National Standard (CNS) A4 specification will be applied to this paper. (210X 297mm) -12- 543209 A7 B7 V. Description of the invention (1〇) (Please read the notes on the back before filling this page) There will be more traps. As a result, the defects contained in the drift layer 6 increase, the electron emission efficiency deteriorates, and the reliability decreases. For example, if there is a defect in each of the silicon oxide films 5 2 and 64 of the drift layer 6, the insulation withstand voltage of each of the silicon oxide films 5 2 and 6 4 becomes low, and the insulation withstand voltage of the electron source is reduced. Or, the electron emission efficiency is reduced due to scattered electrons (Question 5) In the conventional electron source 1 0 >, 1 ◦〃, during continuous driving for a long time, the diode current IP s decreases and the radiation current I e will also decrease. The reason is that electrons will be trapped in the insulating film 64, and the electric field applied to the insulating film 64 will be relaxed, which will cause the electron penetration accuracy to decrease. Printed by the 8th Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and, as for the above-mentioned manufacturing method, since a high heat treatment temperature (for example, 900 ° C) and a long heat treatment time (for example, 1 Hours), so the process time will be longer. In addition, the insulating substrate 11 cannot use an alkali-free glass substrate or a low-alkali glass substrate which is cheaper than a quartz glass substrate and has a lower heat resistance. (Question 6) In the conventional electron source 10 and 10, it is possible to discharge electrons stably and efficiently, but it is more desirable to improve the electron emission characteristics such as the electron emission efficiency and the reliability of the withstand voltage and the like. . However, in the electron source 10 and 10, there may be a defect in the drift layer 6 caused by the manufacturing process. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) fR209 Μ B7______ V. Description of the Invention (Μ) (Please read the notes on the back before filling this page). When there are defects in the microcrystalline silicon 6 3 and the silicon oxide film 5 2, 64, etc., the electron emission efficiency is lowered due to the scattered electrons, and the insulation withstand voltage is lowered. [Disclosure of the Invention] The present invention has been developed to solve the above-mentioned conventional problems, and an object thereof is to provide a flat display device, a flat light source, and a solid vacuum device, which can be radiated by an appropriate electric field. A high-efficiency and high-reliability electron source that emits an electron source and a manufacturing method thereof. Another object of the present invention is to provide an electron source whose insulation withstand voltage and life are easy to design and a manufacturing method thereof. Another object of the present invention is to provide a method or a device for forming an insulating film capable of forming an insulating film having a higher dielectric withstand voltage than in the past, or to provide an electron source having a longer life than the conventional method. Another object of the present invention is to provide a method for manufacturing an electron source which can reduce the cost and improve the electron emission characteristics and reliability of the electron emission efficiency. The electron source (electric field emission type electron source) of the present invention printed by an employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs includes: a conductive substrate; and a drift layer (strong electric field drift layer) formed on the conductive substrate; and a drift layer formed on the conductive substrate; On the surface electrode. In addition, the drift layer has: a plurality of semiconductor microcrystals formed in nanometer units of a part of the semiconductor layer constituting the drift layer; and this paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) " 543209 A7 B7 V. Description of the invention (12) An insulating film formed on the surface of each semiconductor microcrystal and having a thickness smaller than the crystal grain size of the semiconductor microcrystal. Here, the insulating layer formed on the surface of each semiconductor microcrystal has a film thickness (average degree of free travel of electrons) that causes a tunneling phenomenon of electrons. Further, between the surface electrode and the conductive substrate, the surface electrode is formed by the surface electrode. g. A voltage is applied in a high-potential manner, whereby electrons injected into the drift layer from the conductive substrate will drift in the drift layer and be released through the surface electrode. With this electron source, the scattering of electrons in each insulating film can be reduced, and the unevenness of the thickness of the insulating film in the drift layer can be reduced. This makes it easier to design the insulation withstand voltage and life of the electron source. In this electron source, the moisture contained in the insulating film formed on the surface of each semiconductor microcrystal is preferably substantially 0 (substantially free of moisture). In this case, defects or strains that affect the electrical characteristics of the electron source are alleviated, so an insulating film with a high insulation withstand voltage and a long life can be formed. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) / In this electron source, the interface between the semiconductor layer and the conductive substrate constituting the drift layer is preferably interposed between the semiconductor and the A compound or alloy layer made of metal. Further, it is preferable that the semiconductor layer is almost crystallized at the interface 'between the semiconductor layer constituting the drift layer and the conductive substrate. In these cases, since the barrier layer or high-resistance layer between the semiconductor layer and the conductive substrate is reduced, the electron emission efficiency and reliability are improved. The manufacturing method of the electron source of the present invention is a method for manufacturing the above-mentioned electron source of the present invention. The manufacturing method of this electron source is through the electrochemical method 'rapid thermal oxidation method, rapid thermal nitridation method and rapid thermal oxidation and nitridation method. The paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) ) -15- 543209 A7 B7 V. Description of Invention (13) (Please read the precautions on the back before filling out this page), or a combination of them, to form the insulating film on the surface of the semiconductor microcrystal. According to this manufacturing method, the film thickness of the insulating film can be formed to a thickness (an average free-path degree of electrons) that causes electron tunneling. In this method of manufacturing an electron source, it is preferable to perform a temperature below 700 ° C in a vacuum, an inert gas, a forming gas, or a nitriding gas after the formation of an insulating film on the surface of a semiconductor microcrystal. Annealing treatment. In this case, the moisture contained in the insulating film formed on the surface of each semiconductor microcrystal can be made substantially zero (substantially free of moisture). In addition, since the barrier layer or the high-resistance layer between the semiconductor layer and the conductive substrate is reduced, the electron emission efficiency and reliability are improved. In this method of manufacturing an electron source, it is preferable to perform a rapid heating method at a temperature of 600 ° C or more in an environment containing an oxidation type or a nitride type after the formation of an insulating film on the surface of a semiconductor microcrystal. Of heat treatment. In this case, the film thickness of the insulating film can be formed to a thickness that causes electron tunneling. In addition, since the barrier layer or the high-resistance layer between the semiconductor layer and the conductive substrate is reduced, the electron emission efficiency and reliability are improved. Printed by the Intellectual Property of the Ministry of Economic Affairs and Consumer Cooperatives in this electron source manufacturing method, preferably after the formation of an insulating film on the surface of the semiconductor microcrystals, in an inert gas environment at a temperature above 60 ° C To perform the annealing process of the rapid heating method. In this case, defects or strains that affect the electrical characteristics of the electron source are alleviated, so that an insulating film with a high insulation withstand voltage and a long life can be formed. In addition, since the barrier layer or the high-resistance layer between the semiconductor layer and the conductive substrate is reduced, the electron emission efficiency and reliability are improved. In this method of manufacturing an electron source, it is best to apply the Chinese National Standard (CNS) A4 (210X297 mm) to the paper size of the semiconductor microcrystals. -16 · 543209 A7 B7 V. Description of the invention (14) (please first (Please read the notes on the back and fill in this page.) After the completion of the annealing process in vacuum or inert gas. In this case, compared with the case where the porous semiconductor layer is oxidized in a state where moisture or the like is adsorbed on the porous semiconductor layer immediately after the anodization treatment, it is possible to reduce the occurrence of impurities such as hydrogen or fluorine contained in the drift layer. Defects. Thereby, a dense oxide layer can be traveled, and an electron source with less aging changes in electron emission efficiency, high insulation withstand voltage, and high reliability can be obtained. In addition, since the barrier layer or the high-resistance layer between the semiconductor layer and the conductive substrate is reduced, the electron emission efficiency and reliability are improved. In this method of manufacturing an electron source, it is preferable to perform an annealing treatment in a vacuum or an inert gas after forming a semiconductor layer on a conductive substrate. In this case, a compound layer or an alloy layer composed of a semiconductor and a metal may be interposed at the interface between the semiconductor layer and the conductive substrate, or the semiconductor layer may be almost crystallized. Accordingly, since the barrier layer or the high-resistance layer between the semiconductor layer and the conductive substrate is reduced, the electron emission efficiency and reliability can be improved. In addition, in this method of manufacturing an electron source, one or more of the following three processes can be performed at least two of them respectively; printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (a) in a vacuum, inert Annealing in a gas or forming gas at a temperature below 700 t; (b) in an environment containing oxides or nitrides, heat treatment at a temperature above 600 ° C ; (C) performing an annealing treatment in a rapid heating method in an inert gas environment at a temperature of 600 ° C or more. For example, (a) — (b), (a) — (c), (a) — 17— This paper size applies to the Chinese National Standard (CNS) A4 specification (210X 297 mm) 543209 Α7 Β7 V. Description of the invention (15) (b)-(b), (a)-(b)-(c) '(a)-(c)-(b), etc. (Please read the precautions on the back before filling this page.) In this method of manufacturing an electron source, it is best to have at least after the semiconductor layer is formed, and after the semiconductor microcrystal is formed, and after the insulating film is formed on the surface of the semiconductor microcrystal. In one of these periods, an annealing treatment in hydrogen is performed. The hydrogen-based irradiation treatment or the hydrogen-based irradiation annealing treatment is performed. In this case, since the uppermost surface of one surface side of the conductive substrate is irradiated with hydrogen radicals, defects existing in the drift layer can be passivated (not dynamic) or reduced, and the electron emission characteristics and reliability of the electron source can be improved. degree. In addition, since the barrier layer or the high-resistance layer between the semiconductor layer and the conductive substrate is reduced, the electron emission efficiency and reliability are improved. [Best Modes for Implementing the Invention] Hereinafter, several embodiments of the present invention will be described in detail. Here, the common components in each embodiment (that is, those having substantially the same structure and function are the same components) are given the same element symbols, and repeated descriptions thereof are omitted. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs on consumer cooperation (Embodiment 1) Hereinafter, Embodiment 1 of the present invention will be described. In Embodiment 1, the conductive substrate (lower electrode) is a single crystal n-type silicon substrate (for example, the resistivity is approximately 0.  0 1 Qcm ~ 〇. (2 Dcm (100) substrate). As shown in FIG. 2, in the electron source 10 (electric field emission type electron source) according to the first embodiment, the main surface of the n-type silicon substrate 1 of the conductive substrate is in accordance with the Chinese National Standard (CNS) A4 standard on the paper scale. (210 × 297 mm) -18- 543209 A7 B7 V. Description of the invention (16) A drift layer 6 (strong electric field drift layer) composed of an oxidized porous polycrystalline silicon layer is formed on the side. Also, an ohmic electrode 2 is formed on the back of the n-type silicon substrate 丨 (Please read the precautions on the back before filling this page). In the first embodiment, the n-type silicon substrate 1 constitutes a conductive substrate. The surface electrode 7 is made of a material having a small work function. The thickness of the surface electrode 7 is set to 0 ^ m. However, the thickness is not limited to this thickness, as long as it is a thickness through which electrons passing through the drift layer 6 can pass. Therefore, the thickness of the surface electrode 7 is only required to be in the range of 3 to 15 nm. The surface electrode 7 is printed by the Intellectual Property of the Ministry of Economic Affairs ^ Employee Consumer Cooperative Society by: The first thin film layer (formed on the drift layer 6 A metal film) and a second thin film layer (a metal film laminated on the first thin film layer). As the material of the first thin film layer on the drift layer 6, for example, chromium, nickel, platinum, titanium, iridium, and the like can be used, and the adhesion between the second thin film layer and the drift layer 6 can be prevented. Diffusion material. As the material of the second thin film layer, a material such as gold having low resistance and high aging stability can be used. In the first embodiment, the first thin film layer is made of chromium (C r). The thickness of the first thin film layer was set to 2 nm. The second thin film layer is made of gold (Au). The thickness of the second thin film layer was set to 8 nm. In the first embodiment, the surface electrode 7 is composed of two metal films, but it may be a metal film of one layer or three or more layers. In the electron source 10, the surface electrode 7 is disposed in a vacuum, and the collector electrode 21 is disposed opposite the surface electrode 7. In addition, a DC voltage Vps was applied to make the surface electrodes 7 pairs of η-type silicon substrates 1 (ohmic electrodes. The paper size of this paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -19- 543209 A7 B7. V. Description of the invention ( 17) (Please read the precautions on the back before filling this page) 2) It can form a positive electrode, and apply a DC voltage vc, so that the collector electrode 21 is opposed to the surface electrode 7 and W can form a positive electrode. As a result, the electrons injected from the η-type silicon substrate 1 will drift in the drift layer 6 and be emitted through the surface electrode 7 (the one-point lock line in the second figure indicates the flow direction of the electrons e-emitted through the surface electrode 7). . The radiated current (electron current) I e flowing between the collector electrode 21 and the surface electrode 7 is a diode current I flowing between the surface electrode 7 and the n-type silicon substrate 1 (ohmic electrode 2). The larger the ps ratio (I e / I ps), the higher the electron emission efficiency. As shown in FIG. 1, the drift layer 6 of Embodiment 1 is composed of at least: a columnar polycrystalline silicon crystal grain 5 1; and a thin silicon oxide film 5 2 formed on the surface of the crystal grain 51; Microcrystalline silicon 6 3 having a plurality of nanometer units between grains 51; and insulation formed on the surface of each microcrystalline silicon 63 and having a film thickness smaller than the crystal grain size of the microcrystalline silicon 63 Film (most silicon oxide film 6 4); etc. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs In summary, in the drift layer 6, the surface of each grain 51 is porous, and the crystalline state is maintained in the center portion of each grain. Here, the thickness of the oxidized sand film 64 formed on the surface of the microcrystalline sand 63 is preferably a film thickness (average free path degree of electrons) that generates a tunneling phenomenon of electrons, and is set to, for example, 1 to 3 nm. Degree (average free path of electrons: the average free path of electrons in Si02 is about 3 nm). For the electron source 10 of Embodiment 1, for example, the following template paper size can be used: Chinese National Standard (CNS) A4 (210X297 mm) -20- 543209 A7 B7 V. Description of the invention (18) Causes electron emission. That is, the surface electrode 7 is placed in a vacuum. Then, between the surface electrode 7 and the η-type silicon substrate 1 (ohmic electrode 2) (please read the precautions on the back before filling this page), use the surface electrode 7 as the positive electrode, and apply a DC voltage ν ps, and A DC voltage V c is applied between the collector electrode 21 and the surface electrode 7 with the collector electrode 21 as a positive electrode. When the DC voltage Vp s reaches a predetermined threshold (critical threshold), electrons e − are injected from the conductive substrate (n-type sand substrate 1) into the drift layer 6 by thermal excitation. On the other hand, most of the electric field applied to the drift layer 6 is located on the silicon oxide film 64. Therefore, the injected electron e- is accelerated by a strong electric field applied to the silicon oxide film 64. In addition, the electrons in the drift layer 6 move the area between the crystal grains 51 toward the surface in the direction of the arrow A in FIG. 1 and pass through the surface electrode 7 to be released in a vacuum. In this way, in the drift layer 6, the electrons injected from the n-type silicon substrate 1 are hardly scattered in the microcrystalline silicon 63, and are accelerated and drifted in a strong electric field applied to the silicon oxide film 64. It is emitted via the surface electrode 7 (ballistic electron emission image). In addition, the heat generated in the drift layer 6 is released through the crystal grains 51. Therefore, there is no phenomenon of electron jumping when the electrons are emitted, and the electrons can be released stably. In addition, the electrons that reach the surface of the printed layer 6 of the intellectual property and employee consumer cooperatives are thermal electrons, which easily pass through the surface electrode 7 and are released in a vacuum. Hereinafter, a manufacturing method of the electron source 10 according to the first embodiment will be described with reference to FIGS. 3A to 3D. First, after the ohmic electrode 2 is formed on the back surface of the n-type silicon substrate 1, an undoped polycrystalline silicon layer 3 (semiconductor layer) is formed on the main surface of the n-type sand substrate 1 to obtain the 3A structure. As for the size of the polycrystalline sand paper, the Chinese National Standard (CNS) A4 (210X297 mm) is applicable-21-543209 A7 B7 V. Description of the invention (19) For the film formation method of layer 3, for example, the CVD method ( (Please read the precautions on the back before filling out this page) LPCVD method, plasma CVD method, catalyst CVD method, etc.), sputtering method, and CSG (Continuous Grain Silicon) method. After the non-doped polycrystalline silicon layer 3 is formed, the polycrystalline silicon layer 3 is made porous during the anodizing process, thereby forming a porous semiconductor layer (porous polycrystalline silicon layer 4). The structure shown in Figure 3B uses an anodizing tank containing an electrolyte during the anodizing process. The electrolyte is made by mixing a 5 5 wt% hydrogen fluoride aqueous solution with ethanol in a 1: 1 manner. A mixed solution is formed. Then, a platinum electrode (not shown) was used as a negative electrode, and an n-type silicon substrate 1 (ohmic electrode 2) was used as a positive electrode. While the polycrystalline silicon layer 3 was irradiated with light, anodization was performed at a constant current. Thereby, a porous polycrystalline silicon layer 4 is formed. The porous polycrystalline silicon layer 4 thus formed includes crystal grains of polycrystalline silicon and microcrystalline silicon. In addition, in Embodiment 1, although the entire polycrystalline silicon layer 3 is made porous, only a part of it may be made porous. Printed by the Ministry of Economic Affairs of the Intellectual Property Co., Ltd./I^M Industrial Consumer Cooperative, after the end of the anodizing process, the porous polycrystalline silicon layer 4 is oxidized by the oxidation process, thereby forming the porous polycrystalline silicon layer The structured drift layer 6 has a structure shown in FIG. 3C. During the oxidation process', the porous polycrystalline sand layer 4 is oxidized by a rapid heating method, thereby forming a drift layer 6 containing crystal grains 5 1, microcrystalline sand 6 3 and each oxide sand film 5 2, 6 4. A lamp annealing device is used in the rapid heating oxidation process. In this case, the inside of the furnace is a 0 2 gas environment, and the substrate temperature is raised from the room temperature to the preliminarily oxidized oxidation temperature (for example, 900) at a predetermined heating rate (for example, 80 ° C / sec). (:) And, only make the substrate temperature and paper size apply the Chinese National Standard (CNS) A4 specification (210x297 mm)--22- 543209 Α7 Β7 V. Description of the invention (20) (Please read the precautions on the back before filling in this Page) to maintain a predetermined oxidation temperature (for example, 1 hour) to perform rapid thermal oxidation (RT0). Then, the substrate temperature is lowered to room temperature. In the first embodiment, the temperature increase rate is set to 8 0 ° C / sec, but can also be set to 80 ° C / sec or more, more preferably set to 150 t / sec or more. The reason why the heating rate is set this way. The reason will be described later. Implementation In the aspect 1, the oxidation process is an insulating film forming process for forming an insulating film (silicon oxide film 6 4) on the surface side of a semiconductor microcrystal (microcrystalline silicon 6 3). After the drift layer 6 is formed, an electron beam is passed through The vapor deposition method The first thin film layer composed of a chromium film in 1) is formed on the drift layer 6. The second thin film layer composed of a metal film (gold film in Embodiment 1) is formed by an electron beam evaporation method. It is formed on the first thin film layer. As a result, the surface electrode 7 composed of the first thin film layer and the second thin film layer is formed, and an electron source 10 having a structure shown in FIG. 3D is obtained. In the first embodiment Although the surface electrode 7 is formed by the electron beam evaporation method, the formation method of the surface electrode 7 is not limited to the electron beam evaporation method. For example, a sputtering method may be used. However, the inventor's research results have found that the conditions of the oxidation process of the rapid heating method, especially the heating rate, affect the characteristics of the electron emission efficiency, insulation withstand voltage, life, etc. Here, the inventor aimed at the electron source 1 The drift layer 6 of 〇 is analyzed and evaluated (the heating rate of the rapid heating method is set to 80 ° C / sec). Specifically, the structure is near the surface of the drift layer 6 according to the photoluminescence method (LP). Evaluation, and based on profile T E Μ (Applicable to China National Standard (CNS) A4 specification (210 × 297 mm) through this paper size) -23- 543209 A7 B7 V. Description of the invention (21) (Please read the precautions on the back before filling this page) Type electron microscope The structure observation and elemental analysis of the surface layer near the drift layer, and the measurement of the depth distribution of the elements present in the drift layer according to the X-ray photoelectron spectroscopy (X ps method). Also, the electron of the comparative example For the source (drift layer), the same analysis and evaluation were performed. For the electron source of the comparative example, the heating rate of the rapid heating method was set to be lower than 80 ° C / sec, that is, set to 20 ° C / sec. . As a result, in the comparative example in which the heating rate was set to 20 ° C / sec, a si 2 film was formed in the drift layer at a depth from the surface (the interface with the surface electrode 7) to 100 nm. , But no microcrystalline silicon exists. On the other hand, in the drift layer 6 of the electron source 10 with the heating rate set to a relatively high speed (80 ° C / sec), microcrystalline silicon 6 is also formed in a region from the surface to a depth of 100 nm. . Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs The results of each analysis and evaluation are described below. First, the observation results and elemental analysis results of the cross-section TEM (transmission electron microscope) on the surface near structure of the drift layer 6 of the electron source 10 of the first embodiment and the drift layer of the comparative example will be described. According to the evaluation of the cross section TEM, in the drift layer 6 of the electron source 10, columnar grains of polycrystalline silicon and microcrystalline silicon in nanometer units were confirmed. In contrast, in the drift layer of the comparative example, a Si02 film was formed in the entire area from the surface to a depth of 100 nm, while the columnar grains of polycrystalline silicon were formed only at a thickness of less than 1000 nm. Go deeper. Next, the results of structural evaluation of the vicinity of the drift layer surface of the PL method will be described with reference to FIG. 4. Figure 4 shows the laser irradiation wavelength from He-Cd to the Chinese paper standard (CNS) M specification (2 （〇χ297 mm) ~ 543209 Α7 Β7 5. Description of the invention (22) (Please read first (Notes on the back page, please fill in this page again.) 3 2 5 nm light to measure the luminescence spectrum. A in Figure 4 shows the luminescence spectrum of the drift layer 6 of Embodiment 1, and b is the drift layer of the comparative example. Luminescence spectrum. The length of the light irradiated from the He-Cd laser into the drift layer 6 is within 100 nm of the surface of the drift layer 6. Therefore, each of the luminescence spectra of a and b in FIG. The light emission spectrum in the shallow area near the surface. Generally, the light emission from the silicon oxide film is called the F band, and it has a peak chirp around 4 300 nm to 5 40 nm. In addition, the light emission from microcrystalline silicon is It is called an S band, and has a peak chirp near 650 nm to 800 nm. From Fig. 4, it can be clearly observed that the emission peak chirped from microcrystalline silicon 63 and silicon oxide in the first embodiment are clearly observed. The emission peak of the film is relatively small. In contrast, in the drift layer of the comparative example, only the emission from the silicon oxide film The peaks are observed. That is, in the area from the surface of the drift layer 6 of the comparative example to a depth of 100 nm, there is almost no microcrystalline sand, and most or all of them form an oxide sand film. This result and section The analysis results of TE Μ are consistent. Printed by the Intellectual Property of the Ministry of Economic Affairs and the Consumer Consumption Cooperative. Secondly, while referring to Fig. 5, explain the measurement results of the depth distribution of the elements present in the drift layer of the XPS method. The horizontal axis indicates the surface depth from the drift layer 6. The vertical axis in FIG. 5 indicates the atomic concentration. A1, a2, and a3 in FIG. 5 indicate the measurement results of the drift layer 6 in the first embodiment. In addition, b 1, b 2, and b 3 are the measurement results of the drift layer in the comparative example. Here, a 1 and b 1 represent the depth distribution of S i〇2, and a 2 and b 2 represent The depth distribution of Si, a3 and b3 are the depth distribution of Si0x. It can be clearly seen from Figure 5 that in the drift layer 6 of Embodiment 1, the paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297). Mm) -25- 543209 A7 B7 V. Invention Ming (23) (Please read the precautions on the back before filling in this page) 'S i and S i〇2 were observed in an area shallower than the surface depth of 100 nm. In contrast, in the comparative example, In the drift layer, S i is not observed in a region shallower than the surface depth of 100 nm, but only 5 i ◦ 2. This result is consistent with the analysis result of the profile τ E Μ. From the above each The analysis results show that (as shown in Figs. 6A and 6B) 'In the drift layer 6 of Embodiment 1, the surface of the drift layer 6 also includes a microcrystalline silicon 6 having a silicon oxide film 6 4 formed on the surface. 3. In addition, the electrons e − injected into the drift layer 6 will be accelerated by a strong electric field applied to the silicon oxide film 64 and will drift to the arrow in FIG. 6A without almost colliding with the microcrystalline silicon 63. Direction (to the right), and reaches the surface of the drift layer 6, passes through the surface electrode 7 and is released in a vacuum. (A dot-lock line in Fig. 6A indicates the direction of electron e-). Further, "PPS" described in the upper part of Fig. 6A indicates the drift layer 6, "Me t a 1" indicates the surface electrode 7, and "Vacuum" indicates vacuum. Fig. 6B is a band diagram for explaining the electron emission principle. “Si〇2” in FIG. 6B indicates a silicon oxide film 64, and “// c — Si” indicates microcrystalline silicon 6 3 printed in nanometer units printed by an employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and “EF μ "" Indicates the Fermi level of the surface electrode 7, and "Eva" indicates the vacuum level. On the other hand, as shown in FIG. 7, in the drift layer of the comparative example (hereinafter referred to as “drift layer 6 /”), the closer to the surface of the drift layer 6 >, the larger the thickness of the silicon oxide film 64 is. Large, and the resulting microcrystalline silicon 6 3 will be destroyed. In addition, microcrystalline silicon 63 does not exist near the surface. Therefore, a part of the electrons e-injected into the drift layer 6 > will be scattered or absorbed in a film thickness (average free path degree of electrons) which is thicker than the tunneling phenomenon of the electrons. This paper is applicable to China National Standard (CNS) A4 specification (210X 297 mm) -26- 543209 A7 B7 V. Description of the invention (24) The oxide sand film 6 4 will reduce the electron emission efficiency, or the insulation withstand voltage and life will be reduced. (Please read the precautions on the back before filling out this page) The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed on the drift layer 6 of Embodiment 1, and even microcrystalline silicon 6 3 exists near the surface. In contrast, in the In the drift layer 6 > of the comparative example, the microcrystalline silicon 63 was destroyed near the surface, and the reason is as follows. That is, in the first embodiment, during the oxidation process after the anodizing process, as shown in FIG. 8A, oxygen molecules 80 will reach around the microcrystalline silicon 6 3. At this moment, since the heating rate is relatively high (80 ° C / s_ec), the silicon oxide film 64 is formed on the surface side of the microcrystalline silicon 63 formed by the anode oxidation in a short time. Therefore, the diffusion of the oxygen atoms 8 1 to the center of the microcrystalline silicon 6 3 is prevented, and a silicon oxide film 6 4 having a film thickness (average free path of the electrons) of the electron tunneling phenomenon is formed. . In contrast, in the comparative example, during the oxidation process after the anodic oxidation process, as shown in FIG. 8A, oxygen molecules 80 will also reach around the microcrystalline silicon 63. However, since the heating rate is relatively low (20 ° C / s-ec), the oxygen atom 81 will diffuse to the center of the microcrystalline silicon 6 3 formed by anodization, resulting in the microcrystalline silicon 6 3 The whole will be oxidized. This is the reason why the microcrystalline silicon 63 was destroyed.

第9圖是表示升溫速度爲8 0°C/s_ec， 1 6 0 °C / s _ e c及2 0 °C / s — e c時之各個電子放出效率的時 效變化。第9圖的縱軸是表示電子放出效率，橫軸是表示 經過時間。第9圖中的a是表示升溫速度爲8 0 °C / S-ec時，b是表示升溫速度爲20°C/s ec時，c 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇X；297公釐） -27- 543209 Α7 __ Β7 五、發明説明（25) (請先閱讀背面之注意事項再填寫本頁) 疋表示升溫速度爲1 6 0°C/s_e C時。由第9圖可明確 ―知，就實施形態1而言，與比較例相較下，電子放出效 率會變高，電子放出效率的時效變化會變小。藉此，壽命 會變長。並且，藉由升溫速度的高速化（由8 s—e c提升至1 6 0°C/s_e c )，電子放出效率會變 得更高。 第9圖之電子放出效率的時效變化，可以指數函數衰 減的函數（以下，稱爲「衰減函數」）來修正時效時間。 亦即，若電子放出效率的初期値（以下，稱爲「初期電子 放出效率」）爲7/ 0，時定数爲r，比例係數（線形係數） 爲r，經過時間爲t，則任意經過時間t的電子放出效率 β可形成近似於下式1者。並且，時定数r的値越大，電 子源的壽命會越長。 C = ?7 0 · e X p ((— t/r)·^) ••式 1 經濟部智慧財產局員工消費合作社印製 第1 0圖是表示初期電子放出效率與時定数r (以 減數函數來修正求得）的關係。第1 〇圖的縱軸爲初期電 子放出效率；？0，橫軸爲時定数r。第1〇圖中的a是表示 升溫速度爲8 0°C/s-e c時，b是表示升溫速度爲2 0 °C/s_ec時，c是表示升溫速度爲i6 0°C/s_ec 時。由第10圖可知，隨著升溫速度的提高，初期電子放 出效率7? 0及時定数τ會變大。亦即，隨著升溫速度的提高 ，可提高電子放出效率及謀求長壽命化。在此，若以初期 電子放出效率及時定数r的乘積βΟ· r來進行電子源 的特性評價，則0 · τ的値越大，電子源的特性越佳。 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） -28- 543209 A7 B7 五、發明説明（26) (請先閲讀背面之注意事項再填寫本頁) β〇· r的値在b時爲0 · 092，在a時爲5.2，在C時 爲2 1 · 8。在使升溫速度由2 Ot/s-e c提升至80 °C/S_eC時，77〇.1的値會比2〇°(：/3一6(：時還要 大上5 0倍。因此，若將升溫速度設定成8 0°C/s_e c 以上，則與升溫速度爲2 0 °C / s _ e c時相較下，可提升 電子放出效率及謀求長壽命化。甚至，若將升溫速度設定 成1 5 0 °C / s _ e c以上，則更能提升電子放出效率及謀 求長壽命化。通常，升溫速度是受限於急速加熱法中所使 用的製造裝置（例如，燈退火）的性能，目前升溫速度可 高速化至400°C/s_ec程度。 以上，若利用實施形態1之電子源1 0的製造方法， 則可使飄移層6中的絕緣膜（氧化矽膜6 4 )的厚度形成 會產生電子的穿隧現象之膜厚（電子的平均自由行程程度 )。因此，可減少在各氧化矽膜6 4的電子散亂，且可縮 小在飄移層6中之氧化矽膜6 4的厚度不均一。藉此，絕 緣耐壓及壽命的設計會更加容易。進而能夠謀求絕緣耐壓 的提升及長壽命化，以及謀求電子放出效率的提升。 經濟部智慧財產^員工消費合作社印製 (實施形態2 ) 以下，說明本發明之實施形態2。在實施形態1中， 導電性基板是使用：在由玻璃基板（例如石英玻璃基板） 所構成的絕緣性基板的一表面上設置由金屬膜（例如鎢膜 )所構成的導電性層者。 如第1 1圖所示，在實施形態2的電子源1 0中，在 本纸張尺度適用中國國家標準（CNS) A4規格（2i〇x297公釐） 543209 A7 B7 五、發明説明（27) 〔請先閱讀背面之注意事項再填寫本頁} 絕緣性基板1 1上的導電性層1 2上形成有由氧化後的多 孔質多結晶矽層所構成的飄移層6。並且，在飄移層6上 形成有表面電極7。表面電極7的構成是與實施形態1相 同。 經濟部智慧財產笱員工消費合作社印製 在使電子從電子源1 〇放出的程序是與第4 0圖所示 之以往的電子源1 〇時，是以能夠對向於表面電極7之方 式來配設集極電極2 1 ，使表面電極7與集極電極2 1之 間形成真空狀態。又，以表面電極7能夠對導電性層1 2 形成正極（高電位）正極之方式，在表面電極7與導電性 層1 2之間施加直流電壓V p s ，且以集極電極2 1能夠 對表面電極7形成正極（高電位）之方式，在集極電極 2 1與表面電極7之間施加直流電壓V c。只要適當的設 定各直流電壓V p s ，V c，則由導電性層1 2注入的電 子便會飄移於飄移層6內，經由表面電極7而釋放出（第 1 1圖中的一點鎖線是表示通過表面電極7而放出之電子 e —的流向）。並且，到達飄移層6表面的電子爲熱電子， 容易穿過表面電極7而放出於真空中。而且，實施形態2 的電子源1 0亦與實施形態1的電子源1 0同樣的，放射 電流I e對二極體電流I p s的比率（I e / I p s )越 大，電子放出效率越高。 飄移層6的構成及機能與實施形態1相同。亦即，飄 移層6是至少由：晶粒5 1 ，氧化矽膜5 2，多數的微結 晶砂6 3 ，及多數的氧化砂膜6 4所構成（參照第1圖） 。並且，在飄移層6中，各晶粒5 1的表面爲多孔質化， 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -30- 543209 A7 B7 五、發明説明（28) (請先閱讀背面之注意事項再填寫本頁) 在各晶粒的中心部份會維持結晶狀態。在此，氧化矽膜 6 4的厚度是設定成會產生電子的穿隧現象之膜厚（電子 的平均自由行程程度）’例如設定成1〜3 n m的程度。 實施形態2的電子源1 0可以和實施形態1的電子源 1 0同樣的模式來引起電子放出。亦即，在表面電極7與 下部電極1 2之間，以表面電極7作爲正極來施加直流電 壓Vp s ，且在集極電極2 1與表面電極7之間，以集極 電極2 1作爲正極來施加直流電壓V c ，藉此，從下部電 極1 2藉由熱激勵而注入飄移層6的電子e —會飄移，穿過 表面電極7，放出於真空中。 此外，在以實施形態2的電子源1 0作爲顯示器的電 子源用時，只要適當的形成下部電極（導電性基板）及表 面電極7的圖案即可。 以下，一邊參照第1 2A〜1 2D圖，一邊說明實施 形態2之電子源1 0的製造方法。 經濟部智慧財產苟員工消費合作社印製 首先，在絕緣性基板1 1的一表面側，藉由濺鍍法等 來形成由金屬膜（例如，鎢膜）所構成的導電性層1 2， 而製成導電性基板。然後，在導電性基板的主表面側（在 此爲導電性層1 2上）形成無摻雜質的多結晶矽層3 (半 導體層），而取得第1 2 A圖所示的構造。就多結晶矽層 3的成膜方法而言，例如可使用：C V D法（L P C V D 法，電漿C V D法，觸媒C V D法等），濺鍍法，及 C S G ( Continuous Grain Silicon)法等。 在形成無摻雜質的多結晶矽層3之後，在陽極氧化處 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -31 - 543209 A7 B7 五、發明説明（29) (請先閱讀背面之注意事項再填寫本頁) 理過程中使多結晶矽層3多孔質化，藉此來形成多孔質多 結晶矽層4 (多孔質半導體層），取得第1 2 B圖所示的 構造。並且，在陽極氧化處理過程中，是使用放進有電解 液的陽極氧化處理槽，該電解液是由：以1比1方式來混 合5 5 w t %的氟化氫水溶液與乙醇之混合液所形成。然 後，以白金電極（圖中未示）作爲負極，及以導電性層 1 2作爲正極，一邊對多結晶砂層3進行光照射，一邊以 定電流來進行陽極氧化處理。藉此，多孔質多結晶矽層4 會被形成。多孔質多結晶矽層4是含多結晶矽的晶粒及微 結晶矽。而且，在實施形態2中，雖是使多結晶矽層3的 全部形成多孔質化，但亦可使其一部份形成多孔質化。 經濟部智慧財產苟W工消費合作社印製 在陽極氧化處理過程終了後，利用氧化過程來氧化多 孔質多結晶矽層4，藉此來形成由氧化後的多孔質多結晶 矽層所構成的飄移層6，取得第1 2 C圖所示的構造。在 氧化過程中，是以急速加熱法來氧化多孔質多結晶矽層4 ，藉此來形成含晶粒5 1，微結晶矽6 3及各氧化矽膜 5 2，6 4的飄移層6。在急速加熱法的氧化過程中，與 實施形態1的情況時同樣的，是使用燈退火裝置，在爐內 爲〇2氣體環境中，以規定的升溫速度（例如，8 0 °C / s e c )來使基板溫度從室溫上升至預定的氧化溫度（例 如9 0 0 °C )。並且，只使基板溫度維持預定的氧化溫度 (例如，1小時），而來進行急速熱氧化（R T〇）。然 後，使基板溫度下降至室溫。在實施形態2中，雖是將升 溫速度設定成8 0 °C / s e c ，但亦可與實施形態1同樣 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -32- 543209 A7 B7 ___ 五、發明説明（3〇) (請先閲讀背面之注意事項再填寫本頁) 的，設定成8 0 °C / s e c以上’更理想是設定成1 5 0 °C / s e c以上。實施形態2亦與實施形態1的情況時同 樣的，氧化過程是供以在半導體微結晶（微結晶矽6 3 ) 的表面側形成絕緣膜（氧化矽膜6 4 )之絕緣膜形成過程 〇 在形成飄移層6之後，藉由電子束蒸鍍法來將由金屬 膜（在實施形態2中爲鉻膜）所構成的第1薄膜層形成於 飄移層6上。又，藉由電子束蒸鍍法來將由金屬膜（在實 施形態2中爲金膜）所構成的第2薄膜層形成於第1薄膜 層上。藉此，由第1薄膜層與第2薄膜層所構成的表面電 極7會被形成，取得第1 2 D圖所示構造的電子源1 0。 在實施形態2中，雖是藉由電子束蒸鑛法來形成表面電極 7，但表面電極7的形成方法並非只限於電子束蒸鍍法， 例如亦可使用灑鑛法。 經濟部智慧財產^員工消費合作社印製 若利用實施形態2之電子源1 0的製造方法，則可使 飄移層6中的絕緣膜（氧化矽膜6 4 )的厚度形成會產生 電子的穿隧現象之膜厚（電子的平均自由行程程度）。因 此，可減少在各氧化矽膜6 4的電子散亂，且可縮小在飄 移層6中之氧化矽膜6 4的厚度不均一。藉此，絕緣耐壓 及壽命的設計會更加容易。進而能夠謀求絕緣耐壓的提升 及長壽命化，以及謀求電子放出效率的提升。 就實施形態1 ，2而言，雖是以氧化後的多孔質多結 晶矽層來構成飄移層6，但亦可以氮化後的多孔質多結晶 矽層，或以氧化•氮化後的多孔質多結晶矽層來構成飄移 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -33- 543209 Α7 Β7 五、發明説明（31) 層6。或者以氧化，氮化或氧化•氮化後的其他多孔質半 導體層來構成。 (請先閱讀背面之注意事項再填寫本頁) 在以氮化後的多孔質多結晶矽層來形成飄移層6時， 只要以氮化過程（絕緣膜形成過程；利用N Η 3氣體來藉由 升溫速度設定成與各實施形態同樣的急速加熱法進行氮化 多孔質多結晶矽層4的過程）來取代氧化過程（絕緣膜形 成過程；利用0 2氣體來藉由急速加熱法進行氧化多孔質多 結晶矽層4的過程）即可。此情況，第1圖的各氧化矽膜 5 2，6 4皆會形成氮化矽膜。 在以氧化·氮化後的多孔質多結晶矽層來形成飄移層 6時，只要以氧化•氮化過程（絕緣膜形成過程；利用〇2 氣體與ΝΗ3氣體，Ν〇氣體，ν2氣體等含氮的混合氣體 來藉由升溫速度設定成與各實施形態同樣的急速加熱法進 行氧化•氮化多孔質多結晶矽層4的過程）來取代氧化過 程（藉由急速加熱法來進行氧化多孔質多結晶矽層4的過 程）即可。此情況，第1圖的各氧化矽膜5 2，6 4皆會 形成氧化•氮化砂膜。 經濟部智慧財產笱員工消費合作社印製 並且，在以氧化·氮化後的多孔質多結晶矽層來形成 飄移層6時，亦可使用下述氧化膜形成過程及氮化處理過 程來作爲形成絕緣膜（由氧化氮化矽膜所構成）的絕緣膜 形成過程。 該氧化膜形成過程是藉由急速加熱法（將升溫速度設 定成與各實施形態相同），在微結晶矽6 3的表面側形成 氧化膜（氧化矽膜）；及 -34- 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐） 543209 Α7 Β7 五、發明説明（32) 該氮化處理過程是將氧化膜形成過程中所形成的氧化 矽膜予以氮化後形成氧化·氮化膜（氧化氮化矽膜）。 (請先閲讀背面之注意事項再填寫本頁) 而且，在使用氮化矽膜或氧化氮化矽膜來作爲形成於 半導體微結晶（微結晶矽6 3 )的表面側的絕緣膜時，與 使用氧化矽膜相較下，可提高絕緣耐壓。同樣的，在使用 氧化矽膜與氮化矽膜的層疊膜來作爲絕緣膜時，與使用氧 化矽膜相較下，亦可提高絕緣耐壓。 在實施形態1 ，2之電子源1 0的各製造方法的飄移 層6形成後，在表面電極7形成前，可藉由進行補償飄移 層6中的缺陷的成形（forming)處理來補償絕緣膜的缺陷。 藉此’可更進一步提升絕緣耐壓，以及謀求長壽命化。該 成形處理只要在至少由Η 2與N 2所構成的混合氣體中使基 板溫度上升至預定的溫度（例如，4 5 0 °C )即可。藉由 如此的成形處理，可防止絕緣膜的厚度變得比成形處理前 還要厚，及防止雜質導入。而且，與急速加熱法的基板溫 度相較下，可以較低的溫度來補償絕緣膜的缺陷。 經濟部智慧財產场員工消費合作社印製 在實施形態1 ，2的絕緣膜形成過程中，雖是使用急 速加熱法來形成絕緣膜，但亦可利用電氣化學性的方法來 形成絕緣膜（氧化矽膜6 4 )。此情況，只要使用放入電 解質溶液（例如，1 m ο 1的Η 2 S〇4，1 m ο 1的 HN〇3，王水等）的氧化處理槽，而以白金電極（圖中未 示）作爲負極，以及以下部電極（在實施形態1中爲n型 矽基板，在實施形態2中爲導電性層1 2 )作爲正極，使 定電流流動，而來氧化多孔質多結晶矽層4即可。藉此， 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） ' -35 - 543209 Α7 Β7 五、發明説明（33) 可开々成含晶粒5 1 ’微結晶砂6 3，及各氧化砂膜5 2， (請先閲讀背面之注意事項再填寫本頁) 6 4的飄移層6。當然，藉由電氣化學性的方法所形成的 絕緣膜’亦可爲氮化矽膜等的氮化膜或氧化氮化矽膜等的 氧化氮化膜。 在如此藉由電氣化學性的方法來形成絕緣膜時，雖可 形成產生電子的穿隧現象的厚度（電子的平均自由行程程 度）之絕緣膜，且微結晶砂6 3不會被破壞，但與藉由急 速加熱法（將升溫速度設定成8 0 °C / s e c )來形成絕 緣膜者相較下，電子放出率低，且壽命短。又，以電氣化 學性的方法來形成的氧化矽膜與藉由急速加熱法來形成的 氧化矽膜相較下，含多量的水分。 經濟部智慧財產笱員工消費合作社印製 因此，在形成各絕緣膜的絕緣膜形成過程中，若在電 氣化學性的形成絕緣膜之後，藉由急速加熱法來形成絕緣 膜，則可去除氧化矽膜的水分，且能夠提升電子放出特性 。換g之’在藉由急速加熱法來形成絕緣膜之前，只要利 用電氣化學性的方法來形成絕緣膜，便可確實地防止急速 加熱法造成微結晶矽的破壞，實現一種電子放出效率及絕 緣耐壓高且壽命長的電子源1 〇。 (實施形態3 ) 以下，說明本發明之實施形態3。實施形態3的電子 源具有：由氧化矽膜所構成的絕緣膜。在實施形態3的電 子源中，導電性基板是使用：阻抗率較接近導體的阻抗率 之單結晶的η型矽基板（例如，阻抗率約爲 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐） -36- 543209 A7 B7 五、發明説明（34) O.OlQcm 〜〇·〇2Ω(：πι 的（1〇〇)基板）。 (請先閲讀背面之注意事項再填寫本頁) 如第1 3圖所示，實施形態3的電子源1 〇是在導電 性基板之η型砂基板1的主表面側形成有：由氧化後的多 孔質多結晶矽層所構成的飄移層6。並且，在飄移層6上 形成有表面電極7。在η型矽基板1的背面形成有歐姆電 極2。以η型矽基板1及歐姆電極2來構成下部電極1 2 。因此’表面電極7會對向於下部電極1 2，飄移層6會 介於下部電極1 2與表面電極7之間。並且，多孔質多結 晶矽層會構成多孔質半導體層。 表面電極7的材料是使用功函數較小的材料。表面電 極7的厚度是設定成1 〇 n m。但，厚度並非只限於該値 ，只要爲通過飄移層6的電子可穿過之厚度即可。因此， 表面電極7的厚度只要設定於3〜1 5 nm的程度範圍即 可。 經濟部智慧財產笱員工消費合作社印製 飄移層6的構成及機能與實施形態1相同。亦即，飄 移層6是至少由：晶粒5 1 ，氧化矽膜5 2，多數的微結 晶矽6 3 ，及多數的氧化矽膜6 4所構成（參照第1圖） 。並且，在飄移層6中，各晶粒5 1的表面爲多孔質化， 在各晶粒的中心部份會維持結晶狀態。在此，氧化矽膜 6 4的厚度是設定成會產生電子的穿隧現象之膜厚（電子 的平均自由行程程度），例如設定成1〜3 n m的程度。 如第1 4圖所示，實施形態3的電子源1 0可以和實 施形態1的電子源1 0同樣的模式來引起電子放出。亦即 ，在表面電極7與下部電極1 2之間，以表面電極7作爲 本紙張尺度適用中國國家標準（CNS ) A4規格（210><297公釐） -37 - 543209 A7 B7 五、發明説明（35) (請先閱讀背面之注意事項再填寫本頁) 正極來施加直流電壓V p s ，且在集極電極2 1與表面電 極7之間，以集極電極2 1作爲正極來施加直流電壓v c ’藉此，從下部電極1 2藉由熱激勵而注入飄移層6的電 子e —會飄移，穿過表面電極7，放出於真空中。 以下’一邊參照弟1 5 A〜1 5 D圖，一邊說明實施 形態3之電子源1 〇的製造方法。 首先’在η型矽基板1的背面形成歐姆電極2。然後 ’在η型矽基板1的主表面上形成無摻雜質的多結晶砂層 3 (+導體層），而取得弟1 5 Α圖所不的構造。就多結 晶矽層3的成膜方法而言，例如可使用：C V D法（ LPCVD法，電漿CVD法，觸媒CVD法等），灘鍍 法’及 C S G ( Continuous Grain Silicon)法等。 在形成無摻雜質的多結晶矽層3之後，在陽極氧化處 理過程中使多結晶矽層3 (形成陽極氧化的對象之半導體 經濟部智慧財產局員工消費合作社印製 層）多孔質化，藉此來形成多孔質多結晶矽層4，取得第 1 5 B圖所示的構造。並且，在陽極氧化處理過程中所形 成的多孔質多結晶矽層4是包含：多數的多結晶矽的晶粒 ，及多數的微結晶矽。在陽極氧化處理過程中，是使用放 進有電解液的陽極氧化處理槽，該電解液是由：以1比1 方式來混合5 5 w t %的氟化氫水溶液與乙醇之混合液所 形成。然後，一邊利用由5 0 0 W的鎢絲燈所構成的光源 來對多結晶矽層3的表面進行光照射，一邊從電源（圖中 未示）來使定電流（亦即電流密度一定）流動於下部電極 1 2與陰極（由白金電極所構成）之間。藉此，可從多結 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -38- 543209 Α7 Β7 五、發明説明（36) 晶矽層3的主表面到η型矽基板1的深度爲止，使多結晶 矽層3多孔質化。 (請先閲讀背面之注意事項再填寫本頁) 在陽極氧化處理過程終了後，在多孔質多結晶砂層4 中所含的半導體結晶（各晶粒及各微結晶矽）的表面上形 成絕緣膜的氧化矽膜5 2，6 4。藉此，形成含晶粒5 1 ，微結晶砂6 3 ，及各氧化砂膜5 2，6 4之飄移層6， 取得第1 5 C圖所不的構造。在形成絕緣膜時，會在陽極 氧化處理過程終了後，進行利用乙醇的洗淨，然後使用放 進有1 Μ硫酸水溶液的處理槽，從電源（圖中未示）來使 定電壓施加於下部電極1 2與陰極（由白金電極所構成） 之間。藉此，利用電氣化學性的方法來將基礎的絕緣性薄 膜（氧化矽膜）形成於各晶粒及各微結晶矽的表面上。 經濟部智慧財產^7員工消費合作社印製 其次，進行第1 6圖所示的熱處理過程，取得所期望 的絕緣膜（氧化矽膜5 2，6 4 )。如第1 6圖所示，在 熱處理過程中，以絕緣性薄膜中所含的水分能夠在不會沸 騰下去除之方式而設定的第1設定溫度Τ1及升溫速度來 進行第1熱處理。然後，以比第1設定溫度Τ 1還要高， 且絕緣性薄膜的構造能夠趨於緩和之方式而設定的第2設 定溫度Τ 2來進行第2熱處理。藉此，取得所期望的絕緣 薄膜。 在熱處理過程中，雖是例如使用燈退火裝置，但即使 利用通常的爐亦無妨。第1熱處理是在氧氣的環境中（亦 即含氧化類的環境中）進行。第1設定溫度Τ 1是例如設 定成4 5 0 t，熱處理時間Η 2是例如設定成1小時。並 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） -39- 543209 A7 B7 五、發明説明（37) (請先閱讀背面之注意事項再填寫本頁) 且，第2熱處理是在氧氣的環境中（亦即含氧化類的環境 中）進行。第2設定溫度T 2是例如設定成9 0 0 °C，熱 處理時間Η 4是例如設定成2 0分。在第3實施形態中， 第2熱處理是使用急速熱處理法。在此，使基板溫度從第 1設定溫度Τ 1上升至第2設定溫度Τ 2爲止的升溫期間 Η 3的升溫速度是設定成1 5 0 °C / s e c。並且，升溫 期間Η 3的升溫速度是比從室溫上升至第1設定溫度爲止 的升溫期間Η 1的升溫速度還要快。 第1設定溫度Τ 1雖是設定於1 〇 〇 °C〜7 0 0 °C的 範圍即可，但最理想是設定於3 0 0 °C以上。第2設定溫 度T 2是設定於6 0 0 °C以上的範圍即可。升溫期間η 3 的升溫速度雖是設定成2 0°C/s e c以上即可，但最好 是設定成1 5 0 °C / s e c以上。由於升溫期間Η 1的升 溫速度是以絕緣性薄膜中所含的水分不會沸騰之方式而設 疋’因此最好是設定於2 0 C/ s e c以下。 經濟部智慧財產局員工消費合作社印製 在形成飄移層6後，藉由蒸鍍法等來形成由金屬材料 (例如，金）所構成的表面電極7，取得第1 5 D圖所示 構造的電子源1 0。並且，在實施形態3中，雖是藉由蒸 鍍法來形成表面電極7，但表面電極7的形成方法並非只 限於蒸鍍法，例如亦可使用濺鍍法。 在形成絕緣膜（氧化矽膜5 2，6 4 )時，首先是使 用電氣化學性的方法，在半導體結晶（多孔質多結晶矽層 4中所含的多數個晶粒及多數個微結晶矽）的表面上形成 基礎的絕緣性薄膜。藉此，即使半導體結晶爲奈米單位的 -40- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 543209 A7 B7 五、發明説明（38) (請先閲讀背面之注意事項再填寫本頁) 微結晶政（半導體微結晶）之類的小尺寸的半導體結晶， 照樣可以形成不會破壞微結晶矽的絕緣性薄膜。又，以絕 緣性薄膜中所含的水分能夠在不會沸騰下去除之方式而設 定的第1設定溫度τ1及升溫速度來進行第1熱處理。然 後，以比第1設定溫度T 1還要高，且絕緣性薄膜的構造 能夠趨於緩和之方式而設定的第2設定溫度T 2來進行第 2熱處理。藉此，取得所期望的絕緣薄膜（氧化矽膜5 2 ，6 4 )。亦即，一方面可防止因絕緣性薄膜中的水分沸 騰而造成絕緣膜的絕緣耐壓降低，另一方面可充分減少絕 緣性薄膜中所含的水分（與只使用電氣化學性的方法來形 成的絕緣膜相較下）。並且，可藉由構造緩和來緩和對電 氣特性造成不良影響的缺陷及應變等。藉此，而能夠形成 絕緣耐壓高且壽命長的絕緣膜。 就利用如此的製造方法而製成的電子源1 〇而言，與 只使用急速熱氧化法來形成飄移層6的氧化矽膜5 2， 經濟部智慧財產局員工消費合作社印製 6 4時相較下，可形成不會破壞微結晶矽6 3的氧化矽膜 5 2，6 4。因此，可提升電子放出效率，絕緣耐壓，及 壽命等。並且，與只使用電氣化學性的方法來形成飄移層 6的氧化矽膜5 2，6 4時相較下，可以降低氧化矽膜 5 2，6 4中的水分及應變，以及能夠提高絕緣耐壓及壽 命。 在上述製造方法中，第1設定溫度T 1是被設定成 7 0 0 °C以下。因此，即使半導體結晶（晶粒及微結晶矽 )形成於比石英玻璃基板還要便宜且耐熱溫度低的玻璃基 本紙張尺度適用中國國家榡準（CNS ) A4規格（210X 297公釐） -41 - 543209 A7 B7 五、發明説明（39) (請先閱讀背面之注意事項再填寫本頁) 板的表面側時，還是可以拉長第1熱處理的熱處理時間 Η 2。藉此，可以更爲減少第1熱處理後的殘留水分。又 ，由於第2設定溫度Τ 2是被設定於6 0 0 t以上的溫度 範圍，因此可比第1熱處理後的絕緣性薄膜還要能夠降低 絕緣膜（氧化矽膜5 2，6 4 )中的殘留水分。又，因爲 是藉由急速熱處理法來進行第2熱處理，所以能夠以短時 間來升溫至第2設定溫度T 2。因此，可降低微結晶矽中 所產生的損傷。 經濟部智慧財產^員工消費合作社印製 又，由於第1熱處理是在含氧化類的環境中進行，因 此可期望補償因絕緣性薄膜中的水分脫離所引起的缺陷等 。並且，在使絕緣性薄膜中的水分脫離時，並非只限於熱 能，亦可利用與氧氣結合的能量，或反應能量。藉此，可 更爲減少第1熱處理後的殘留水分。又，由於第2熱處理 是在含氧化類的環境中進行，因此可藉由第2熱處理在絕 緣性薄膜的表面側形成薄薄的熱氧化膜，提高絕緣膜的絕 緣耐壓。並且，實施形態3是在第1熱處理後進行第2熱 處理。但，亦可不進行第2熱處理，而只進行第1熱處理 。此情況與以往相較，同樣可提高絕緣耐壓及壽命。 又’亦可在真空中或惰性氣體的環境中進行第1熱處 理。若能在真空中進行第1熱處理，則可將第1設定溫度 T 1設定成較低。亦即，在真空中進行第1熱處理，可以 較低的溫度來脫離絕緣性薄膜中所含的水分，因此可將第 1設定溫度T 1設定成較低。若在惰性氣體的環境中進行 第1熱處理，則不必使用真空裝置來進行第1熱處理。因 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -42- 543209 A7 ____ B7 五、發明説明（4〇) 此’可以使用比真空裝置還要便宜的裝置，且能夠提高進 行第1熱處理的裝置之處理能力。 (請先閱讀背面之注意事項再填寫本頁) 又’亦可在惰性氣體的環境中，或者含氮化類的環境 中進行第2熱處理。若在惰性氣體的環境中進行第2熱處 理，則不必使用真空裝置來進行第2熱處理。因此，可以 使用比真空裝置還要便宜的裝置，且能夠提高進行第2熱 處理的裝置之處理能力。又，由於絕緣性薄膜的膜厚不會 因第2熱處理而變化，只要在電氣化學性的方法條件下便 通控制絕緣膜的膜厚。因此，可提高絕緣膜的膜厚控制性 。另一方面，若在含氮化類的環境中進行第2熱處理，則 可藉由第2熱處理在絕緣性薄膜的表面側形成薄薄的氧化 氮膜。藉此，可提高絕緣膜的絕緣耐壓，且可因絕緣膜中 的缺陷密度降低而提升電氣特性。 經濟部智慧財產苟員工消費合作社印製 在形成絕緣膜時，只要使用具備：薄膜形成裝置，第 1熱處理裝置，及第2熱處理裝置之絕緣膜的形成裝置即 可。在此，薄膜形成裝置會在半導體結晶的表面上電氣化 學性的形成絕緣性薄膜。第1熱處理裝置是以絕緣性薄膜 中所含的水分能夠在不會沸騰下去除之方式而設定的第1 設定溫度τ 1及升溫速度來進行第1熱處理。第2熱處理 裝置是以比第1設定溫度還要高且絕緣性薄膜的構造能夠 趨於緩和之方式而設定的第2設定溫度T 2來進行第2熱 處理，藉此來形成所期望的絕緣膜。 雖於圖中未示，但實際上薄膜形成裝置具備： 一處理槽；該處理槽是裝入規定的電解液（例如，可 本紙^張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） "" " -43- 543209 A7 __ B7____ 一 五、發明説明（41 ) 使用硫酸，硝酸，王水等的酸，或有機溶煤中使溶質溶解 後的電解液）；及 (請先閱讀背面之注意事項再填寫本頁) 一陰極；該陰極是由浸泡於處理槽內的電解液中的白 金電極所構成；及 一電源；該電源是在陽極與陰極之間以陽極作爲高電 位而通電的通電手段（例如，定電壓源）。 並且，薄膜形成裝置是將形成絕緣性薄膜的對象之具 有半導體結晶的被處理物浸泡於處理槽內，以事先設置於 被處理物的背面側的電極（在實施例3中爲下部電極1 2 )作爲陽極用。 經濟部智慧財產局員工消費合作社印製 如第1 7圖所示，第1熱處理裝置爲燈退火裝置，具 備作爲溫度檢測手段的放射溫度計4 2，及控制手段4 4 。放射溫度計4 2是在於檢測出設置於供以進行第1熱處 理的處理室4 1內的被處理物C的基板溫度（在實施例3 中爲下部電極12)。並且，在實施例3中，在下部電極 1 2的主表面側形成有含晶粒5 1 ，微結晶矽6 3及絕緣 性薄膜的被此處理層6 ’。而且，控制手段4 4是以放射溫 度計4 2的檢測溫度能夠與事先設定的設定溫度（第1設 定溫度T 1 )幾乎形成相等之方式來控制由鹵素等（未圖 示）的輸出。因此，可將第1熱處理裝置兼作第2熱處理 裝置用。藉此，可在同一處理室4 1內連續進行第1熱處 理與第2熱處理。 此外，在第1熱處理裝置中設有水分検出手段4 3。 該水分檢出手段4 3是設置於處理室4 1的排氣側，供以 本紙張尺度適用中國國家標準（CNS ) A4規格（210><297公釐） ~ ~ -44 - 543209 A7 B7 五、發明説明（42) 檢測出被處理物C的絕緣性薄膜所引起的水分。若藉由水 为検出手段4 3所檢測出的水分量不會比規定量來得少， 則控制手段4 4最好是使第1熱處理終了。如此一來，可 防止第1熱處理的熱處理時間Η 2過度不足，且可提高絕 緣膜的電性再現性。就水分検出手段4 3而言，例如可使 用四重極質量分析計（Quadrupole Mass Spectrometer)。並 且，藉由將水分檢出手段4 3設置於處理室4 1的排氣側 ，可較容易檢測出絕緣性薄膜所引起的水分。 第1 8圖是表示利用升溫脫離氣體質量分析法（ Thermal Desorption Spectrometry:TDS)來測定從絕緣性薄膜 脫離的水分流量對基板溫度的變化特性之結果。在第1 8 圖中，脫離的水分流量是以離子電流的形態來表示。若根 據第1 8圖所示的結果，則於基板溫度爲4 5 0 °C以上的 溫度領域中，可視絕緣薄膜中的水分已充分被脫離。如此 狀態是可視爲實質上未含水分的狀態。 若利用如此的絕緣膜形成裝置，則可再現性良好地形 成絕緣耐壓性高且長壽命化的絕緣膜。並且，可藉由共用 第1熱處理裝置及第2熱處理裝置來連續地進行第1熱處 理及第2熱處理。 在實施形態3中，飄移層6是含晶粒5 1及微結晶矽 6 3，但亦可爲不含晶粒5 1的構成。在實施形態3中， 絕緣性薄膜爲氧化矽膜，但亦可爲氮化矽膜。並且，在實 施形態3中，半導體結晶的材料雖是使用砍，但亦可爲砂 以外的半導體材料。 (請先閲讀背面之注意事項再填寫本頁) •裝·Fig. 9 is a graph showing the aging changes of the respective electron emission efficiency when the heating rate is 80 ° C / s_ec, 160 ° C / s_ec and 20 ° C / s-ec. In Fig. 9, the vertical axis represents the electron emission efficiency, and the horizontal axis represents the elapsed time. In Figure 9, a indicates that the heating rate is 80 ° C / S-ec, and b indicates that when the heating rate is 20 ° C / s ec, c This paper size applies the Chinese National Standard (CNS) A4 specification (21 〇X; 297mm) -27- 543209 Α7 __ Β7 V. Description of the invention (25) (Please read the precautions on the back before filling this page) 疋 Indicates when the temperature rise rate is 160 ° C / s_e C. It is clear from FIG. 9 that, in the first embodiment, compared with the comparative example, the electron emission efficiency becomes higher, and the aging change of the electron emission efficiency becomes smaller. As a result, the life will be longer. In addition, by increasing the heating rate (from 8 s-e c to 160 ° C / s_e c), the electron emission efficiency becomes higher. The time-dependent change of the electron emission efficiency in Fig. 9 can be corrected by the function of the exponential function decay (hereinafter referred to as the "decay function"). That is, if the initial electron emission efficiency (hereinafter referred to as "initial electron emission efficiency") is 7/0, the fixed number is r, the proportionality factor (linear coefficient) is r, and the elapsed time is t. The electron emission efficiency β of t can be formed to be approximately equal to the following formula 1. In addition, the larger the time constant r is, the longer the life of the electron source will be. C =? 7 0 · e X p ((— t / r) · ^) •• Formula 1 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Figure 10 shows the initial electron emission efficiency and the fixed number r (minus Number function to modify the relationship). The vertical axis of Fig. 10 is the initial electron emission efficiency; 0, the horizontal axis is the time constant r. In Fig. 10, a indicates that the temperature increase rate is 80 ° C / s-e c, b indicates that the temperature increase rate is 20 ° C / s_ec, and c indicates that the temperature increase rate is i6 0 ° C / s_ec. As can be seen from Fig. 10, as the heating rate is increased, the initial electron emission efficiency 7? 0 and the constant number τ become larger. That is, as the heating rate is increased, the electron emission efficiency can be improved and a longer life can be achieved. Here, if the characteristics of the electron source are evaluated by the product β0 · r of the initial electron emission efficiency and the constant r in time, the larger the value of 0 · τ, the better the characteristics of the electron source. This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) -28- 543209 A7 B7 V. Description of the invention (26) (Please read the precautions on the back before filling this page) β〇 · r 値It is 0 · 092 at b, 5.2 at a, and 2 1 · 8 at C. When the heating rate is increased from 2 Ot / se c to 80 ° C / S_eC, the radon of 770.1 is 50 times larger than that of 20 ° (: / 3-6 (). Therefore, if When the heating rate is set to 80 ° C / s_e c or more, the electron emission efficiency can be improved and the life can be increased compared to when the heating rate is 20 ° C / s_ec. Even if the heating rate is set If the temperature is more than 150 ° C / s_ec, the electron emission efficiency can be improved and the life can be extended. Generally, the temperature rise rate is limited by the performance of the manufacturing equipment (such as lamp annealing) used in the rapid heating method. The current heating rate can be increased to 400 ° C / s_ec at high speed. As mentioned above, if the manufacturing method of the electron source 10 of Embodiment 1 is used, the thickness of the insulating film (silicon oxide film 6 4) in the drift layer 6 can be made. Forms a film thickness (average free path of electrons) that will cause electron tunneling. Therefore, the scattering of electrons in each silicon oxide film 64 can be reduced, and the silicon oxide film 64 in the drift layer 6 can be reduced. The thickness is not uniform. With this, the design of insulation withstand voltage and life will be easier. And the improvement of the longevity, and the improvement of the efficiency of electron emission. Printed by the Intellectual Property of the Ministry of Economy ^ Printed by the Consumer Consumption Cooperative (Embodiment 2) Hereinafter, Embodiment 2 of the present invention will be described. Use: A conductive layer made of a metal film (such as a tungsten film) is provided on one surface of an insulating substrate made of a glass substrate (such as a quartz glass substrate). As shown in FIG. 11, in the embodiment For the electron source 2 of 10, the Chinese national standard (CNS) A4 specification (2i0x297 mm) is applicable to this paper size. 543209 A7 B7 V. Description of the invention (27) [Please read the precautions on the back before filling in this PAGE} A drift layer 6 made of an oxidized porous polycrystalline silicon layer is formed on the conductive layer 12 on the insulating substrate 11 and a surface electrode 7 is formed on the drift layer 6. The surface electrode 7 The structure is the same as that of Embodiment 1. The procedure printed by the Intellectual Property of the Ministry of Economic Affairs and the Consumer Consumption Cooperative for the release of electrons from the electron source 10 is the same as that of the conventional electron source 10 shown in Figure 40. The collector electrode 2 1 is disposed so as to face the surface electrode 7 so that a vacuum state is formed between the surface electrode 7 and the collector electrode 21. In addition, the surface electrode 7 can form a positive electrode (high Potential) positive electrode method, a DC voltage V ps is applied between the surface electrode 7 and the conductive layer 12, and the collector electrode 21 can form a positive electrode (high potential) on the surface electrode 7, and the collector electrode 2 A DC voltage V c is applied between 1 and the surface electrode 7. As long as the DC voltages V ps and V c are set appropriately, the electrons injected from the conductive layer 12 will drift in the drift layer 6 and pass through the surface electrode 7. Release (the one-point lock line in Fig. 11 indicates the flow direction of the electrons e- emitted through the surface electrode 7). In addition, the electrons reaching the surface of the drift layer 6 are thermionic electrons, which easily pass through the surface electrode 7 and are released into a vacuum. In addition, the electron source 10 of the second embodiment is the same as the electron source 10 of the first embodiment. The larger the ratio (I e / I ps) of the radiation current I e to the diode current I ps is, the higher the electron emission efficiency is. high. The structure and function of the drift layer 6 are the same as those of the first embodiment. That is, the drift layer 6 is composed of at least: a grain 5 1, a silicon oxide film 5 2, a majority of micro-structured sand 6 3, and a majority of the oxide sand film 6 4 (see FIG. 1). Moreover, in the drift layer 6, the surface of each crystal grain 51 is porous, and the paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -30- 543209 A7 B7 V. Description of the invention (28) (Please read the precautions on the back before filling this page) The crystalline state will be maintained in the center of each die. Here, the thickness of the silicon oxide film 64 is set to a film thickness (average degree of free travel of electrons) 'that causes a tunneling phenomenon of electrons, and is set to, for example, about 1 to 3 nm. The electron source 10 of the second embodiment can cause electron emission in the same mode as the electron source 10 of the first embodiment. That is, a DC voltage Vp s is applied between the surface electrode 7 and the lower electrode 12, with the surface electrode 7 as a positive electrode, and between the collector electrode 21 and the surface electrode 7, the collector electrode 21 is used as a positive electrode. A direct-current voltage V c is applied, whereby the electrons e—injected into the drift layer 6 from the lower electrode 12 by thermal excitation—will drift, pass through the surface electrode 7, and are placed in a vacuum. When the electron source 10 of the second embodiment is used as the electron source of the display, the patterns of the lower electrode (conductive substrate) and the surface electrode 7 may be appropriately formed. Hereinafter, a method of manufacturing the electron source 10 according to the second embodiment will be described with reference to FIGS. 12A to 12D. Printed by the Intellectual Property of the Ministry of Economic Affairs and the Consumer Cooperatives First, a conductive layer 12 made of a metal film (for example, a tungsten film) is formed on one surface side of the insulating substrate 11 by sputtering or the like, and A conductive substrate is made. Then, an undoped polycrystalline silicon layer 3 (semiconductor layer) is formed on the main surface side of the conductive substrate (here, the conductive layer 12), and the structure shown in FIG. 12A is obtained. As the method for forming the polycrystalline silicon layer 3, for example, a CVD method (LPCVD method, plasma CVD method, catalyst CVD method, etc.), a sputtering method, and a CSG (Continuous Grain Silicon) method can be used. After the formation of an undoped polycrystalline silicon layer 3, the paper size applies the Chinese National Standard (CNS) A4 (210X297 mm) -31-543209 A7 B7 at the anodizing point V. Description of the invention (29) (Please First read the notes on the back and then fill out this page.) During the process, the polycrystalline silicon layer 3 is made porous to form a porous polycrystalline silicon layer 4 (porous semiconductor layer). The construction. In the anodizing process, an anodizing tank containing an electrolytic solution is used. The electrolytic solution is formed by mixing a 5 5 wt% hydrogen fluoride aqueous solution with ethanol in a 1: 1 manner. Then, a platinum electrode (not shown) was used as the negative electrode, and the conductive layer 12 was used as the positive electrode. While the polycrystalline sand layer 3 was irradiated with light, anodization was performed at a constant current. Thereby, the porous polycrystalline silicon layer 4 is formed. The porous polycrystalline silicon layer 4 is composed of crystal grains of polycrystalline silicon and microcrystalline silicon. In the second embodiment, the entire polycrystalline silicon layer 3 is made porous, but a part of the polycrystalline silicon layer 3 may be made porous. Printed by the Intellectual Property Co., Ltd. of the Ministry of Economic Affairs and Consumer Cooperatives after the end of the anodizing process, the porous polycrystalline silicon layer 4 is oxidized by the oxidation process to form a drift composed of the oxidized porous polycrystalline silicon layer. Layer 6 has the structure shown in Figure 1 2C. In the oxidation process, the porous polycrystalline silicon layer 4 is oxidized by a rapid heating method, thereby forming a drift layer 6 containing crystal grains 51, microcrystalline silicon 6 3, and silicon oxide films 5 2 and 64. During the rapid heating oxidation process, as in the case of the first embodiment, a lamp annealing device is used, and the temperature is increased at a predetermined temperature (for example, 80 ° C / sec) in a 02 atmosphere in a furnace. To raise the substrate temperature from room temperature to a predetermined oxidation temperature (for example, 900 ° C). Then, the substrate is maintained at a predetermined oxidation temperature (for example, 1 hour) to perform rapid thermal oxidation (RT0). Then, the substrate temperature was lowered to room temperature. In the second embodiment, although the heating rate is set to 80 ° C / sec, it can be the same as in the first embodiment. The paper size is applicable to the Chinese National Standard (CNS) A4 standard (210X297 mm) -32- 543209 A7. B7 ___ 5. In the description of the invention (30) (please read the precautions on the back before filling in this page), set it to 80 ° C / sec or more, more preferably set to 150 ° C / sec or more. Embodiment 2 is also the same as in the case of Embodiment 1. The oxidation process is an insulation film formation process for forming an insulating film (silicon oxide film 6 4) on the surface side of semiconductor microcrystals (microcrystalline silicon 6 3). After the drift layer 6 is formed, a first thin film layer made of a metal film (a chromium film in the second embodiment) is formed on the drift layer 6 by an electron beam evaporation method. Further, a second thin film layer composed of a metal film (a gold film in Embodiment 2) was formed on the first thin film layer by an electron beam evaporation method. Thereby, the surface electrode 7 composed of the first thin film layer and the second thin film layer is formed, and an electron source 10 having a structure shown in Fig. 12D is obtained. In the second embodiment, although the surface electrode 7 is formed by the electron beam vapor deposition method, the method of forming the surface electrode 7 is not limited to the electron beam vapor deposition method. For example, a ore spraying method may be used. Printed by the Intellectual Property of the Ministry of Economic Affairs ^ Employee Consumer Cooperatives If the manufacturing method of the electron source 10 of Embodiment 2 is used, the thickness of the insulating film (silicon oxide film 6 4) in the drift layer 6 can be formed to cause electron tunneling Phenomenal film thickness (average free travel of electrons). Therefore, the scattering of electrons in each silicon oxide film 64 can be reduced, and the thickness unevenness of the silicon oxide film 64 in the drift layer 6 can be reduced. This makes the design of insulation withstand voltage and life easier. Furthermore, it is possible to improve the insulation withstand voltage and prolong the life, and to improve the electron emission efficiency. In the first and second embodiments, although the drift layer 6 is formed by an oxidized porous polycrystalline silicon layer, the porous polycrystalline silicon layer after nitridation or the porous layer after oxidation / nitridation may be used. The polycrystalline silicon layer is used to form the drift. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -33- 543209 Α7 Β7 5. Description of the invention (31) Layer 6. Alternatively, it may be composed of another porous semiconductor layer after oxidation, nitridation, or oxidation-nitridation. (Please read the precautions on the back before filling in this page) When forming the drift layer 6 with the nitrided porous polycrystalline silicon layer, just use the nitriding process (insulating film formation process; use N Η 3 gas to borrow The process of nitriding the porous polycrystalline silicon layer 4 by a rapid heating method set to the same heating rate as in each embodiment is used instead of the oxidation process (the process of forming an insulating film; the oxidizing porosity is performed by a rapid heating method using a 02 gas. Quality polycrystalline silicon layer 4). In this case, each of the silicon oxide films 5 2 and 64 in FIG. 1 forms a silicon nitride film. When the drift layer 6 is formed by oxidizing and nitriding the porous polycrystalline silicon layer, as long as the oxidizing and nitriding process (the formation process of the insulating film; using 〇2 gas and ΝΗ3 gas, NO gas, ν2 gas, etc.) A mixed gas of nitrogen is used instead of the oxidation process (oxidizing the porous body by the rapid heating method) by performing a process of oxidizing and nitriding the porous polycrystalline silicon layer 4 by a rapid heating method that is set to the same heating rate as in each embodiment. Polycrystalline silicon layer 4). In this case, each of the silicon oxide films 5 2 and 64 in FIG. 1 will form an oxide / nitride sand film. Printed by the Intellectual Property of the Ministry of Economic Affairs and the Consumer Consumption Cooperative, and when the drift layer 6 is formed of a porous polycrystalline silicon layer after oxidation and nitridation, the following oxide film formation process and nitridation process can also be used for formation. The process of forming an insulating film (consisting of a silicon oxide nitride film). This oxide film formation process is to form an oxide film (silicon oxide film) on the surface side of the microcrystalline silicon 63 by a rapid heating method (setting the heating rate to be the same as in each embodiment); and Chinese National Standard (CNS) A4 specification (210 × 297 mm) 543209 Α7 B7 V. Description of the invention (32) The nitriding process is to nitride the silicon oxide film formed during the formation of the oxide film to form oxide and nitrogen. Film (silicon oxide nitride film). (Please read the precautions on the back before filling in this page.) When using a silicon nitride film or a silicon oxide nitride film as the insulating film formed on the surface side of the semiconductor microcrystal (microcrystalline silicon 6 3), Compared with the use of silicon oxide film, the insulation withstand voltage can be improved. Similarly, when a laminated film of a silicon oxide film and a silicon nitride film is used as the insulating film, the insulation withstand voltage can be improved compared with the case of using a silicon oxide film. After the drift layer 6 of each manufacturing method of the electron source 10 of Embodiments 1 and 2 is formed, before the surface electrode 7 is formed, the insulating film can be compensated by a forming process to compensate for defects in the drift layer 6. Defects. By this, it is possible to further improve the withstand voltage of the insulation and to achieve a longer life. This forming process may be performed by raising the substrate temperature to a predetermined temperature (for example, 450 ° C) in a mixed gas composed of at least Η 2 and N 2. By such a molding process, the thickness of the insulating film can be prevented from becoming thicker than that before the molding process, and the introduction of impurities can be prevented. Moreover, compared with the substrate temperature of the rapid heating method, the defect of the insulating film can be compensated at a lower temperature. Printed by the Consumer Cooperative of the Intellectual Property Field of the Ministry of Economic Affairs. In the process of forming the insulating film in Embodiments 1 and 2, although the insulating film was formed by the rapid heating method, the insulating film (silicon oxide) can also be formed by an electrochemical method. Film 6 4). In this case, as long as an oxidation treatment tank containing an electrolyte solution (for example, 1 m ο 1 Η 2 S〇4, 1 m ο 1 HN0 3, aqua regia, etc.) is used, a platinum electrode (not shown in the figure) is used. ) As the negative electrode and the following electrodes (the n-type silicon substrate in Embodiment 1 and the conductive layer 1 2 in Embodiment 2) as the positive electrode, a constant current flows to oxidize the porous polycrystalline silicon layer 4 Just fine. Therefore, the paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) '-35-543209 Α7 Β7 V. Description of the invention (33) It can be split into grain containing 5 1' Microcrystalline sand 6 3 , And each oxide sand film 5 2 (Please read the precautions on the back before filling this page) 6 4 drift layer 6. Of course, the insulating film 'formed by an electrochemical method may be a nitride film such as a silicon nitride film or an oxide nitride film such as a silicon oxide nitride film. When an insulating film is formed by such an electrochemical method, an insulating film having a thickness (average degree of free travel of electrons) which can generate electron tunneling phenomenon can be formed, and the microcrystalline sand 63 will not be damaged, but Compared with a case where an insulating film is formed by a rapid heating method (the temperature rising rate is set to 80 ° C / sec), the electron emission rate is low and the life is short. In addition, a silicon oxide film formed by an electrochemical method contains a larger amount of water than a silicon oxide film formed by a rapid heating method. Printed by the Intellectual Property of the Ministry of Economic Affairs and Employee Cooperatives. Therefore, in the process of forming the insulating film for each insulating film, if the insulating film is formed chemically by the rapid heating method, the silicon oxide can be removed. The moisture content of the film can improve the electron emission characteristics. For g's, before the insulating film is formed by the rapid heating method, as long as the insulating film is formed using an electrochemical method, the rapid heating method can reliably prevent the destruction of microcrystalline silicon, and achieve an electron emission efficiency and insulation. An electron source with high withstand voltage and long life. (Embodiment 3) Hereinafter, Embodiment 3 of the present invention will be described. The electron source of the third embodiment has an insulating film made of a silicon oxide film. In the electron source of Embodiment 3, the conductive substrate is a single-crystal η-type silicon substrate with a resistivity close to that of the conductor (for example, the resistivity is approximately the size of this paper and the Chinese National Standard (CNS) A4 specification is applicable) (210 × 297 mm) -36- 543209 A7 B7 V. Description of the invention (34) O.OlQcm ~ 〇 · 〇2Ω (: (100) substrate of π). (Please read the precautions on the back before filling in this Page) As shown in FIG. 13, the electron source 10 of Embodiment 3 is formed on the main surface side of the n-type sand substrate 1 of the conductive substrate with a drift layer composed of an oxidized porous polycrystalline silicon layer. 6. Furthermore, a surface electrode 7 is formed on the drift layer 6. An ohmic electrode 2 is formed on the back surface of the n-type silicon substrate 1. The lower electrode 1 2 is composed of the n-type silicon substrate 1 and the ohmic electrode 2. Therefore, the 'surface electrode 7 will face the lower electrode 12 and the drift layer 6 will be interposed between the lower electrode 12 and the surface electrode 7. In addition, the porous polycrystalline silicon layer will constitute a porous semiconductor layer. The material of the surface electrode 7 uses work. Material with smaller function. The thickness of the surface electrode 7 is The thickness is set to 10 nm. However, the thickness is not limited to this thickness, as long as it is a thickness through which electrons passing through the drift layer 6 can pass. Therefore, the thickness of the surface electrode 7 may be set to a range of 3 to 15 nm. Yes. The composition and function of the drift layer 6 printed by the intellectual property and employee consumer cooperatives of the Ministry of Economic Affairs are the same as in Embodiment 1. That is, the drift layer 6 is composed of at least: grain 5 1, silicon oxide film 5 2, and most microcrystals. It is composed of silicon 6 3 and most silicon oxide films 64 (see FIG. 1). In the drift layer 6, the surface of each crystal grain 51 is made porous, and the center portion of each crystal grain will be porous. The crystalline state is maintained. Here, the thickness of the silicon oxide film 64 is set to a film thickness (average free path degree of electrons) that causes tunneling of electrons, and is set to, for example, about 1 to 3 nm. As shown in the figure, the electron source 10 of Embodiment 3 can cause electron emission in the same mode as the electron source 10 of Embodiment 1. That is, between the surface electrode 7 and the lower electrode 12, the surface electrode 7 is used as This paper size applies Chinese National Standard (CNS) A4 Grid (210 > < 297 mm) -37-543209 A7 B7 V. Description of the invention (35) (Please read the precautions on the back before filling this page) The positive voltage is applied to the DC voltage V ps, and the collector electrode 21 and the surface electrode Between 7, the collector electrode 21 is used as the positive electrode to apply a DC voltage vc ', thereby the electrons e injected into the drift layer 6 from the lower electrode 12 by thermal excitation will drift, pass through the surface electrode 7, and be released In a vacuum. Hereinafter, the manufacturing method of the electron source 10 according to the third embodiment will be described with reference to the drawings of FIGS. 15A to 15D. First, an ohmic electrode 2 is formed on the back surface of the n-type silicon substrate 1. Then, an undoped polycrystalline sand layer 3 (+ conductor layer) is formed on the main surface of the n-type silicon substrate 1, and a structure not shown in FIG. 5A is obtained. As the method for forming the polycrystalline silicon layer 3, for example, a CVD method (LPCVD method, plasma CVD method, catalyst CVD method, etc.), a beach plating method, and a CSG (Continuous Grain Silicon) method can be used. After the non-doped polycrystalline silicon layer 3 is formed, the polycrystalline silicon layer 3 (the printed layer of the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Semiconductor Economy and the Ministry of Semiconductor Economy) is made porous during the anodizing process. Thereby, the porous polycrystalline silicon layer 4 is formed, and the structure shown in FIG. 15B is obtained. In addition, the porous polycrystalline silicon layer 4 formed during the anodizing process includes a plurality of crystal grains of polycrystalline silicon and a plurality of microcrystalline silicon. In the anodizing process, an anodizing tank containing an electrolytic solution is used. The electrolytic solution is formed by mixing a 5 5 wt% hydrogen fluoride aqueous solution with ethanol in a 1: 1 manner. Then, while illuminating the surface of the polycrystalline silicon layer 3 with a light source composed of a 500 W tungsten lamp, a constant current (that is, a constant current density) was obtained from a power source (not shown). It flows between the lower electrode 12 and the cathode (made of a platinum electrode). In this way, you can apply the Chinese National Standard (CNS) A4 specification (210X297 mm) -38- 543209 Α7 B7 from the multi-junction paper size. 5. Description of the invention (36) The main surface of the crystalline silicon layer 3 to the n-type silicon substrate 1 The polycrystalline silicon layer 3 is made porous to a depth of about 50 Å. (Please read the precautions on the back before filling this page) After the anodizing process is completed, an insulating film is formed on the surface of the semiconductor crystals (each grain and each microcrystalline silicon) contained in the porous polycrystalline sand layer 4 The silicon oxide film 5 2, 6 4. Thereby, a drift layer 6 containing crystal grains 5 1, microcrystalline sand 6 3, and each oxide sand film 5 2, 64 is formed to obtain a structure not shown in FIG. 15 C. When the insulating film is formed, after the anodizing process is completed, it is washed with ethanol, and then a treatment tank containing a 1 M sulfuric acid aqueous solution is used to apply a constant voltage from the power source (not shown) to the lower part. Between the electrode 12 and the cathode (composed of a platinum electrode). Thereby, a basic insulating thin film (silicon oxide film) is formed on the surface of each crystal grain and each microcrystalline silicon by an electrochemical method. Printed by the Intellectual Property of the Ministry of Economic Affairs ^ 7 Employees' cooperatives Second, the heat treatment process shown in Fig. 16 is performed to obtain the desired insulating film (silicon oxide film 5 2, 6 4). As shown in FIG. 16, during the heat treatment, the first heat treatment is performed at a first set temperature T1 and a temperature increase rate that are set so that the moisture contained in the insulating film can be removed without boiling. Then, the second heat treatment is performed at a second set temperature T 2 which is set higher than the first set temperature T 1 and the structure of the insulating film can be relaxed. Thereby, a desired insulating film is obtained. In the heat treatment process, for example, a lamp annealing apparatus is used, but it is not necessary to use an ordinary furnace. The first heat treatment is performed in an oxygen environment (that is, in an environment containing oxidizing species). The first set temperature T1 is set to, for example, 450 °, and the heat treatment time Η2 is set to, for example, 1 hour. And this paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm) -39- 543209 A7 B7 V. Description of the invention (37) (Please read the precautions on the back before filling this page), and the second heat treatment is It is carried out in an oxygen environment (that is, in an environment containing oxidants). The second set temperature T 2 is set to 90 ° C., for example, and the heat treatment time Η 4 is set to 20 minutes, for example. In the third embodiment, the second heat treatment is performed using a rapid heat treatment method. Here, the temperature increase rate 基板 3 during which the substrate temperature is increased from the first set temperature T1 to the second set temperature T2 is set to 150 ° C / sec. In addition, the temperature increase rate of the temperature increase period Η 3 is faster than the temperature increase rate of the temperature increase period 室温 1 from the room temperature to the first set temperature. Although the first set temperature T1 may be set in a range of 100 ° C to 700 ° C, it is most preferably set to 300 ° C or more. The second set temperature T 2 may be set in a range of 60 ° C or higher. The temperature increase rate of η 3 may be set to 20 ° C / s e c or more, but it is preferably set to 150 ° C / s e c or more. Since the temperature increase rate of Η 1 during the temperature increase period is set so that moisture contained in the insulating film does not boil, 疋 'is preferably set to 20 C / s e c or less. The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the surface electrode 7 made of a metal material (for example, gold) by the evaporation method or the like after forming the drift layer 6 to obtain the structure shown in FIG. 15D Electron source 1 0. In the third embodiment, although the surface electrode 7 is formed by a vapor deposition method, the method of forming the surface electrode 7 is not limited to the vapor deposition method, and for example, a sputtering method may be used. When forming an insulating film (silicon oxide films 5 2 and 6 4), first, an electrochemical method is used to crystallize the semiconductor (the porous polycrystalline silicon layer 4 contains a plurality of crystal grains and a plurality of microcrystalline silicon). ) Forms a basic insulating film on the surface. This way, even if the semiconductor crystal is -40 units of nanometers, this paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 543209 A7 B7 5. Invention description (38) (Please read the precautions on the back before (Fill in this page) Small-sized semiconductor crystals such as microcrystalline silicon (semiconductor microcrystals) can still form insulating films that do not damage microcrystalline silicon. The first heat treatment is performed at a first set temperature τ1 and a temperature increase rate that are set so that the moisture contained in the insulating film can be removed without boiling. Then, the second heat treatment is performed at a second set temperature T 2 that is set higher than the first set temperature T 1 and the structure of the insulating film can be relaxed. Thereby, a desired insulating film (silicon oxide films 5 2, 6 4) is obtained. That is, on the one hand, it is possible to prevent a reduction in the insulation withstand voltage of the insulating film due to the boiling of the water in the insulating film, and on the other hand, it is possible to sufficiently reduce the moisture contained in the insulating film. Compared to the insulating film). In addition, it is possible to mitigate defects and strains that adversely affect electrical characteristics by structural relaxation. This makes it possible to form an insulating film having a high insulation withstand voltage and a long life. As for the electron source 10 manufactured by such a manufacturing method, compared with the silicon oxide film 5 2 that uses only the rapid thermal oxidation method to form the drift layer 6, it is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Next, a silicon oxide film 5 2, 6 4 that does not damage the microcrystalline silicon 6 3 can be formed. Therefore, the efficiency of electron emission, insulation withstand voltage, and life can be improved. In addition, when the silicon oxide films 5 2 and 64 are formed using the electrochemical method alone, the moisture and strain in the silicon oxide films 5 2 and 64 can be reduced, and the insulation resistance can be improved. Pressure and life. In the manufacturing method described above, the first set temperature T 1 is set to 700 ° C. or lower. Therefore, even if semiconductor crystals (grains and microcrystalline silicon) are formed on glass that is cheaper than quartz glass substrates and has a low heat-resistant temperature, the basic paper size of China applies to China National Standard (CNS) A4 (210X 297 mm) -41- 543209 A7 B7 V. Description of the invention (39) (Please read the precautions on the back before filling this page) When the front side of the board, the heat treatment time of the first heat treatment can be extended 拉 2. This can further reduce the residual moisture after the first heat treatment. In addition, since the second set temperature T 2 is set to a temperature range of 6 0 0 t or more, the second set temperature T 2 can be reduced in the insulating film (the silicon oxide film 5 2, 6 4) than the first heat-treated insulating film. Residual moisture. In addition, since the second heat treatment is performed by the rapid heat treatment method, the temperature can be raised to the second set temperature T 2 in a short time. Therefore, damage caused in the microcrystalline silicon can be reduced. Printed by the Intellectual Property of the Ministry of Economic Affairs ^ Employee Consumer Cooperatives. Since the first heat treatment is carried out in an environment containing oxidizing materials, it is expected to compensate for defects caused by the release of moisture from the insulating film. In addition, when removing moisture from the insulating film, it is not limited to thermal energy, and energy combined with oxygen or reaction energy may be used. This makes it possible to further reduce the residual moisture after the first heat treatment. In addition, since the second heat treatment is performed in an environment containing an oxidizing agent, a thin thermal oxide film can be formed on the surface side of the insulating film by the second heat treatment, thereby improving the insulation withstand voltage of the insulating film. In the third embodiment, the second heat treatment is performed after the first heat treatment. However, instead of performing the second heat treatment, only the first heat treatment may be performed. Compared with the past, this situation can also improve the insulation withstand voltage and life. It is also possible to perform the first heat treatment in a vacuum or an inert gas environment. If the first heat treatment can be performed in a vacuum, the first set temperature T 1 can be set to be low. That is, by performing the first heat treatment in a vacuum, the moisture contained in the insulating film can be removed at a relatively low temperature. Therefore, the first set temperature T 1 can be set to be low. If the first heat treatment is performed in an inert gas environment, it is not necessary to perform the first heat treatment using a vacuum device. Because this paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) -42- 543209 A7 ____ B7 V. Description of the invention (4〇) This can use a device that is cheaper than a vacuum device, and can improve Processing capacity of the apparatus for performing the first heat treatment. (Please read the precautions on the back before filling out this page.) Also, the second heat treatment can also be performed in an inert gas environment or an environment containing nitrogen. When the second heat treatment is performed in an inert gas environment, it is not necessary to use a vacuum device for the second heat treatment. Therefore, it is possible to use a device that is cheaper than a vacuum device, and it is possible to increase the processing capacity of the device that performs the second heat treatment. In addition, since the film thickness of the insulating film is not changed by the second heat treatment, the film thickness of the insulating film can be controlled only under the conditions of the electrochemical method. Therefore, the film thickness controllability of the insulating film can be improved. On the other hand, if the second heat treatment is performed in an environment containing a nitride type, a thin nitrogen oxide film can be formed on the surface side of the insulating film by the second heat treatment. Thereby, the insulation withstand voltage of the insulating film can be improved, and the electrical characteristics can be improved due to a reduction in the density of defects in the insulating film. Printed by the Intellectual Property of the Ministry of Economic Affairs and the Consumer Cooperative. When forming an insulating film, an insulating film forming apparatus including a thin film forming apparatus, a first heat treatment apparatus, and a second heat treatment apparatus may be used. Here, the thin film forming apparatus electrically forms an insulating thin film on the surface of the semiconductor crystal. The first heat treatment device performs the first heat treatment with a first set temperature τ 1 and a temperature increase rate set so that moisture contained in the insulating film can be removed without boiling. The second heat treatment device performs the second heat treatment at a second set temperature T 2 which is set higher than the first set temperature and the structure of the insulating film can be relaxed, thereby forming a desired insulating film. . Although it is not shown in the figure, in fact, the thin film forming apparatus includes: a processing tank; the processing tank is filled with a prescribed electrolyte (for example, the size of the paper can be applied to the Chinese National Standard (CNS) A4 specification (210X297 mm) ) &Quot; " " -43- 543209 A7 __ B7____ One or five, description of the invention (41) Use of sulfuric acid, nitric acid, aqua regia, etc., or the electrolyte after dissolving the solute in organic dissolved coal); and (please Read the precautions on the back before filling in this page) A cathode; the cathode is made of platinum electrodes immersed in the electrolyte in the processing tank; and a power source; the power source uses the anode as a high voltage between the anode and the cathode A means of energizing (eg, a constant voltage source). In addition, the thin film forming device is an electrode (the lower electrode 1 in Example 3 is provided on the back side of the processed object) in which a processed object having semiconductor crystals as an object for forming an insulating film is immersed in a processing tank. ) As anode. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs As shown in Fig. 17, the first heat treatment device is a lamp annealing device, which is provided with a radiation thermometer 4 2 as a temperature detection means and a control means 4 4. The radiation thermometer 42 detects the substrate temperature (the lower electrode 12 in the third embodiment) of the substrate C provided in the processing chamber 41 for performing the first heat treatment. Furthermore, in Example 3, the treated layer 6 'containing crystal grains 5 1, microcrystalline silicon 6 3 and an insulating film was formed on the main surface side of the lower electrode 12. In addition, the control means 44 controls the output of a halogen or the like (not shown) in such a manner that the detection temperature of the radiation thermometer 42 can be made almost equal to the preset temperature (the first set temperature T 1). Therefore, the first heat treatment apparatus can also be used as the second heat treatment apparatus. Thereby, the first heat treatment and the second heat treatment can be continuously performed in the same processing chamber 41. In addition, the first heat treatment device is provided with a moisture evacuation means 43. The moisture detection means 43 is provided on the exhaust side of the processing chamber 41, and is adapted to the Chinese paper standard (CNS) A4 (210 > < 297 mm) ~ ~ -44-543209 A7 B7 V. Description of the invention (42) The moisture caused by the insulating film of the object C to be treated was detected. If the amount of water detected by the dehydration means 4 3 using water is not less than a predetermined amount, the control means 4 4 preferably ends the first heat treatment. In this way, the heat treatment time Η 2 of the first heat treatment can be prevented from being excessively insufficient, and the electrical reproducibility of the insulating film can be improved. As the moisture extraction means 43, for example, a quadrupole mass spectrometer can be used. In addition, by providing the moisture detection means 43 on the exhaust side of the processing chamber 41, it is possible to easily detect the moisture caused by the insulating film. FIG. 18 is a graph showing the results of measuring the change characteristics of the flow rate of the moisture detached from the insulating film with respect to the substrate temperature by a thermal desorption spectroscopy (TDS). In Fig. 18, the desorbed water flow rate is shown in the form of ion current. According to the results shown in Fig. 18, it can be seen that the moisture in the insulating film has been sufficiently removed in a temperature range where the substrate temperature is 450 ° C or higher. Such a state can be regarded as a state substantially free of moisture. By using such an insulating film forming apparatus, an insulating film with high insulation withstand voltage and long life can be formed with good reproducibility. Furthermore, the first heat treatment and the second heat treatment can be performed continuously by sharing the first heat treatment device and the second heat treatment device. In Embodiment 3, the drift layer 6 includes crystal grains 51 and microcrystalline silicon 6 3, but may have a configuration not including crystal grains 51. In Embodiment 3, the insulating thin film is a silicon oxide film, but it may be a silicon nitride film. In Embodiment 3, although the material for semiconductor crystals is chopped, it may be a semiconductor material other than sand. (Please read the notes on the back before filling this page)

、1T 經濟部智慧財產局8工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) Α4規格（21〇><297公釐） -45- 543209 A7 B7 五、發明説明（43) (請先閱讀背面之注意事項再填寫本頁) 又，亦可取代飄移層6，利用絕緣膜（藉由上述絕緣 薄膜的形成方法來形成）來形成具備：下部電極（導電性 基板），及表面電極，及介於下部電極與表面電極之間白勺 絕緣層之電子源。如此的電子源與習知的Μ I Μ型電場放 射型電子源相較下，可使絕緣耐壓及壽命提高。 (實施形態4 ) 以下，說明本發明之實施形態4。在實施形態4中， 導電性基板是使用：在由玻璃基板所構成的絕緣性基板 1 1的一表面上設置導電性層1 2 (例如，鉻膜等的金屬 膜或I Τ ◦膜等）者。在使用如此的基板（在絕緣性基板 1 1的一表面側形成導電性層1 2 )時，與使用半導體基 板來作爲導電性基板時相較下，可使電子源大面積化及低 成本化。 實施形態4之電子源1 0的基本構成是與第4 0圖所 示之以往的電子源1 0 〃相同。亦即，在絕緣性基板i丄 上的導電性層1 2上形成有無摻雜質的多結晶砂層3 ( _ 經濟部智慧財產局員工消費合作社印製 導體層）。在多結晶矽層3上形成有由氧化後的多孔質$ 結晶砂層所構成的飄移層6。在飄移層6上形成有* $胃_ 極7。表面電極7是使用功函數較小的材料（例如，^ ^ 。表面電極7的厚度是設定成3〜1 5 nm。有關 6的構造會在往後敘述。在第1 9 G圖所示的電子源i 〇 中，會使多結晶矽層3的一部份介於導電性層1 2與飄1 _ 層6之間。但，亦可不介在多結晶砂層3，而於導電;丨生_ 本紙張尺度適用中國國家標準（CNS ) A4規格（210Χ297公釐） -----— 543209 A7 B7 五、發明説明（44) 1 2上形成飄移層6。 (請先閲讀背面之注意事項再填寫本頁) 使電子從電子源1 0放出的程序是與第4 0圖所示之 以往的電子源1 0 〃，時相同。亦即，以能夠對向於表面 電極7之方式來配設集極電極21(參照第40圖），且 使表面電極7與集極電極2 1之間形成真空狀態。又，以 表面電極7能夠對導電性層1 2形成高電位（正極）之方 式’在表面電極7與導電性層1 2之間施加直流電壓 V p s。並且，以集極電極2 1能夠對表面電極7形成高 電位（正極）之方式，在集極電極2 1與表面電極7之間 施加直流電壓V c。只要適當的設定各直流電壓vp s ， V c，則由導電性層1 2注入的電子便會飄移於飄移層6 內，經由表面電極7而釋放出。 以下，一邊參照第1 9A〜1 9D圖，一邊說明實施 形態4之電子源1 0的製造方法。 首先’在絕緣性基板1 1的一表面側，藉由濺鍍法等 來設置導電性層1 2，而形成導電性基板，而取得第 1 9 A圖所示的構造。 經濟部智慧財產苟員工消費合作社印製 其次’在導電性基板的一表面側，形成（成膜）預定 的膜厚（例如1 · 5 // m )之無摻雜質的多結晶矽層3 ( 半導體層），而取得第1 9 B圖所示的構造。就多結晶石夕 層3的成膜方法而言，例如可使用：C V D法（ LPCVD法，電漿CVD法，觸媒CVD法等），濺鍍 法，及 c S G ( Continuous Grain Silicon)法等。 在形成無摻雜質的多結晶矽層3之後，在多結晶矽層 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -47- 543209 A7 B7 五、發明説明（45) (請先閱讀背面之注意事項再填寫本頁) 3上設置一光罩材（圖示省略），該光罩材是供以只在預 定領域形成多孔質多結晶矽層4 /(後述）。然後，準備 一放進有電解液的陽極氧化處理槽，該電解液是由：以1 比1方式來混合5 5 w t %的氟化氫水溶液與乙醇之混合 液所形成。之後，以白金電極（圖中未示）作爲負極，以 導電性層1 2作爲正極，一邊對多結晶矽層3進行光照射 ’ 一邊以預定的條件來進行陽極氧化。藉此來形成多孔質 多結晶矽層4 > 。然後，除去光罩材，而取得第1 9 C圖 所示的構造。在實施形態4的陽極氧化處理中，是使陽極 氧化處理的期間，及照射於多結晶矽層3表面的光量，以 及電流密度形成一定。但，此處理條件亦可適當的予以變 更（例如，使電流密度變化）。 經濟部智慧財產笱員工消費合作社印製 在陽極氧化處理終了後，在惰性氣體的N 2氣體中，以 4 0 0 °C來針對多孔質多結晶矽層4 >後進行退火，藉此 來取得第19D圖所示的構造。第19D圖中的4是表示 退火後的多孔質多結晶矽層。在退火前，多孔質多結晶矽 層4 /的最上表面，如第4 2圖所示，終端爲氫原子。並 且，氟原子會被取入多孔質多結晶矽層4 /中，而且水分 會吸附於多孔質多結晶矽層4 /的表面。 又，如第2 0圖所示，藉由上述退火的進行，退火後 的多孔質多結晶砍層4的最上表面會形成氣原子，氟原子 及水分脫離的狀態。並且，在針對多孔質多結晶矽層4 / 進行退火時的溫度，只要對應於導電性基板的材料或半導 體層的材料等來適當地予以設定於1 0 0 °C〜7 0 0 °C的 -48- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 543209 A7 B7 五、發明説明（46) (請先閱讀背面之注意事項再填寫本頁) 溫度範圍即可。而且，在針對多孔質多結晶矽層4 /進行 退火時的惰性氣體，並非只限於N 2氣體，例如亦可爲A r 氣體等。 其次，在1 ( m ο 1 )的硫酸（Η 2 S〇4 )水溶液中 ，針對退火後的多孔質多結晶矽層4進行電氣化學性的氧 化處理，而來形成飄移層6 >，取得第1 9 Ε圖所示的構 造。並且，進行電氣化學性的氧化時之水溶液及濃度，並 無特別加以限定。例如，可使用硝酸水溶液等。 在電氣化學性的氧化終了後，在惰性氣體的Ν 2氣體中 ，以4 0 0 °C來針對飄移層6 —進行退火，取得第1 9 F 圖所示的構造。第1 9 F圖中的6是表示退火後的飄移層 6。並且，在針對飄移層6 >進行退火時的溫度，只要對 應於導電性基板的材料或半導體層的材料等來適當地予以 設定於1 0 0 °C〜7 0 0 °C的溫度範圍即可。而且，在針 對飄移層6 >進行退火時的惰性氣體，並非只限於ν 2氣體 ，例如亦可爲A r氣體等。又，飄移層6 >的退火並非一 定要在惰性氣體中進行，亦可於真空中進行。 經濟部智慧財產苟8工消費合作社印製 在形成飄移層6 /之後，在飄移層6上，例如藉由蒸 鍍法來形成由導電性薄膜（例如，金薄膜）所構成的表面 電極7，取得第1 9 G圖所示構造的電子源1 〇。在此， 表面電極7的形成方法，並非只限於蒸鍍法，例如亦可使 用濺鍍法。 藉由如此的製造方法而製成的電子源1 〇的飄移層6 與第3 9圖所示的習知電子源1 〇的飄移層6 〃同樣的， 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） " -49- 543209 A7 B7 五、發明説明（47) (請先閱讀背面之注意事項再填寫本頁) 至少由：柱狀多結晶矽的晶粒5 1 ，及薄氧化矽膜5 2， 及奈米單位的微結晶矽6 3，以及氧化矽膜6 4所構成。 但，實施形態4的電子源1 0與習知的電子源有所不同。 亦即，就該電子源1 0而言，是在惰性氣體中針對以陽極 氧化處理所形成的多孔質多結晶矽層4 >來進行退火後， 藉由氧化退火後的多孔質多結晶矽層4 >來形成飄移層 6 >。並且，在惰性氣體中使飄移層6 >退火後形成表面 電極7。因此，與陽極氧化處理後馬上在多孔質多結晶石夕 層吸附水分等的狀態下氧化多孔質多結晶矽層時相較下， 比較能夠降低因飄移層6中所含的氫或氟等雜質所引起的 缺陷。並且，可形成S i〇2的構造或接近S i〇2構造的 緻密氧化膜。藉此，可減少電子放出效率的時效變化，提 高絕緣耐壓，實現可靠度高的電子源1 〇。 經濟部智慧財產局員工消費合作社印製 在上述的製造方法中，由於是以電氣化學性的方式來 氧化退火後的多孔質多結晶矽層4，因此能夠以較低的溫 度來氧化退火後的多孔質多結晶矽層4。但，就氧化退火 後的多孔質多結晶矽層4的過程而言，並非只限於電氣化 學性的氧化過程。例如，可爲利用0 2氣體的熱氧化過程， 及利用〇2電漿的氧化過程，以及利用臭氧的氧化過程等之 乾式製程。由於這些過程並非是如電氣化學性的氧化過程 那樣屬於溼式製程，因此不一定要進行氧化過程後的退火 。所以與進行電氣化學性的氧化時相較下，可減少過程數 。而且，還能夠在燈退火裝置中連續進行多孔質多結晶砂 層4 /的退火處理，及退火後的多孔質多結晶矽層4的氧 木&張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -50 - 543209 Α7 Β7 五、發明説明（48) 化處理。 (請先閲讀背面之注意事項再填寫本頁) 在實施形態4中，導電性基板是使用：在絕緣性基板 1 1 (由玻璃基板所構成）的一表面上形成導電性層1 2 者，但導電性基板亦可使用鉻等的金屬基板。又，亦可使 用半導體基板（例如，阻抗率較接近導體的阻抗率之η型 砂基板，或一面側形成有作爲導電性層的η型領域之ρ型 砂基板等）。又，絕緣性基板1 1除了玻璃基板以外，可 _使用陶瓷基板等。 在實施形態4中，表面電極7的材料是採用金，但並 非只限於此，例如亦可使用鋁，鉻，鎢，鎳，白金等。又 ，亦可以層疊於厚度方向的至少2層薄膜層來構成表面電 極7 °在以2層的薄膜層來構成表面電極7時，就上層的 薄膜層材料而言，例如可使用金等，就下層的薄膜層（飄 移層6側的薄膜層）材料而言，可使用鉻，鎳，白金，鈦 ，銥等。 經濟部智慧財產局員工消費合作社印製 在實施形態4中，雖是藉由氧化後的多孔質多結晶矽 層來構成飄移層6，但亦可以氧化後的多孔質單結晶矽層 或其他氧化後的多孔質半導體層來構成。 (實施形態5 ) 以下，說明本發明之實施形態5。 如第2 1 F圖所示，在實施形態5中，導電性基板是 使用：在由玻璃基板所構成的絕緣性基板1 1的一表面上 設置導電性層1 2 (例如，鉻膜，鈦膜，鎢膜等的金屬膜 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） -51 - 543209 A7 B7 五、發明説明（49) (請先閲讀背面之注意事項再填寫本頁) 或複數種類的金屬膜的層疊膜，I T 0膜等）者。在使用 如此的基板（在絕緣性基板1 1的一表面側形成導電性層 1 2 )時，與使用半導體基板來作爲導電性基板時相較下 ’可使電子源大面積化及低成本化。 實施形態5之電子源1 0的基本構成是與第4 0圖所 示之以往的電子源1 0 〃幾乎相同。亦即，在絕緣性基板 1 1上的導電性層1 2上形成有無摻雜質的多結晶矽層 3 /(半導體層）。在多結晶矽層3 >上形成有由氧化後 的多孔質多結晶矽層所構成的飄移層6。在飄移層6上形 成有表面電極7。表面電極7是使用功函數較小的材料（ 例如’金）。表面電極7的厚度是設定成1 0〜1 5 n m 。有關飄移層6的構造會在往後敘述。在第2 1 F圖所示 的電子源1 0中，會使多結晶矽層3 /的一部份介於導電 性層1 2與飄移層6之間。但，亦可不介在多結晶矽層 3 /，而於導電性層1 2上形成飄移層6。 經濟部智慧財產局Μ工消費合作社印製 使電子從電子源1 0放出的程序是與第4 0圖所示之 以往的電子源1 〇 〃時相同。亦即，以能夠對向於表面電 極7之方式來配設集極電極2.1 (參照第40圖），且使 表面電極7與集極電極2 1之間形成真空狀態。又，以表 面電極7能夠對導電性層1 2形成高電位（正極）之方式 ’在表面電極7與導電性層1 2之間施加直流電壓V p s 。並且，以集極電極2 1能夠對表面電極7形成高電位之 方式，在集極電極2 1與表面電極7之間施加直流電壓 Vc。只要適當的設定各直流電壓vp s ，vc ，則由導 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ29?公釐） -52- 543209 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（5〇) 電性層1 2注入的電子便會飄移於飄移層6內，經由表面 電極7而釋放出。 以下，一邊參照第2 1 A〜2 1 F圖，一邊說明實施 形態5之電子源1 0的製造方法。 首先，在絕緣性基板1 1的一表面側，藉由濺鍍法等 來設置導電性層1 2，而形成導電性基板，而取得第 2 1 A圖所示的構造。然後，在導電性基板的一表面側（ 亦即，在導電性層1 2上），形成（成膜）預定的膜厚（ 例如1 · 5 // m )的多結晶矽層3 (由多結晶半導體之多 結晶矽所構成的層狀半導體層），而取得第2 1 B圖所示 的構造。就多結晶矽層3的成膜方法而言，例如可使用： CVD法（LPCVD法，電漿CVD法，觸媒CVD法 等），濺鍍法，及 C S G (Continuous Grain Silicon)法等 。若成膜溫度微6 0 0 °C以下，則絕緣性基板1 1可例如 使用無鹼玻璃基板，低鹼玻璃基板，鹼石灰玻璃基板等較 便宜的玻璃基板，而使能夠謀求低成本化。 在形成無摻雜質的多結晶矽層3後，在惰性氣體的N 2 氣體中，以規定的退火溫度（例如，1 〇 〇 °C〜7 0 0 °C ’最好爲5 0 0 °C〜6 0 0 °C )來進行規定時間（例如， 1小時）的退火。藉此來改善結晶性，且降低缺陷，取得 第2 1 C圖所示的構造。第2 1 C圖中的3 /是表示退火 後的結晶矽層。在實施形態5中，退火後的多結晶矽層 3 /爲構成多結晶半導體層。並且，在針對多結晶矽層3 進行退火時的情性氣體，並非只限於N 2氣體，例如亦可使 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 543209 Α7 Β7 經濟部智慧財產局員工消費合作社印製 五、發明説明（51) 用A r氣體等。而且，多結晶矽層3的退火，並非一定要 在惰性氣體中進行，亦可在真空中進行。若在惰性氣體中 或真空中進行退火，則可於退火時抑止活性的雜質導入多 結晶矽層3中。此外，在針對多結晶矽層3進行退火時的 溫度，最好是在考量導電性基板的材料等的耐熱溫度下來 設定成較高的溫度。 在進行退火後，在多結晶矽層3 ·上設置一光罩材（圖 示省略），該光罩材是供以只在預定領域形成多孔質多結 晶矽層4 (後述）。然後，準備一放進有電解液的陽極氧 化處理槽，該電解液是由：以1比1方式來混合5 5 w t %的氟化氫水溶液與乙醇之混合液所形成。之後，以白金 電極（圖中未示）作爲負極，以導電性層1 2作爲正極， 一邊對多結晶矽層3 >進行光照射，一邊以預定的條件來 進行陽極氧化。藉此來形成多孔質多結晶矽層4。然後， 除去光罩材，而取得第2 1 D圖所示的構造。在實施形態 5的陽極氧化處理中，是使陽極氧化處理的期間，及照射 於多結晶矽層3 /表面的光量，以及電流密度形成一定。 但，此處理條件亦可適當的予以變更（例如，使電流密度 變化）。 在陽極氧化處理終了後，在1 ( m ο 1 )的硫酸（ H 2 S〇4 )水溶液中，針對多孔質多結晶矽層4進行電氣 化學性的氧化處理，而來形成飄移層6，取得第2 1 Ε圖 所示的構造。在此，進行電氣化學性的氧化時之水溶液及 濃度，並無特別加以限定。例如，可使用硝酸水溶液等。 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） -54- 543209 A7 -----B7 五、發明説明（52) 在形成飄移層6之後，在飄移層6上，例如藉由蒸鍍 法來形成由導電性薄膜（例如，金薄膜）所構成的表面電 極7，取得第2 1 F圖所示的電子源i 〇。在此，表面電 極7的形成方法，並非只限於蒸鍍法，例如亦可使用濺鑛 法。 藉由如此的製造方法而製成的電子源1 〇的飄移層6 與第3 9圖所不的習知電子源1 〇的飄移層6 〃同樣的， 至少由：柱狀多結晶矽的晶粒5 1 ，及薄氧化矽膜5 2， 及奈米單位的微結晶矽6 3，以及氧化矽膜6 4所構成。 但，實施形態5的電子源1 〇與習知的電子源有所不同。 亦即，就該電子源1 〇而言，是在針對多結晶矽層3進行 退火後，藉由氧化陽極氧化處理中所形成的多孔質多結晶 矽層4來形成飄移層6。因此，可藉由層狀半導體層（多 結晶矽層3 )的退火來形成多結晶半導體層（多結晶矽層 3。° 藉此，可一邊以較低的溫度（6 0 0 °C以下）來形成 多結晶矽層3 /，一邊在多結晶矽層3與導電性層1 2的 界面形成由半導體與金屬所構成的化合物層或合金層，且 多結晶矽層3會在界面幾乎形成結晶化，因此與以往較低 溫形成的多結晶矽層3相較下，可謀求低阻抗化，其結果 ，多結晶矽層3與導電性層1 2間的阻擋層或高阻抗層會 減少，因此可提供一種能夠提高電子放出效率及可靠度的 電子源1 0。此外，以如此製造方法所製成的電子源1 0 與第3 8圖所示的習知電子源1 0 >同樣的’電子放出特 (請先閱讀背面之注意事項再填寫本頁) -裝· 訂 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（2!〇x297公釐） -55- 543209 A7 B7 五、發明説明（53) 性的真空度依賴性小，且電子放出時不會發生跳動現象， 可安定地放出電子。 (請先閱讀背面之注意事項再填寫本頁) 第2 2 A〜C圖是表示針對習知的電子源1 0 〃 （參 照第4 0圖）與實施形態5的製造方法所製成的電子源 1 0測定電子放出特性（放射電流I e ，電子放出效率等 )的結果。第2 2 A圖是有關習知的電子源1 〇 〃 （習知 例：未進行退火時）的測定結果，第2 2 B圖是有關退火 溫度爲5 0 0 °C的實施形態5的電子源1 0 (實施例2 ) 的測定結果。 第2 2 A〜C圖的橫軸是表示直流電壓V p s ，左側 的縱軸是表示電流密度。α是表示二極體電流I p s的電 流密度，/?是表示放射電流I e的電流密度。又，第 2 2 A〜C圖的右側的縱軸是表示電子放出效率。r是表 示電子放出效率。直流電壓Vc爲一定（1〇 〇v)。電 子放出效率爲（I e/I p s)x 1 〇〇 〔％〕所求得的 値。無論是習知例，還是實施例1及2，往導電性基板之 多結晶矽層3的堆積皆是藉由電漿C V D法來進行。 經濟部智慧財產局員工消費合作社印製 由第2 2 A〜C圖可知，進行退火的實施例1 ，2與 未進行退火的習知例相較下，放射電流I e及電子放出效 率會大幅度地提升。並且，若比較實施例1與實施例2， 則退火溫度較高的實施例2在放射電流I e及電子放出效 率的雙方皆會提升。 此外，在上述製造方法中，雖是以多結晶矽層3 (由 多結晶矽所形成）來構成層狀的半導體層，但亦可以微結 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -56 - 543209 Α7 Β7 五、發明説明（54) (請先閱讀背面之注意事項再填寫本頁) 晶矽之類的半導體微結晶來構成層狀的半導體層。此情況 ，只要在形成由微結晶矽所構成的層狀半導體層之後，藉 由退火來形成多結晶化，而形成多結晶矽層3 ’即可。 在實施形態5中，導電性基板是使用：在絕緣性基板 1 1 (由玻璃基板所構成）的一表面上形成導電性層1 2 者，但導電性基板亦可使用鉻等的金屬基板。或者，亦可 使用半導體基板（例如，阻抗率較接近導體的阻抗率之η 型矽基板，或一面側形成有作爲導電性層的η型領域之ρ 型矽基板等）。又，絕緣性基板1 1除了玻璃基板以外， 可使用陶瓷基板等。 在實施形態5中，表面電極7的材料是採用金，但並 非只限於此，例如亦可使用鋁，鉻，鎢，鎳，白金等。 又，亦可以層疊於厚度方向的至少2層薄膜層來構成 表面電極7。此情況，就上層的薄膜層材料而言，例如可 使用金等，就下層的薄膜層（飄移層6側的薄膜層）材料 而言，可使用鉻，鎳，白金，鈦，銥等。 經濟部智慧財產苟員工消費合作社印製 在實施形態5中，雖是藉由氧化後的多孔質多結晶砂 層來構成飄移層6，但亦可以其他氧化後的多孔質半導體 層來構成。 (實施形態6 ) 以下，說明本發明之實施形態6。 如第2 3圖所示，在實施形態6的電子源1 〇中，導 電性基板是使用：阻抗率較接近導體的阻抗率之單結晶的 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐） -57- 543209 A7 B7 五、發明説明（55) η型矽基板（例如，阻抗率約爲〇 . 0 1 Ω c m〜 〇.〇2Dcm 的（1〇〇）基板）。 (請先閱讀背面之注意事項再填寫本頁) 在此電子源1 〇中，在η型矽基板1的主表面側形成 有：由氧化後的多孔質多結晶矽層所構成的飄移層6。並 且，在飄移層6上形成有表面電極7。在η型矽基板1的 背面形成有歐姆電極2。而且，以η型矽基板1與歐姆基 板2來構成導電性層1 2。因此，表面電極7會對向於下 部電極1 2，飄移層6會介於下部電極1 2與表面電極7 之間。 表面電極7，例如可由金（Au)，白金（Pt)， 鉻（C r )的等功函數小，耐氧化性佳且化學性安定的金 屬所構成的金屬膜或這些金屬膜的層疊膜所形成。表面電 極7的厚度只要設定於3〜1 5 n m的程度範圍即可。 飄移層6的構成及機能，基本上與實施形態1時相同 。亦即，飄移層6是至少由：晶粒5 1 ，氧化矽膜5 2， 經濟部智慧財產局員工消費合作社印製 多數的微結晶砂6 3，及多數的氧化砂膜6 4所構成（參 照第1圖）。並且，在飄移層6中，各晶粒5 1的表面爲 多孔質化’在各晶粒的中心部份會維持結晶狀態。並且， 各晶粒5 1是延伸於下部電極1 2的厚度方向。有關絕緣 膜5 2 ’ 6 4方面，會在往後所述之製造方法的說明時詳 述。 如第2 4圖所不，實施形態6的電子源1 〇可以和實 施形態1或實施形態3的電子源1 〇同樣的模式來引起電 子放出。亦即，在表面電極7與下部電極1 2之間，以表 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 58 - 543209 A7 ____B7 五、發明説明（56) 面電極7作爲正極來施加直流電壓Vp s ，且在集極電極 2 1 (例如，I T〇膜等的透明絕緣膜）與表面電極7之 (請先閲讀背面之注意事項再填寫本頁) 間，以集極電極2 1作爲正極來施加直流電壓V c，藉此 ’從下部電極1 2藉由熱激勵而注入飄移層6的電子e —會 飄移，穿過表面電極7，放出於真空中。 以下，一邊參照第2 5A〜2 5D圖，一邊說明實施 形態6之電子源1 0的製造方法。 首先，在η型矽基板1的背面形成歐姆電極2。然後 ’在η型矽基板1的主表面（一表面）上形成無摻雜質的 多結晶矽層3 (半導體層），而取得第2 5 Α圖所示的構 造。就多結晶矽層3的成膜方法而言，例如可使用： CVD法（LPCVD法，電漿CVD法，觸媒CVD法 等）’濺鍍法’及 C S G (Continuous Grain Silicon)法等 ο 在形成無摻雜質的多結晶矽層3之後，藉由使用電解 液的陽極氧化處理來進行使多結晶矽層3 (形成陽極氧化 經濟部智慧財產^7M工消費合作社印製 的對象之半導體層）多孔質化。藉此來形成多孔質多結晶 砂層4 (多孔質半導體層），取得第2 5 Β圖所示的構造 。並且，在陽極氧化處理過程中所形成的多孔質多結晶矽 層4是包含：多數的多結晶矽的晶粒5 1 (參照第1圖） ’及多數的微結晶砂6 3 (參照第1圖）。在陽極氧化處 理過程中，是使用放進有電解液的陽極氧化處理槽，該電 解液是由·以1比1方式來混合5 5 w t %的氟化氫水溶 液與乙醇之混合液所形成。然後，一邊利用由5 〇 〇 w的 Ϊ紙張尺度適财關家縣（CNS ) A4規格（21GX297公釐)' -59 - 543209 Α7 Β7 五、發明説明（57) (請先閱讀背面之注意事項再填寫本頁) 鎢絲燈所構成的光源來對多結晶矽層3的表面進行光照射 ，一邊使電流流動於下部電極1 2與陰極（由白金電極所 構成）之間。藉此，可從主表面到預定深度爲止（在實施 形態6中，雖是設定成未到達下部電極1 2的深度，但亦 可設定成到達下部電極1 2的深度），使多結晶矽層3多 孔質化。。 在陽極氧化處理過程終了後，進行利用乙醇的洗淨， 然後進行絕緣膜形成過程，亦即在多孔質多結晶矽層4中 所含的各晶粒5 1及各微結晶矽6 3的表面形成絕緣膜 5 2，6 4。藉此，形成含晶粒5 1，微結晶矽6 3，及 各氧化矽膜52，64之飄移層6，取得第25C圖所示 的構造。並且，有關絕緣膜形成過程方面會在往後敘述。 在形成飄移層6後，藉由蒸鍍法等來形成由金屬材料 (例如，金）所構成的表面電極7，取得第2 5 D圖所示 的構造。在實施形態6中，雖是藉由蒸鍍法來形成表面電 極7，但表面電極7的形成方法並非只限於蒸鍍法，例如 亦可使用濺鍍法。 經濟部智慧財產¾¾工消費合作社印製 在絕緣膜形成過程中，進行氧化處理及氮化處理。就 氧化處理而言，是在可防止對各微結晶砂6 3產生損傷的 處理下，在各微結晶矽6 3的表面形成可產生電子的穿隧 現象的膜厚（比微結晶矽6 3的結晶粒徑還要小的膜厚） 之氧化膜（氧化矽膜）。並且，就氮化處理而言，是在可 防止對各微結晶矽6 3產生損傷的處理下，改善各氧化膜 (氧化矽膜）的膜質。 本紙張尺度適用中國國家標準（CNS ) A4規格（210Χ297公釐） 543209 A7 B7 五、發明説明（58) (請先閱讀背面之注意事項再填寫本頁) 氧化處理是由氧化過程所構成，亦即該氧化過程是藉 由急速熱氧化法，在可防止對各微結晶矽6 3產生損傷的 熱處理時間（以下稱爲「第1規定的熱處理時間」）下， 在各微結晶矽6 3的表面形成可產生電子的穿隧現象的膜 厚之氧化膜。在此氧化過程中，是利用燈退火裝置，在例 如氧氣的環境中，在第1規定的熱處理溫度（例如， 9 0 0 °C )下，只以第1規定的熱處理時間（例如，5分 鐘）來進行氧化。亦即，第1規定的熱處理時間與以往急 速熱氧化法的氧化過程的預定熱處理時間（1小時）相較 下’可大幅度的縮減。由製造後之電子源1 〇的電子放出 特性的測定結果可得知，第1規定的熱處理時間最好是設 定在5分鐘以內。但，使基板溫度上升至第1規定的熱處 理溫度爲止之升溫期間的升溫速度最好是設定成2 〇它/ s e c以上，更理想是1 5 0 °C / s e c以上。 經濟部智慧財產局員工消費合作社印製 氮化處理是由氮化過程所構成，亦即該氮化過程是藉 由急速熱氮化法，在可防止對各微結晶矽6 3產生損傷的 熱處理時間（以下稱爲「第2規定的熱處理時間」）下， 使各氧化膜氮化。在此氮化過程中，是利用燈退火裝置， 在例如N 2 ◦氣體的環境中，在第2規定的熱處理溫度（例 如’ 9 0 0 °C )下，只以第2規定的熱處理時間（例如， 5分鐘）來進行氮化。由製造後之電子源1 〇的電子放出 特性的測定結果可得知，第2規定的熱處理時間最好是設 定在5分鐘以內。但，使基板溫度上升至第2規定的熱處 理溫度爲止之升溫期間的升溫速度最好是設定成2 0 t / 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -61 - 543209 A7 B7 五、發明説明（59) s e c以上，更理想是1 5 0 °C / s e c以上。就實施形 態6而言，由於在氮化過程中是使用N 2 ◦氣體，因此可與 各氧化膜的氮化同時進行氧化。其結果，各絕緣膜5 2， 6 4會形成氮化氧膜（氮化氧矽膜）。並且，在氮化過程 中所使用的氣體並非只限於N2〇氣體，亦可使用NO氣體 ，NH3氣體，N2氣體等含氮的氣體。 若利用此製造方法，則於形成絕緣膜5 2 ，6 4的絕 緣膜形成過程中，可在能夠防止對各微結晶矽6 3產生損 傷的處理下，在各微結晶矽6 3的表面形成可產生電子的 穿隧現象的膜厚之氧化膜。並且，在晶粒5 1的表面形成 氧化膜，以及在能夠防止對各微結晶矽6 3產生損傷的處 理下，使各氧化膜氮化，而來改善膜質。因此，與以往藉 由急速熱氧化法在較長的熱處理時間（例如1小時）形成 各絕緣膜5 2，6 4時相較下，更能提高電子放出特性之 時效安定性。甚至，可縮短各絕緣膜5 2，6 4的形成時 所伴隨之高溫下的熱處理時間。因此，如第4 0圖之習知 的電子源1 0 〃所示，在絕緣性基板1 1上形成下部電極 1 2時，玻璃基板可使用與石英玻璃相較下價格較便宜的 無鹼玻璃基板或低鹼玻璃基板等之耐熱溫度較低的玻璃基 板，而使能夠謀求低成本化。並且，在實施形態6中，由 於可在同一裝置內進行氧化處理與氮化處理，因此可防止 在氧化處理與氮化處理之間附著雜質。 第2 6及2 7圖是表示分別測定由上述製造方法所製 成的電子源1 0的電子放出特性，及電子放出特性的時效 (請先閲讀背面之注意事項再填寫本頁) •裝·、 1T Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs of the 8th Industrial Cooperative Cooperative. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (21〇 > < 297mm) -45- 543209 A7 B7 V. Description of the Invention (43) ( Please read the precautions on the back before filling in this page.) Alternatively, instead of the drift layer 6, an insulating film (formed by the above-mentioned method for forming an insulating film) can be used to form: a lower electrode (conductive substrate), and a surface An electrode, and an electron source with an insulating layer between the lower electrode and the surface electrode. Such an electron source can improve the withstand voltage and life of the insulation as compared with the conventional M IM electric field emission type electron source. (Embodiment 4) Hereinafter, Embodiment 4 of the present invention will be described. In Embodiment 4, a conductive substrate is used in which a conductive layer 1 2 (for example, a metal film such as a chromium film or an ITO film) is provided on one surface of an insulating substrate 11 made of a glass substrate. By. When such a substrate is used (the conductive layer 1 2 is formed on one surface side of the insulating substrate 11), the area of the electron source can be increased and the cost can be reduced compared with a case where a semiconductor substrate is used as the conductive substrate. . The basic structure of the electron source 10 of the fourth embodiment is the same as that of the conventional electron source 10〃 shown in Fig. 40. That is, a non-doped polycrystalline sand layer 3 is formed on the conductive layer 12 on the insulating substrate i 丄 (the conductor layer is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs). A drift layer 6 composed of an oxidized porous $ crystalline sand layer is formed on the polycrystalline silicon layer 3. On the drift layer 6 is formed * Stomach_pole 7. The surface electrode 7 is made of a material having a smaller work function (for example, ^ ^. The thickness of the surface electrode 7 is set to 3 to 15 nm. The structure of 6 will be described later. It is shown in Figure 19G In the electron source i 〇, a part of the polycrystalline silicon layer 3 is interposed between the conductive layer 12 and the floating layer _ layer 6. However, the polycrystalline silicon layer 3 may be conductive without interposing the polycrystalline sand layer 3; This paper size is applicable to Chinese National Standard (CNS) A4 specification (210 × 297 mm) ------ 543209 A7 B7 V. Description of the invention (44) 1 A drift layer 6 is formed on top of the paper (Please read the precautions on the back first) (Fill in this page) The procedure for emitting electrons from the electron source 10 is the same as that of the conventional electron source 10 〃 shown in FIG. 40. That is, it is arranged so as to face the surface electrode 7. The collector electrode 21 (refer to FIG. 40), and a vacuum state is formed between the surface electrode 7 and the collector electrode 21. Furthermore, the surface electrode 7 can form a high potential (positive electrode) to the conductive layer 12 ' A DC voltage V ps is applied between the surface electrode 7 and the conductive layer 12. The surface electrode 7 can be applied to the surface electrode 7 by the collector electrode 21. In the method of forming a high potential (positive electrode), a DC voltage V c is applied between the collector electrode 21 and the surface electrode 7. As long as the respective DC voltages vp s and V c are appropriately set, electrons injected from the conductive layer 12 Then, it floats in the drift layer 6 and is released through the surface electrode 7. Hereinafter, the manufacturing method of the electron source 10 of the fourth embodiment will be described with reference to FIGS. 19A to 19D. First, on the insulating substrate 1 On one surface side of 1, a conductive layer 12 is formed by a sputtering method or the like to form a conductive substrate, and the structure shown in FIG. 19A is obtained. Printed by the Intellectual Property of the Ministry of Economic Affairs and the Consumer Cooperatives' On one surface side of the conductive substrate, a non-doped polycrystalline silicon layer 3 (semiconductor layer) having a predetermined film thickness (for example, 1 · 5 // m) is formed (formed), and FIG. 19B is obtained. As shown in the structure of the polycrystalline stone layer 3, for example, a CVD method (LPCVD method, plasma CVD method, catalyst CVD method, etc.), a sputtering method, and c SG (Continuous Grain Silicon) method, etc. After the undoped polycrystalline silicon layer 3 is formed, In the polycrystalline silicon layer, the paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -47- 543209 A7 B7 V. Description of the invention (45) (Please read the precautions on the back before filling this page) 3 A photomask material (not shown) is provided, and the photomask material is used to form a porous polycrystalline silicon layer 4 / (to be described later) only in a predetermined area. Then, an anodizing tank containing an electrolytic solution is prepared. The electrolytic solution is formed by mixing a 55 wt% aqueous solution of hydrogen fluoride and a mixed solution of ethanol in a 1: 1 manner. Thereafter, a platinum electrode (not shown) is used as the negative electrode, and the conductive layer 12 is used as the positive electrode. The polycrystalline silicon layer 3 is irradiated with light while being anodized under predetermined conditions. Thereby, a porous polycrystalline silicon layer 4 is formed. Then, the mask material was removed, and the structure shown in FIG. 19C was obtained. In the anodizing treatment of Embodiment 4, the period of the anodizing treatment, the amount of light irradiated on the surface of the polycrystalline silicon layer 3, and the constant current density are formed. However, the processing conditions may be appropriately changed (for example, the current density may be changed). Printed by the Intellectual Property of the Ministry of Economic Affairs and the Employees' Cooperatives after the anodizing process is completed, the porous polycrystalline silicon layer 4 is annealed at 400 ° C in N 2 gas with an inert gas, and then annealed to thereby A structure shown in FIG. 19D is obtained. Reference numeral 4 in Fig. 19D shows a porous polycrystalline silicon layer after annealing. Before annealing, the uppermost surface of the porous polycrystalline silicon layer 4 / is shown in Fig. 42 and the terminal is a hydrogen atom. In addition, fluorine atoms are taken into the porous polycrystalline silicon layer 4 /, and moisture is adsorbed on the surface of the porous polycrystalline silicon layer 4 /. Further, as shown in Fig. 20, by performing the above-mentioned annealing, the uppermost surface of the porous polycrystalline cleaved layer 4 after annealing is formed into a state in which gas atoms, fluorine atoms, and moisture are separated. In addition, the temperature at the time of annealing the porous polycrystalline silicon layer 4 / is appropriately set to 100 ° C. to 70 ° C. as long as it corresponds to the material of the conductive substrate or the material of the semiconductor layer. -48- This paper size applies Chinese National Standard (CNS) A4 specification (210X297mm) 543209 A7 B7 V. Description of invention (46) (Please read the precautions on the back before filling this page) The temperature range is sufficient. The inert gas used for annealing the porous polycrystalline silicon layer 4 / is not limited to the N 2 gas, and may be, for example, an Ar gas. Next, in a 1 (m ο 1) aqueous solution of sulfuric acid (Η 2 S〇4), annealed porous polycrystalline silicon layer 4 was subjected to an electrochemical oxidation treatment to form a drift layer 6 > The structure shown in Fig. 19E. In addition, the aqueous solution and the concentration at the time of performing electrochemical oxidation are not particularly limited. For example, an aqueous nitric acid solution can be used. After the electrochemical oxidation is completed, the drift layer 6 is annealed at 400 ° C in N 2 gas of an inert gas to obtain the structure shown in Fig. 19 F. Reference numeral 6 in Fig. 19F indicates the drift layer 6 after annealing. In addition, the temperature at the time of annealing the drift layer 6 > should be appropriately set to a temperature range of 100 ° C to 700 ° C corresponding to the material of the conductive substrate or the material of the semiconductor layer, etc. can. The inert gas used for annealing the drift layer 6 > is not limited to the ν 2 gas, and may be, for example, an Ar gas. The annealing of the drift layer 6 > is not necessarily performed in an inert gas, and may be performed in a vacuum. After the formation of the drift layer 6 /, the intellectual property of the Ministry of Economic Affairs and the Consumer Cooperative Co., Ltd. prints a surface electrode 7 made of a conductive thin film (for example, a gold thin film) on the drift layer 6 by, for example, evaporation, An electron source 10 having a structure shown in Fig. 19 G was obtained. Here, the method for forming the surface electrode 7 is not limited to the vapor deposition method. For example, a sputtering method may be used. The drift layer 6 of the electron source 10 manufactured by such a manufacturing method is the same as the drift layer 6 of the conventional electron source 10 shown in FIG. 39. The paper standard is applicable to the Chinese National Standard (CNS). A4 specifications (210X 297 mm) " -49- 543209 A7 B7 V. Description of the invention (47) (Please read the precautions on the back before filling this page) At least by: the grains of columnar polycrystalline silicon 5 1, And a thin silicon oxide film 52, a nanocrystalline unit of microcrystalline silicon 63, and a silicon oxide film 64. However, the electron source 10 of the fourth embodiment is different from the conventional electron source. That is, in the electron source 10, the porous polycrystalline silicon layer 4 formed by anodizing treatment in an inert gas is annealed, and the porous polycrystalline silicon layer is annealed by oxidation. Layer 4 > to form the drift layer 6 >. Then, the drift layer 6 > is annealed in an inert gas to form a surface electrode 7. Therefore, compared with the case where the porous polycrystalline silicon layer is oxidized in a state in which the porous polycrystalline stone layer absorbs moisture or the like immediately after the anodizing treatment, impurities such as hydrogen or fluorine contained in the drift layer 6 can be reduced compared to when the porous polycrystalline silicon layer is oxidized. Defects caused. In addition, a dense oxide film having a structure similar to the structure of Si 102 or a structure close to the structure of Si 102 can be formed. This can reduce the aging change of the electron emission efficiency, improve the insulation withstand voltage, and realize a highly reliable electron source 10. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs in the above-mentioned manufacturing method, since the porous polycrystalline silicon layer 4 after oxidation annealing is electro-chemically oxidized, it can be oxidized at a relatively low temperature. Porous polycrystalline silicon layer 4. However, the process of the porous polycrystalline silicon layer 4 after the oxidation annealing is not limited to the electrochemical oxidation process. For example, it may be a dry process using a thermal oxidation process using 02 gas, an oxidation process using 02 plasma, and an oxidation process using ozone. Since these processes are not wet processes like the electrochemical oxidation process, it is not necessary to perform annealing after the oxidation process. Therefore, the number of processes can be reduced compared to when performing electrochemical oxidation. In addition, the annealing process of the porous polycrystalline sand layer 4 / and the annealed porous polycrystalline silicon layer 4 in the lamp annealing device can be continuously performed in accordance with the Chinese National Standard (CNS) A4 specification ( 210X297 mm) -50-543209 Α7 Β7 V. Description of the invention (48) Chemical treatment. (Please read the precautions on the back before filling in this page.) In Embodiment 4, the conductive substrate is used: a conductive layer 1 2 is formed on one surface of an insulating substrate 1 (consisting of a glass substrate), However, as the conductive substrate, a metal substrate such as chromium may be used. Alternatively, a semiconductor substrate (for example, an n-type sand substrate having a resistivity close to that of a conductor, or a p-type sand substrate having an n-type region as a conductive layer formed on one side thereof) may be used. In addition to the glass substrate, the insulating substrate 11 can be a ceramic substrate or the like. In the fourth embodiment, the material of the surface electrode 7 is gold, but it is not limited to this. For example, aluminum, chromium, tungsten, nickel, platinum, etc. may be used. In addition, at least two thin film layers in the thickness direction may be laminated to form the surface electrode 7 °. When two thin film layers are used to form the surface electrode 7, the upper film material may be gold, for example. As the material of the lower film layer (film layer on the side of the drift layer 6), chromium, nickel, platinum, titanium, iridium, etc. can be used. Printed in Embodiment 4 by the Consumer Consumption Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, although the drift layer 6 is formed by an oxidized porous polycrystalline silicon layer, the oxidized porous monocrystalline silicon layer or other oxidized layers The porous semiconductor layer. (Embodiment 5) Hereinafter, Embodiment 5 of the present invention will be described. As shown in FIG. 2 F, in Embodiment 5, a conductive substrate is used: a conductive layer 1 2 (for example, a chromium film, titanium) is provided on one surface of an insulating substrate 11 made of a glass substrate. Metal film such as film, tungsten film, etc. The paper size applies to Chinese National Standard (CNS) A4 specification (210X 297 mm) -51-543209 A7 B7 V. Description of the invention (49) (Please read the precautions on the back before filling in this Page) or laminated films of multiple types of metal films, IT 0 films, etc.). When such a substrate is used (the conductive layer 1 2 is formed on one surface side of the insulating substrate 1 1), the area of the electron source can be increased and the cost can be reduced compared to when a semiconductor substrate is used as the conductive substrate. . The basic structure of the electron source 10 of the fifth embodiment is almost the same as the conventional electron source 101 shown in Fig. 40. That is, an undoped polycrystalline silicon layer 3 / (semiconductor layer) is formed on the conductive layer 12 on the insulating substrate 11. On the polycrystalline silicon layer 3, a drift layer 6 composed of an oxidized porous polycrystalline silicon layer is formed. A surface electrode 7 is formed on the drift layer 6. The surface electrode 7 is made of a material having a small work function (for example, 'gold'). The thickness of the surface electrode 7 is set to 10 to 15 nm. The structure of the drift layer 6 will be described later. In the electron source 10 shown in FIG. 21F, a part of the polycrystalline silicon layer 3 / is interposed between the conductive layer 12 and the drift layer 6. However, the drift layer 6 may be formed on the conductive layer 12 without interposing the polycrystalline silicon layer 3 /. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and the Consumers' Cooperative, the procedure for releasing electrons from the electron source 10 is the same as the conventional electron source 10 hours shown in Figure 40. That is, the collector electrode 2.1 (see FIG. 40) is disposed so as to face the surface electrode 7, and a vacuum state is formed between the surface electrode 7 and the collector electrode 21. Further, a direct voltage V p s is applied between the surface electrode 7 and the conductive layer 12 so that the surface electrode 7 can form a high potential (positive electrode) to the conductive layer 12. A DC voltage Vc is applied between the collector electrode 21 and the surface electrode 7 so that the collector electrode 21 can form a high potential to the surface electrode 7. As long as the DC voltages vp s and vc are properly set, the paper size of the guide is applicable to the Chinese National Standard (CNS) A4 specification (210 × 29? Mm) Explanation of the invention (50) The electrons injected in the electrical layer 12 will drift in the drift layer 6 and be released through the surface electrode 7. Hereinafter, a method of manufacturing the electron source 10 according to the fifth embodiment will be described with reference to FIGS. 2A to 2F. First, a conductive layer 12 is formed on one surface side of the insulating substrate 11 by a sputtering method or the like to form a conductive substrate, and a structure shown in FIG. 2A is obtained. Then, on one surface side of the conductive substrate (that is, on the conductive layer 12), a polycrystalline silicon layer 3 (made of polysilicon) 3 (formed by a film thickness) of a predetermined film thickness (for example, 1 · 5 // m) is formed (formed). A layered semiconductor layer made of polycrystalline silicon (a crystalline semiconductor), and a structure shown in FIG. 2B is obtained. As the method for forming the polycrystalline silicon layer 3, for example, a CVD method (LPCVD method, plasma CVD method, catalyst CVD method, etc.), a sputtering method, and a Continuous Grain Silicon method can be used. If the film-forming temperature is slightly lower than 60 ° C, the insulating substrate 11 can be made of, for example, an inexpensive glass substrate such as an alkali-free glass substrate, a low-alkali glass substrate, or a soda-lime glass substrate, thereby enabling cost reduction. After the non-doped polycrystalline silicon layer 3 is formed, in a N 2 gas of an inert gas, a predetermined annealing temperature (for example, 100 ° C to 7 0 0 ° C 'is preferably 50 0 ° C ~ 60 0 ° C) to perform annealing for a predetermined time (for example, 1 hour). This improves crystallinity, reduces defects, and obtains a structure shown in FIG. 21C. 3 / in Fig. 21C indicates the crystalline silicon layer after annealing. In the fifth embodiment, the annealed polycrystalline silicon layer 3 / constitutes a polycrystalline semiconductor layer. In addition, the emotional gas when annealing the polycrystalline silicon layer 3 is not limited to N 2 gas. For example, the paper size can be adapted to the Chinese National Standard (CNS) A4 specification (210X297 mm) (please read the back first) Please note this page before filling in this page) 543209 Α7 Β7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (51) Use of Ar gas. The annealing of the polycrystalline silicon layer 3 is not necessarily performed in an inert gas, and may be performed in a vacuum. When annealing is performed in an inert gas or in a vacuum, impurities that inhibit activity during annealing can be introduced into the polycrystalline silicon layer 3. The temperature for annealing the polycrystalline silicon layer 3 is preferably set to a relatively high temperature in consideration of the heat-resistant temperature of the material of the conductive substrate. After the annealing, a mask material (not shown) is provided on the polycrystalline silicon layer 3 ·. The mask material is used to form a porous polycrystalline silicon layer 4 (described later) only in a predetermined area. Then, an anodic oxidation treatment tank containing an electrolytic solution was prepared. The electrolytic solution was formed by mixing a 55 wt% hydrogen fluoride aqueous solution and ethanol in a 1: 1 manner. Thereafter, a platinum electrode (not shown) was used as the negative electrode, and the conductive layer 12 was used as the positive electrode. The polycrystalline silicon layer 3 was irradiated with light while performing anodization under predetermined conditions. Thereby, a porous polycrystalline silicon layer 4 is formed. Then, the photomask material was removed, and the structure shown in FIG. 21 D was obtained. In the anodizing treatment of Embodiment 5, the period of the anodizing treatment, the amount of light irradiated on the polycrystalline silicon layer 3 / surface, and the current density are made constant. However, the processing conditions may be appropriately changed (for example, the current density may be changed). After the anodic oxidation treatment is completed, the porous polycrystalline silicon layer 4 is subjected to electrochemical oxidation treatment in a 1 (m ο 1) sulfuric acid (H 2 S04) aqueous solution to form a drift layer 6 to obtain Figure 2 1 Ε structure. Here, the aqueous solution and the concentration at the time of performing electrochemical oxidation are not particularly limited. For example, an aqueous nitric acid solution can be used. (Please read the precautions on the back before filling this page) This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X 297 mm) -54- 543209 A7 ----- B7 V. Description of the invention (52) After the drift layer 6 is formed, a surface electrode 7 composed of a conductive thin film (for example, a gold thin film) is formed on the drift layer 6 by, for example, a vapor deposition method, and an electron source i shown in FIG. 2F is obtained. . Here, the method for forming the surface electrode 7 is not limited to the vapor deposition method, and, for example, a sputtering method may be used. The drift layer 6 of the electron source 10 manufactured by such a manufacturing method is the same as the drift layer 6 of the conventional electron source 10 not shown in FIG. 39, which is at least composed of the crystals of the columnar polycrystalline silicon. The grain 5 1 is composed of a thin silicon oxide film 5 2, nanocrystalline microcrystalline silicon 6 3, and a silicon oxide film 64. However, the electron source 10 of the fifth embodiment is different from the conventional electron source. That is, in the electron source 10, the drift layer 6 is formed by annealing the polycrystalline silicon layer 3 and then oxidizing the porous polycrystalline silicon layer 4 formed in the anodic oxidation treatment. Therefore, the polycrystalline semiconductor layer (polycrystalline silicon layer 3.) can be formed by annealing the layered semiconductor layer (polycrystalline silicon layer 3). This allows one side to be used at a lower temperature (below 60 ° C) To form a polycrystalline silicon layer 3 /, a compound layer or an alloy layer composed of a semiconductor and a metal is formed at the interface between the polycrystalline silicon layer 3 and the conductive layer 12, and the polycrystalline silicon layer 3 will almost form a crystal at the interface. Therefore, compared with the polycrystalline silicon layer 3 formed at a relatively low temperature, the resistance can be reduced. As a result, the barrier layer or the high-resistance layer between the polycrystalline silicon layer 3 and the conductive layer 12 can be reduced. An electron source 10 capable of improving the efficiency and reliability of electron emission can be provided. In addition, the electron source 10 manufactured by such a manufacturing method is the same as the conventional electron source 1 0 shown in FIG. 38 > Electronic release feature (please read the precautions on the back before filling this page)-Binding and ordering Printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economics This paper is printed in accordance with the Chinese National Standard (CNS) A4 specification (2.0 × 297 mm) -55- 543209 A7 B7 V. Description of the invention 53) The dependence of the degree of vacuum on sex is small, and the electrons can be released stably when the electrons are emitted. (Please read the precautions on the back before filling out this page.) Figure 2 A ~ C indicates The results of measuring the electron emission characteristics (radiated current I e, electron emission efficiency, etc.) of the known electron source 10 〃 (refer to FIG. 40) and the electron source 10 produced by the manufacturing method of the fifth embodiment. 2 2 Fig. A is a measurement result of a conventional electron source 1 0〃 (a conventional example: when annealing is not performed), and Fig. 2 B is an electron source 1 according to Embodiment 5 whose annealing temperature is 50 0 ° C. (Example 2) Measurement results. The horizontal axis of the 2nd A to C graphs represents the DC voltage V ps, and the vertical axis on the left side represents the current density. Α is the current density representing the diode current I ps, /? Is the current density representing the radiated current I e. The vertical axis on the right side of the 2 2 A to C graphs indicates the electron emission efficiency. R is the electron emission efficiency. The DC voltage Vc is constant (100 v). Emission efficiency is (I e / I ps) x 1 〇 [%] 値. The conventional example is also Examples 1 and 2. The deposition of the polycrystalline silicon layer 3 on the conductive substrate is performed by the plasma CVD method. From Figure C, it can be seen that compared with the conventional examples without annealing, the radiation current I e and the electron emission efficiency will be greatly improved. Moreover, if Example 1 and Example 2 are compared, In Example 2 where the annealing temperature is high, both the radiation current I e and the electron emission efficiency are improved. In addition, in the above manufacturing method, the polycrystalline silicon layer 3 (formed from polycrystalline silicon) is used. Layered semiconductor layer, but it can also be micro-structured. The paper size is applicable to Chinese National Standard (CNS) A4 (210X297 mm) -56-543209 Α7 Β7 5. Description of the invention (54) (Please read the precautions on the back before (Fill in this page) Semiconductor microcrystals such as crystalline silicon form layered semiconductor layers. In this case, it is only necessary to form a polycrystalline silicon layer 3 'by annealing to form a polycrystalline silicon layer after forming a layered semiconductor layer composed of microcrystalline silicon. In the fifth embodiment, a conductive substrate is used in which a conductive layer 12 is formed on one surface of an insulating substrate 1 (consisting of a glass substrate). However, a metal substrate such as chromium may be used as the conductive substrate. Alternatively, a semiconductor substrate (for example, an n-type silicon substrate having a resistivity close to that of a conductor, or a p-type silicon substrate having an n-type region as a conductive layer formed on one side) may be used. The insulating substrate 11 may be a ceramic substrate or the like other than a glass substrate. In the fifth embodiment, the material of the surface electrode 7 is gold, but it is not limited to this. For example, aluminum, chromium, tungsten, nickel, platinum, etc. may be used. The surface electrode 7 may be formed by laminating at least two thin film layers in the thickness direction. In this case, for the upper film layer material, for example, gold can be used, and for the lower film layer (film layer on the side of the drift layer 6), chromium, nickel, platinum, titanium, iridium, etc. can be used. Printed by the Intellectual Property of the Ministry of Economic Affairs and Consumer Cooperatives In the fifth embodiment, the drift layer 6 is formed by an oxidized porous polycrystalline sand layer, but it may also be formed by another oxidized porous semiconductor layer. (Embodiment 6) Hereinafter, Embodiment 6 of the present invention will be described. As shown in FIG. 23, in the electron source 10 of the sixth embodiment, the conductive substrate is a single crystal having a resistivity close to that of the conductor. The paper size of this paper applies the Chinese National Standard (CNS) A4 specification ( 210 × 297 mm) -57- 543209 A7 B7 V. Description of the invention (55) η-type silicon substrate (for example, a (100) substrate with a resistivity of about 0.01 Ω cm to 0.02 Dcm). (Please read the precautions on the back before filling this page) In this electron source 10, a drift layer 6 composed of an oxidized porous polycrystalline silicon layer is formed on the main surface side of the n-type silicon substrate 1 . A surface electrode 7 is formed on the drift layer 6. An ohmic electrode 2 is formed on the back surface of the n-type silicon substrate 1. The n-type silicon substrate 1 and the ohmic substrate 2 constitute a conductive layer 12. Therefore, the surface electrode 7 faces the lower electrode 12 and the drift layer 6 is interposed between the lower electrode 12 and the surface electrode 7. The surface electrode 7 can be made of, for example, a metal film composed of a metal having a small work function such as gold (Au), platinum (Pt), and chromium (C r), excellent oxidation resistance, and chemical stability, or a laminated film of these metal films form. The thickness of the surface electrode 7 may be set to a range of about 3 to 15 nm. The structure and function of the drift layer 6 are basically the same as those in the first embodiment. That is, the drift layer 6 is composed of at least: grain 5 1, silicon oxide film 5 2, most of the microcrystalline sand 6 3 printed by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and most of the oxide sand film 6 4 ( (See Figure 1). Further, in the drift layer 6, the surface of each of the crystal grains 51 is made porous', and the crystal state is maintained at the center portion of each crystal grain. Each crystal grain 51 extends in the thickness direction of the lower electrode 12. The aspect of the insulating film 5 2 ′ 6 4 will be described in detail in the description of the manufacturing method described later. As shown in Fig. 24, the electron source 10 of the sixth embodiment can cause electron emission in the same mode as the electron source 10 of the first or third embodiment. That is, between the surface electrode 7 and the lower electrode 12, the Chinese national standard (CNS) A4 specification (210X297 mm) is applied to the paper size of the surface. 58-543209 A7 ____B7 V. Description of the invention (56) The surface electrode 7 is used as The DC voltage Vp s is applied to the positive electrode, and the collector electrode is between the collector electrode 2 1 (for example, a transparent insulating film such as IT0 film) and the surface electrode 7 (please read the precautions on the back before filling this page). The electrode 21 is used as a positive electrode to apply a DC voltage Vc, whereby the electrons e injected into the drift layer 6 from the lower electrode 12 by thermal excitation will drift, pass through the surface electrode 7, and be placed in a vacuum. Hereinafter, a method of manufacturing the electron source 10 according to the sixth embodiment will be described with reference to FIGS. 2A to 25D. First, an ohmic electrode 2 is formed on the back surface of the n-type silicon substrate 1. Then, an undoped polycrystalline silicon layer 3 (semiconductor layer) is formed on the main surface (one surface) of the n-type silicon substrate 1, and the structure shown in FIG. 2A is obtained. As a method for forming the polycrystalline silicon layer 3, for example, a CVD method (LPCVD method, plasma CVD method, catalytic CVD method, etc.), a 'sputtering method', and a CSG (Continuous Grain Silicon) method can be used. After the non-doped polycrystalline silicon layer 3 is formed, the polycrystalline silicon layer 3 is formed by anodization using an electrolytic solution (to form a semiconductor layer to be printed by the Intellectual Property Department of the Ministry of Economic Affairs ^ 7M Industrial and Consumer Cooperative). ) Porous. Thereby, a porous polycrystalline sand layer 4 (porous semiconductor layer) is formed, and the structure shown in FIG. 2B is obtained. In addition, the porous polycrystalline silicon layer 4 formed during the anodizing process is composed of a plurality of polycrystalline silicon grains 5 1 (see FIG. 1) ′ and a plurality of microcrystalline sands 6 3 (see FIG. 1). Figure). In the anodizing process, an anodizing tank containing an electrolytic solution is used. The electrolytic solution is formed by mixing a 5 5 wt% hydrogen fluoride aqueous solution with ethanol in a 1: 1 manner. Then, while using the paper size of 500w 适 paper scale Shicai Guanjia County (CNS) A4 specifications (21GX297 mm) '-59-543209 Α7 Β7 V. Description of the invention (57) (Please read the precautions on the back first Fill out this page again) A light source composed of a tungsten filament lamp irradiates the surface of the polycrystalline silicon layer 3 with light, while a current flows between the lower electrode 12 and the cathode (consisting of a platinum electrode). This allows the polycrystalline silicon layer to be formed from the main surface to a predetermined depth (in the sixth embodiment, the depth does not reach the lower electrode 12 but may be set to a depth reaching the lower electrode 12). 3 made porous. . After the anodization process is completed, washing with ethanol is performed, and then an insulating film formation process is performed, that is, the surfaces of the individual crystal grains 51 and microcrystalline silicon 63 contained in the porous polycrystalline silicon layer 4 The insulating films 5 2 and 6 4 are formed. Thereby, the drift layer 6 containing the crystal grains 51, the microcrystalline silicon 63, and the silicon oxide films 52 and 64 is formed, and the structure shown in FIG. 25C is obtained. The process of forming the insulating film will be described later. After the drift layer 6 is formed, a surface electrode 7 made of a metal material (e.g., gold) is formed by a vapor deposition method or the like to obtain a structure shown in FIG. 2D. In the sixth embodiment, although the surface electrode 7 is formed by the vapor deposition method, the method of forming the surface electrode 7 is not limited to the vapor deposition method. For example, a sputtering method may be used. Printed by the Intellectual Property of the Ministry of Economic Affairs, Industrial and Consumer Cooperatives During the formation of the insulating film, oxidation and nitriding are performed. In terms of oxidation treatment, under the treatment that can prevent damage to each microcrystalline sand 63, a film thickness capable of generating a tunneling phenomenon of electrons is formed on the surface of each microcrystalline silicon 6 3 (than microcrystalline silicon 6 3 (The thickness of the crystal grains is even smaller) and the oxide film (silicon oxide film). In addition, in the case of nitriding treatment, the quality of each oxide film (silicon oxide film) is improved under a treatment that can prevent damage to each microcrystalline silicon 63. This paper size applies Chinese National Standard (CNS) A4 specification (210 × 297 mm) 543209 A7 B7 V. Description of the invention (58) (Please read the precautions on the back before filling this page) Oxidation treatment is composed of oxidation process. That is, this oxidation process is performed by a rapid thermal oxidation method at a heat treatment time (hereinafter referred to as "the first prescribed heat treatment time") that prevents damage to each microcrystalline silicon 63. An oxide film is formed on the surface to produce a film with a tunneling phenomenon. In this oxidation process, a lamp annealing device is used, in an environment such as oxygen, at the first prescribed heat treatment temperature (for example, 900 ° C), only for the first prescribed heat treatment time (for example, 5 minutes) ) For oxidation. That is, the heat treatment time specified in the first step can be significantly reduced compared to the heat treatment time (1 hour) scheduled in the conventional rapid thermal oxidation oxidation process. It can be seen from the measurement results of the electron emission characteristics of the electron source 10 after manufacture that the first prescribed heat treatment time is preferably set to within 5 minutes. However, the temperature increase rate during the temperature increase period until the substrate temperature is increased to the first predetermined heat treatment temperature is preferably set to 200 ° C / sec or more, and more preferably 150 ° C / sec or more. The nitriding process printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is composed of a nitriding process, that is, the nitriding process is a heat treatment that can prevent damage to each microcrystalline silicon 63 by rapid thermal nitriding. Each oxide film is nitrided at a time (hereinafter referred to as "the second predetermined heat treatment time"). In this nitriding process, a lamp annealing device is used, in an environment such as N 2 ◦ gas, at the second prescribed heat treatment temperature (for example, '900 ° C), only for the second prescribed heat treatment time ( For example, 5 minutes). It can be seen from the measurement results of the electron emission characteristics of the electron source 10 after manufacture that the second prescribed heat treatment time is preferably set to within 5 minutes. However, it is best to set the heating rate during the heating period up to the second prescribed heat treatment temperature to be 20 t / this paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -61-543209 A7 B7 5. Description of the invention (59) sec or more, more preferably 150 ° C / sec or more. In the sixth aspect, since N 2 gas is used in the nitriding process, it can be oxidized simultaneously with the nitriding of each oxide film. As a result, an oxygen nitride film (oxynitride silicon film) is formed in each of the insulating films 5 2 and 6 4. In addition, the gas used in the nitriding process is not limited to N2O gas, and nitrogen-containing gases such as NO gas, NH3 gas, and N2 gas can also be used. If this manufacturing method is used, during the formation of the insulating films 5 2 and 64, the microcrystalline silicon 63 can be formed on the surface of the microcrystalline silicon 63 under a process that can prevent damage to the microcrystalline silicon 63. An oxide film with a thickness that can cause electron tunneling. In addition, an oxide film is formed on the surface of the crystal grain 51, and each film is nitrided to prevent the microcrystalline silicon 63 from being damaged to improve the film quality. Therefore, compared with the conventional method of forming each of the insulating films 5 2 and 64 by a rapid thermal oxidation method (for example, 1 hour), the aging stability of the electron emission characteristics can be improved. Furthermore, the heat treatment time at a high temperature accompanying the formation of each of the insulating films 52, 64 can be shortened. Therefore, as shown in the conventional electron source 10〃 in FIG. 40, when the lower electrode 12 is formed on the insulating substrate 11, the alkali-free glass, which is cheaper than the quartz glass, can be used for the glass substrate. Glass substrates, such as substrates and low-alkali glass substrates, which have a low heat-resistant temperature, can reduce costs. Furthermore, in the sixth embodiment, since the oxidation treatment and the nitridation treatment can be performed in the same device, it is possible to prevent impurities from adhering between the oxidation treatment and the nitridation treatment. Figures 26 and 27 show the measurement of the electron emission characteristics of the electron source 10 produced by the above manufacturing method, and the aging of the electron emission characteristics (please read the precautions on the back before filling this page).

、1T 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -62- 543209 A7 B7 五、發明説明（60) 變化的結果。 (請先閲讀背面之注意事項再填寫本頁) 第2 8及2 9圖是表示分別測定在絕緣膜形成過程中 僅利用急速熱氮化法來進行熱處理（熱處理溫度爲9 0 0 °C，熱處理時間爲5分鐘）的比較例1之電子源的電子放 出特性，及電子放出特性的時效變化的結果。 第3 0及3 1圖是表示分別測定在絕緣膜形成過程中 僅利用急速熱氮化法來進行熱處理（熱處理溫度爲9 0 0 °C，熱處理時間爲6 0分鐘）的比較例2之電子源的電子 放出特性，及電子放出特性的時效變化的結果。 電子源1 0及比較例1 ，2之電子源的電子放出特性 的測定是如以下所示方式來進行。亦即，在真空處理室（ 未圖示）內導入電子源1 0及比較例1 ，2的電子源。然 後，如第3 8圖所示，對向於表面電極7來配置集極電極 2 1。並且，以表面電極7能夠對導電性層1 2形成高電 位之方式來施加直流電壓V p s ，而且以集極電極2 1倉g 夠對表面電極7形成高電位之方式來施加直流電壓V c。 經濟部智慧財產局員工消費合作社印製 第2 6，28及30圖是分別表示直流電壓Vc爲一 定1 0 0V，真空處理室內的真空度爲5x 1 0_5P a時 之電子放出特性的測定結果。在這些圖中，橫軸是表示直 流電壓Vp s ’縱軸是表不電流密度。「P」是表不二極 體電流I P s的電流密度，「Q」是表示放射電流I e的 電流密度。 弟2 7 ’ 2 9及3 1圖是分別表示直流電壓V c爲一 定1 0 0V，真空處理室內的真空度爲5χ 1 〇-5p ^時 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -63- 543209 Α7 Β7 五、發明説明（61 ) (請先閲讀背面之注意事項再填寫本頁) 之電子放出特性的時效變化的測定結果。在這些圖中，橫 軸是表示驅動開始後的時效，左側的縱軸是表示電流密度 ，右側的縱軸是表示電子放出效率。「P」是表示二極體 電流I p S的電流密度，「Q」是表示放射電流I e的電 流密度，「R」是表示電子放出效率。但，第2 9圖是以 直流電壓V p s爲一定1 1 V時的測定結果，第3 1圖是 以直流電壓V p s爲一定1 5 V時的測定結果。 由第2 6〜3 1圖可知，實施形態6的電子源1 〇與 比較例1 ，2的電子源相較下，可提升電子放出特性的時 效安定性。 在實施形態6中，雖是以η型矽基板1與歐姆電極2 來構成下部電極1 2，但亦可在絕緣性基板（例如，玻璃 基板，陶瓷基板等）的一表面側形成由金屬材料或摻雜高 濃度雜質的多結晶矽層所構成的下部電極1 2。並且，亦 可在陽極氧化處理過程中使η型矽基板1的表面側的一部 份形成多孔質化，藉此來形成多孔質半導體層的多孔質矽 層，且對此多孔質矽層進行絕緣膜形成過程。 經濟部智慧財產笱a(工消費合作社印製 (實施形態7 ) 以下，說明本發明之實施形態7。實施形態7之電子 源的製造方法與實施形態6之電子源的製造方法的不同點 是在於絕緣膜形成過程。因此，以下主要針對絕緣膜形成 過程進行說明。此實施形態7與實施形態6同樣的在絕緣 膜形成過程中進行氧化處理與氮化處理。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -64- 543209 A7 _ B7 五、發明説明（62) (請先閱讀背面之注意事項再填寫本頁) 實施形態7的氧化處理是由氧化過程與退火過程所構 成。在氧化過程中，是藉由電氣化學性的方法，在各微結 晶矽6 3的表面形成氧化膜。退火過程是在氧化過程後實 施，對各氧化膜進行退火。 具體而言，氧化過程是在陽極氧化處理過程終了後， 進行利用乙醇的洗淨。然後，利用電氣化學性的方法，亦 即使用放進有預定濃度（例如，lmo 1/1/=1M) 的硫酸水溶液之處理槽，使定電壓施加於下部電極1 2與 陰極（由白金電極所構成）之間。藉此，在各晶粒5 1及 各微結晶矽6 3的表面形成可產生電子的穿隧現象的膜厚 之氧化膜。並且，在氧化過程中所使用的電解液並非只限 於硫酸水溶液，例如亦可使用硝酸水溶液，王水等。或者 ，使用在有機溶煤中使溶質溶解後的電解液。 經濟部智慧財產^員工消費合作社印製 在退火過程中，例如利用燈退火裝置（即使是通常的 爐也無妨），在N 2〇氣體的環境中，以預定的退火溫度（ 例如4 5 0 °C )來只進行預定的退火時間（例如，χ小時 )。在此，退火溫度只要設定於7 0 0 °C以下即可，最好 是設定於6 0 0 °C以下。若利用電氣化學性的方法，則氧 化膜可於室溫形成。因此，可將退火溫度設定於7 0 〇 °C 以下，藉此與實施形態6相較下，可排除氧化過程之高溫 (例如，9 0 0 °C )下的熱處理。並且，因爲可將退火溫 度設定於7 0 0 °C以下，所以在將下部電極1 2形成於玻 璃基板等的絕緣性基板1 1上時（如第4 0圖所示之習知 的電子源1 0 〃），氧化過程不會影響玻璃基板。 本紙張尺度適用中國國家標準（CNS ) A4規格（2ΐ〇χ297公釐） -65 - 543209 A7 ___ B7 五、發明説明（63 ) (請先閱讀背面之注意事項再填寫本頁) 氮化處埋是由氮化過程所構成，該氮化過程是藉由急 M S氮化法，在可防止對各微結晶矽6 3產生損傷的熱處 ϊ里時間（以下，與實施形態1同樣的，稱爲第2規定的熱 處理時間）下，使各氧化膜氮化。在此氮化過程中，是利 用燈退火裝置，在例如Ν 2〇氣體的環境中，在第2規定的 熱處理溫度（例如，9 0 0 °C )下，只以第2規定的熱處 理時間（例如，5分鐘）來進行氮化。由製造後之電子源 1 0的電子放出特性的測定結果可得知，第2規定的熱處 理時間最好是設定在5分鐘以內。但，使基板溫度上升至 第2規定的熱處理溫度爲止之升溫期間的升溫速度最好是 設定成2〇°C/s e c以上，更理想是1 5(KC/s e c 以上。就實施形態7而言，由於在氮化過程中是使用N 2〇 氣體，因此可與各氧化膜的氮化同時進行氧化。其結果， 各絕緣膜5 2，6 4會形成氮化氧膜（氮化氧矽膜）。並 且’在氮化過程中所使用的氣體並非只限於N 2 ◦氣體，亦 可使用NO氣體，NH3氣體，N2氣體等含氮的氣體。 經濟部智慧財產^7a(工消費合作社印製 若利用實施形態7之電子源1 0的製造方法，則可取 得與實施形態6同樣的作用•效果。亦即，就此製造方法 而言，在絕緣膜形成過程中，可在能夠防止對各微結晶砂 6 3產生損傷的處理下，在各微結晶矽6 3的表面形成可 產生電子的穿隧現象的膜厚之氧化膜。並且，在晶粒5丄 的表面形成戰化膜’以及在能夠防止對各微結晶砂6 3產 生損傷的處理下，使各氧化膜氮化，而來改善膜質。因此 ，與以往藉由急速熱氧化法在較長的熱處理時間（例如工 I紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） " -- -66 - 543209 A7 B7 五、發明説明（64) (請先閲讀背面之注意事項再填寫本頁) 小時）形成各絕緣膜5 2，6 4時相較下，能提高電子放 出特性之時效安定性。甚至，可縮短各絕緣膜5 2，6 4 的形成時所伴隨之高溫下的熱處理時間。因此，如第4 0 圖之習知的電子源1 0 〃所示，在絕緣性基板1 1上形成 下部電極1 2時，玻璃基板可使用與石英玻璃相較下價格 較便宜的無鹼玻璃基板或低鹼玻璃基板等，而使能夠謀求 低成本化。並且，與實施形態1相較下，更可縮短絕緣膜 形成過程之高溫（例如，9 0 0 t )下的熱處理時間。又 ，因爲是藉由溼式的陽極氧化處理來形成各微結晶矽6 3 ，所以在陽極氧化處理後，可在不暴露於大氣中之下，在 氧化過程中，將氧化膜形成於各微結晶矽6 3及各晶粒 5 1的表面。因此，可防止在各微結晶矽6 3及各晶粒 5 1的表面形成自然氧化膜。藉此，在氧化過程中，可於 各微結晶矽6 3及各晶粒5 1的表面上形成良質的氧化膜 〇 經濟部智慧財產局員工消費合作社印製 第3 2及3 3圖是表示分別測定由實施形態7的製造 方法所製成的電子源1 0的電子放出特性，及電子放出特 性的時效變化的結果。 實施形態7之電子源1 〇的電子放出特性的測定是如 以下所示方式來進行。亦即，在真空處理室（未圖示）內 導入電子源1 0。然後，如第3 8圖所示，對向於表面電 極7來配置集極電極2 1。並且，以表面電極7能夠對導 電性層1 2形成高電位之方式來施加直流電壓v p s ，而 且以集極電極2 1能夠對表面電極7形成高電位之方式來 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -67 - 543209 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（65) 施加直流電壓v C。 第3 2圖是表示直流電壓Vc爲一定1 〇 0V，真空 處理室內的真空度爲5 X 1 〇 — 5 P a時之電子放出特性的 測定結果。在第3 2圖中，橫軸是表示直流電壓V p s ， 縱軸是表示電流密度。並且，「P」是表示二極體電流 I p s的電流密度，「Q」是表示放射電流I e的電流密 度。 第3 3圖是表示直流電壓v c爲一定1 0 0V，直流 電壓Vp s爲一定1 6V，真空處理室內的真空度爲5x 1 0 _ 5 P a時之電子放出特性的時效變化的測定結果。在 第3 3圖中，橫軸是表示驅動開始後的時效，左側的縱軸 是表示電流密度，右側的縱軸是表示電子放出效率。並且 ，「P」是表示二極體電流I p s的電流密度，「Q」是 表示放射電流I e的電流密度，「R」是表示電子放出效 率。 由第3 2圖及第3 3圖，以及表示實施形態6所述的 比較例1 ，2的測定結果的第2 8〜3 1圖可知，實施形 態7的電子源1 0與比較例1 ，2的電子源相較下，可提 升電子放出特性的時效安定性。 (實施形態8 ) 以下，說明本發明之實施形態8。實施形態8之電子 源的製造方法與實施形態6之電子源的製造方法的不同點 是在於絕緣膜形成過程。因此，以下主要針對絕緣膜形成 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -68- 543209 A7 B7 五、發明説明（66) 過程進行說明。此實施形態8與實施形態6同樣的在絕緣 膜形成過程中進行氧化處理與氮化處理。 (請先閲讀背面之注意事項再填寫本頁) 實施形態8的氧化處理是由：第1氧化過程，退火過 程，及第2氧化過程所構成。在第1氧化過程中，是藉由 電氣化學性的方法，在各微結晶矽6 3的表面形成氧化膜 。退火過程是在第1氧化過程後實施，對各氧化膜進行退 火。第2氧化過程是在退火過程後實施，藉由急速熱氧化 法在可防止對各微結晶矽6 3產生損傷的處理時間下，再 使各氧化膜氧化。 經濟部智慧財產局員工消費合作社印製 具體而言，第1氧化過程是在陽極氧化處理過程終了 後，進行利用乙醇的洗淨。然後，利用電氣化學性的方法 ，亦即使用放進有預定濃度（例如，1 m ο 1 / 1 /二1 Μ )的硫酸水溶液之處理槽，使定電壓施加於下部電極 1 2與陰極（由白金電極所構成）之間。藉此，在各晶粒 5 1及各微結晶矽6 3的表面形成可產生電子的穿隧現象 的膜厚之氧化膜。並且，在第1氧化過程中所使用的電解 液並非只限於硫酸水溶液，例如亦可使用硝酸水溶液，王 水等。或者，使用在有機溶煤中使溶質溶解後的電解液。 在退火過程中，例如利用燈退火裝置（即使是通常的 爐也無妨），在Ν2〇氣體的環境中，以預定的退火溫度（ 例如4 5 0 °C )來只進行預定的退火時間（例如，1小時 )。在此，退火溫度只要設定於7 0 0 °C以下即可，最好 是設定於6 0 0 °C以下。因爲可將退火溫度設定於7 〇 〇 C以下，所以在將下部電極1 2形成於玻璃基板等的絕緣 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -69- 543209 A7 B7 五、發明説明（67) 性基板1 1上時（如第4 0圖所示之習知的電子源1 0 〃 )，氧化過程不會影響玻璃基板。 (請先閲讀背面之注意事項再填寫本頁) 在第2氧化過程中，是利用燈退火裝置，例如在氧氣 的環境中，以第1規定的熱處理溫度（例如9 0 0 °C )來 只進行第1規定的熱處理時間（例如，5分鐘）的氧化。 在此，由製造後之電子源1 0的電子放出特性的測定結果 可得知，第1規定的熱處理時間最好是設定在5分鐘以內 。但，使基板溫度上升至第1規定的熱處理溫度爲止之升 溫期間的升溫速度最好是設定成2 0 °C / s e c以上，更 理想是1 5 0 t： / s e c以上。 經濟部智慧財產^7B(工消費合作社印製 氮化處理是由氮化過程所構成，該氮化過程是藉由急 速熱氮化法，在可防止對各微結晶砂6 3產生損傷的熱處 理時間（亦即，第2規定的熱處理時間）下，使各氧化膜 氮化。在此氮化過程中，是利用燈退火裝置，在例如N 2〇 氣體的環境中，在第2規定的熱處理溫度（例如，9 0 0 °C )下，只以第2規定的熱處理時間（例如，5分鐘）來 進行氮化。由製造後之電子源1 0的電子放出特性的測定 結果可得知，第2規定的熱處理時間最好是設定在5分鐘 以內。但，使基板溫度上升至第2規定的熱處理溫度爲止 之升溫期間的升溫速度最好是設定成2 0 t / s e c以上 ，更理想是1 5 0 °C / s e c以上。就實施形態8而言， 由於在氮化過程中是使用N 2 0氣體，因此可與各氧化膜的 氮化同時進行氧化。其結果，各絕緣膜5 2，6 4會形成 氮化氧膜（氮化氧矽膜）。並且，在氮化過程中所使用的 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -70- 543209 A7 ____ B7 五、發明説明（68) 氣體並非只限於Ν'2 ◦氣體，亦可使用n〇氣體，NH3氣 體，N2氣體等含氮的氣體。 (請先閱讀背面之注意事項再填寫本頁) 若利用實施形態8之電子源1 〇的製造方法，則可取 得與實施形態6同樣的作用•效果。亦即，在絕緣膜形成 過程中，可在能夠防止對各微結晶矽6 3產生損傷的處理 下’在各微結晶矽6 3的表面形成可產生電子的穿隧現象 的膜厚之氧化膜，且在晶粒5 1的表面形成氧化膜。然後 ，在能夠防止對各微結晶矽6 3產生損傷的處理下，使各 氧化膜氮化，而來改善膜質。因此，與以往藉由急速熱氧 化法在較長的熱處理時間（例如1小時）形成各絕緣膜 5 2 ’ 6 4時相較下，能提高電子放出特性之時效安定性 。甚至，可縮短各絕緣膜5 2，6 4的形成時所伴隨之高 溫下的熱處理時間。因此，如第4 〇圖之習知的電子源 1 0 〃所示，在絕緣性基板1 1上形成下部電極1 2時， 玻璃基板可使用與石英玻璃相較下價格較便宜的無鹼玻璃 基板或低鹼玻璃基板等，而使能夠謀求低成本化。並且， 與實施形態7的製造方法相較下，可降低各絕緣膜5 2， 經濟部智慧財產局員工消費合作社印製 6 4中的缺陷，提升電子放出特性。又，因爲是藉由溼式 的陽極氧化處理來形成各微結晶矽6 3，所以在陽極氧化 處理後，可在不暴露於大氣中之下，在第1氧化過程中， 將氧化膜形成於各微結晶矽6 3及各晶粒5 1的表面。因 此，可防止在各微結晶矽6 3及各晶粒5 1的表面形成自 然氧化膜。藉此，在第1氧化過程中，可於各微結晶矽 6 3及各晶粒5 1的表面上形成良質的氧化膜。 本紙張尺度適用中國國家標準（ CNS ) A4規格（210X297公釐） ' ' 一 543209 A7 B7 五、發明説明（69) (實施形態9 ) (請先閲讀背面之注意事項再填寫本頁) 以下，說明本發明之實施形態9。實施形態9之電子 源的製造方法與實施形態6之電子源的製造方法的不同點 是在於絕緣膜形成過程。因此，以下主要針對絕緣膜形成 過程進行說明。此實施形態9與實施形態6同樣的在絕緣 膜形成過程中進行氧化處理與氮化處理。 經濟部智慧財產局員工消費合作社印製 實施形態9的氧化處理是由氧化過程所構成，亦即該 氧化過程是藉由電氣化學性的方法，在各微結晶矽6 3的 表面形成氧化膜。就氧化過程而言，是在陽極氧化處理過 程終了後，進行利用乙醇的洗淨。然後，利用電氣化學性 的方法，亦即使用放進有預定濃度（例如，1 m ο 1 / 1 /二1 Μ )的硫酸水溶液之處理槽，使定電壓施加於下部 電極1 2與陰極（由白金電極所構成）之間。藉此，在各 晶粒5 1及各微結晶矽6 3的表面形成可產生電子的穿隧 現象的膜厚之氧化膜。並且，在氧化過程中所使用的電解 液並非只限於硫酸水溶液，例如亦可使用硝酸水溶液，王 水等。或者，使用在有機溶煤中使溶質溶解後的電解液。 退火處理是由退火過程所構成，該退火過程是在氮化 氣體的環境中針對各氧化膜進行退火者。在退火過程中， 是例如利用燈退火裝置（即使是通常的爐也無妨），在 Ν 2〇氣體的環境中，以預定的退火溫度（例如4 5 0 °C ) 來只進行預定的退火時間（例如，1小時）。在此，退火 溫度只要設定於7 0 0 °C以下即可，最好是設定於6 0 0 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -72- 543209 A7 B7 五、發明説明（7〇) (請先閲讀背面之注意事項再填寫本頁) C以下。因爲可將退火溫度设疋於7 0 0°C以下 所以在 將下部電極1 2形成於玻璃基板等的絕緣性基板i i上時 (如第4 0圖所示之習知的電子源1 〇 〃），氧化過程不 會影響玻璃基板。 經濟部智慧財產局員工消費合作社印製 若利用貫施形is 9之電子源1 〇的製造方法，則基本 上可取得與實施形態6同樣的作用•效果。亦即，在絕緣 膜形成過程中，可在能夠防止對各微結晶矽6 3產生損傷 的處理下，在各微結晶矽6 3的表面形成可產生電子的穿 隧現象的膜厚之氧化膜，且在晶粒5 1的表面形成氧化膜 。然後，在能夠防止對各微結晶矽6 3產生損傷的處理下 ，進行各氧化膜的缺陷補償，而來改善膜質。因此，與以 往藉由急速熱氧化法在較長的熱處理時間（例如1小時） 形成各絕緣膜5 2，6 4時相較下，能提高電子放出特性 之時效安定性。甚至，可縮短各絕緣膜5 2，6 4的形成 時所伴隨之高溫下的熱處理時間。因此，如第4 0圖之習 知的電子源1 0 〃所示，在絕緣性基板1 1上形成下部電 極1 2時，玻璃基板可使用與石英玻璃相較下價格較便宜 的無鹼玻璃基板或低鹼玻璃基板等，而使能夠謀求低成本 化。並且，與實施形態7相較下，可降低各絕緣膜5 2， 6 4中的缺陷，提升電子放出特性。又，因爲是藉由溼式 的陽極氧化處理來形成各微結晶矽6 3，所以在陽極氧化 處理後，可在不暴露於大氣中之下，在氧化過程中，將氧 化膜形成於各微結晶矽6 3及各晶粒5 1的表面。因此， 可防止在各微結晶矽6 3及各晶粒5 1的表面形成自然氧 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -73- 543209 Α7 _____ Β7 五、發明説明（71 ) 化膜°藉此，在氧化過程中，可於各微結晶矽6 3及各晶 粒5 1的表面上形成良質的氧化膜。 (請先閲讀背面之注意事項再填寫本頁) (實施形態1〇） 以下’說明本發明之實施形態1 〇。實施形態1 〇之 電子源的製造方法與實施形態6之電子源的製造方法的不 同點是在於絕緣膜形成過程。因此，以下主要針對絕緣膜 形成過程進行說明。此實施形態1 〇與實施形態6同樣的 在絕緣膜形成過程中進行氧化處理與氮化處理。 經濟部智慧財產局員工消費合作社印製 實施形態1 0的氧化處理是由第i氧化過程所構成， 亦即該第1氧化過程是藉由電氣化學性的方法，在各微結 晶砂6 3的表面形成氧化膜。就第1氧化過程而言，是在 陽極氧化處理過程終了後，進行利用乙醇的洗淨。然後， 利用電氣化學性的方法，亦即使用放進有預定濃度（例如 ’ 1 m ο 1 / 1 /二1 μ )的硫酸水溶液之處理槽，使定 電壓施加於下部電極1 2與陰極（由白金電極所構成）之 間。藉此’在各晶粒5 1及各微結晶矽6 3的表面形成可 產生電子的穿隧現象的膜厚之氧化膜。並且，在第1氧化 過程中所使用的電解液並非只限於硫酸水溶液，例如亦可 使用硝酸水溶液，王水等。或者，使用在有機溶煤中使溶 質溶解後的電解液。 又，退火處理是由退火過程所構成，該退火過程是在 氮化氣體的環境中針對各氧化膜進行退火者。在退火過程 中，是例如利用燈退火裝置（即使是通常的爐也無妨）， 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） -74- 543209 A7 B7 五、發明説明（72) (請先閲讀背面之注意事項再填寫本頁} 在N 2 ◦氣體的環境中，以預定的退火溫度（例如4 5 〇 °c )來只進行預定的退火時間（例如，1小時）。在此，退 火溫度只要設定於7 0 0 °C以下即可，最好是設定於 6 0 0 °C以下。因爲可將退火溫度設定於7 0 〇 °C以下， 所以在將下部電極1 2形成於玻璃基板等的絕緣性基板 1 1上時（如第4 0圖所示之習知的電子源1 〇 〃），氧 化過程不會影響玻璃基板。 實施形態1 0之製造方法的絕緣膜形成過程是具有： 一第2氧化過程；該第2氧化過程是在退火處理後， 藉由急速熱氧化法，在可防止對各微結晶矽6 3產生損傷 的熱處理時間下，再對各氧化膜進行氧化處理；及 一氮化過程；該氮化過程是在第2氧化過程後，藉由 急速熱氮化法，在可防止對各微結晶矽6 3產生損傷的熱 處理時間下，對各氧化膜進行氮化處理。 經濟部智慧財產局員工消費合作社印製 在第2氧化過程中，是利用燈退火裝置，例如在氧氣 的環境中，以第1規定的熱處理溫度（例如9 0 0 °C )來 只進行第1規定的熱處理時間（例如，5分鐘）的氧化。 在此，第1規定的熱處理時間與以往的急速熱氧化法之氧 化過程中所定的熱處理時間（1小時）相較下，可大幅度 地縮短。由製造後之電子源1 0的電子放出特性的測定結 果可得知，第1規定的熱處理時間最好是設定在5分鐘以 內。但，使基板溫度上升至第1規定的熱處理溫度爲止之 升溫期間的升溫速度最好是設定成2 0 °C / s e c以上， 更理想是1 5 0 °C / s e c以上。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -75- 543209 A7 B7 五、發明説明（73) (請先閱讀背面之注意事項再填寫本頁) 氮化處理是由氮化過程所構成，該氮化過程是藉由急 速熱氮化法，在可防止對各微結晶矽6 3產生損傷的熱處 理時間（亦即，第2規定的熱處理時間）下，使各氧化膜 氮化。在此氮化過程中，是利用燈退火裝置，在例如N 2〇 氣體的環境中，在第2規定的熱處理溫度（例如，9 0 0 °C )下，只以第2規定的熱處理時間（例如，5分鐘）來 進行氮化。由製造後之電子源1 0的電子放出特性的測定 結果可得知，第2規定的熱處理時間最好是設定在5分鐘 以內。但，使基板溫度上升至第2規定的熱處理溫度爲止 之升溫期間的升溫速度最好是設定成2 0 °C / s e c以上 ，更理想是1 5 0 °C / s e c以上。就實施形態1 〇而言 ，由於在氮化過程中是使用N 2 0氣體，因此可與各氧化膜 的氮化同時進行氧化。其結果，各絕緣膜5 2，6 4會形 成氮化氧膜（氮化氧矽膜）。並且，在氮化過程中所使用 的氣體並非只限於N 2 ◦氣體，亦可使用N〇氣體，N Η 3 氣體，Ν2氣體等含氮的氣體。 經濟部智慧財/Ι^7Μ工消費合作社印製 若利用實施形態1 0的製造方法，則基本上可取得與 實施形態6同樣的作用•效果。亦即，在絕緣膜形成過程 中，可在能夠防止對各微結晶矽6 3產生損傷的處理下， 在各微結晶矽6 3的表面形成可產生電子的穿隧現象的膜 厚之氧化膜，且在晶粒5 1的表面形成氧化膜。然後，在 能夠防止對各微結晶矽6 3產生損傷的處理下，使各氧化 膜氮化，而來改善膜質。因此，與以往藉由急速熱氧化法 在較長的熱處理時間（例如1小時）形成各絕緣膜5 2 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） 543209 A7 B7 五、發明説明（74 ) (請先閱讀背面之注意事項再填寫本頁) 6 4時相較下，能提高電子放出特性之時效安定性。甚至 ，可縮短各絕緣膜5 2，6 4的形成時所伴隨之高溫下的 熱處理時間。因此，如第4 0圖之習知的電子源1 〇 〃所 示，在絕緣性基板1 1上形成下部電極1 2時，玻璃基板 可使用與石英玻璃相較下價格較便宜的無鹼玻璃基板或低 鹼玻璃基板等，而使能夠謀求低成本化。並且，與實施形 態7的製造方法相較下，可降低各絕緣膜5 2，6 4中的 缺陷，提升電子放出特性。又，因爲是藉由溼式的陽極氧 化處理來形成各微結晶矽6 3，所以在陽極氧化處理後， 可在不暴露於大氣中之下，在第1氧化過程中，將氧化膜 形成於各微結晶矽6 3及各晶粒5 1的表面。因此，可防 止在各微結晶矽6 3及各晶粒5 1的表面形成自然氧化膜 。藉此，在第1氧化過程中，可於各微結晶矽6 3及各晶 粒5 1的表面上形成良質的氧化膜。 第3 4及3 5圖是表示分別測定由實施形態1 0的製 造方法所製成的電子源1 0的電子放出特性，及電子放出 特性的時效變化的結果。 經濟部智慧財產局員工消費合作社印製 電子源1 0的電子放出特性的測定是如以下所示方式 來進行。亦即，在真空處理室（未圖示）內導入電子源 1 0。然後，如第3 8圖所示，對向於表面電極7來配置 集極電極2 1。並且，以表面電極7能夠對導電性層1 2 形成尚電位之方式來施加直流電壓V p s ，而且以集極電 極2 1通夠對表面電極7形成高電位之方式來施加直流電 壓V c。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 543209 A7 B7 五、發明説明（75) 第3 4圖是表示直流電壓v c爲一定1 〇 〇v，真空 處理室內的真空度爲5x 1 〇— 5P a時之電子放出特性的 測疋結果。在桌3 4圖中，橫軸是表示直流電壓V p s ， 縱軸是表示電流密度。並且，「p」是表示二極體電流 I p s的電流密度，「Q」是表示放射電流I e的電流密 度。 第3 5圖是表示直流電壓vc爲一定1 〇 〇v，直流 電壓V p s爲一定1 5 V，真空處理室內的真空度爲5x 1 〇 — 5 P a時之電子放出特性的時效變化的測定結果。在 第3 5圖中，橫軸是表示驅動開始後的時效，左側的縱軸 是表示電流密度，右側的縱軸是表示電子放出效率。並且 ，「P」是表示二極體電流I p s的電流密度，「Q」是 表示放射電流I e的電流密度，「R」是表示電子放出效 率。 由第3 4圖及第3 5圖，以及表示實施形態6所述的 比較例1 ，2的測定結果的第2 8〜3 1圖可知，實施形 態1 0的電子源1 〇與比較例1 ，2的電子源相較下，可 提升電子放出特性的時效安定性。 (實施形態1 1 ) 以下’說明本發明之實施形態1 1。實施形態1 1之 電子源的製造方法與實施形態6之電子源的製造方法的不 同點是在於絕緣膜形成過程。因此，以下主要針對絕緣膜 形成過程進行說明。此實施形態1 1與實施形態6同樣的 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） (請先閲讀背面之注意事項再填寫本頁) 項再填办 經濟部智慧財產局員工消費合作社印製 -78- 543209 A7 B7 五、發明説明（76) 在絕緣膜形成過程中進行氧化處理與氮化處理。 (請先閱讀背面之注意事項再填寫本頁) 實施形態1 1的氧化處理是由第1氧化過程所構成， 亦即該第1氧化過程是藉由電氣化學性的方法，在各微結 晶砂6 3的表面形成氧化膜。就第1氧化過程而言，是在 陽極氧化處理過程終了後，進行利用乙醇的洗淨。然後， 利用電氣化學性的方法’亦即使用放進有預定濃度（例如 ’ 1 m ο 1 / 1 /二1 M )的硫酸水溶液之處理槽，使定 電壓施加於下部電極1 2與陰極（由白金電極所構成）之 間。藉此’在各晶粒5 1及各微結晶矽6 3的表面形成可 產生電子的穿隧現象的膜厚之氧化膜。並且，在第1氧化 過程中所使用的電解液並非只限於硫酸水溶液，例如亦可 使用硝酸水溶液，王水等。或者，使用在有機溶煤中使溶 質溶解後的電解液。 經濟部智慧財產局員工消費合作社印製 在退火過程中，例如利用燈退火裝置（即使是通常的 爐也無妨），在N 2〇氣體的環境中，以預定的退火溫度（ 例如4 5 0 °C )來只進行預定的退火時間（例如，1小時 )。在此，退火溫度只要設定於7 0 0 t以下即可，最好 是設定於6 0 0 t以下。若利用電氣化學性的方法，則氧 化膜可於室溫形成。因此，可將退火溫度設定於7 0 0 °C 以下，藉此與實施形態6相較下，可排除氧化過程之高溫 (例如，9 0 0 °C )下的熱處理。並且，因爲可將退火溫 度設定於7 0 0 °C以下，所以在將下部電極1 2形成於玻 璃基板等的絕緣性基板1 1上時（如第4 0圖所示之習知 的電子源1 0 〃），氧化過程不會影響玻璃基板。 -79- 本紙張尺度適用中國國家標準（cns ) A4規格（210X297公董 543209 A7 B7 五、發明説明（77) (請先閲讀背面之注意事項再填寫本頁) 在此氮化過程中，是利用燈退火裝置，在例如N 2〇氣 體的環境中，在第2規定的熱處理溫度（例如，9 〇 〇 c )下，只以第2規定的熱處理時間（例如，5分鐘）來進 行氮化。由製造後之電子源1 〇的電子放出特性的測定結 果可得知’第2規定的熱處理時間最好是設定在5分鐘以 內。但’使基板溫度上升至第2規定的熱處理溫度爲止之 升溫期間的升溫速度最好是設定成2 0 °C / s e c以上， 更理想是1 5 0 °C / s e c以上。就實施形態1 1而言， 由於在氮化過程中是使用N 2 ◦氣體，因此可與各氧化膜的 氮化同時進行氧化。其結果，各絕緣膜5 2，6 4會形成 氮化氧膜（氮化氧矽膜）。並且，在氮化過程中所使用的 氣體並非只限於N2 ◦氣體，亦可使用n ◦氣體，NH3氣 體，N2氣體等含氮的氣體。 經濟部智慧財產局員工消費合作社印製 若利用實施形態1 1之電子源1 〇的製造方法，則基 本上可取得與實施形態6同樣的作用•效果。亦即，就此 製造方法而言，在絕緣膜形成過程中，可在能夠防止對各 微結晶矽6 3產生損傷的處理下，在各微結晶矽6 3的表 面形成可產生電子的穿隧現象的膜厚之氧化膜，且在晶粒 5 1的表面形成氧化膜。然後，在能夠防止對各微結晶矽 6 3產生損傷的處理下，使各氧化膜氮化，而來改善膜質 。因此，與以往藉由急速熱氧化法在較長的熱處理時間（ 例如1小時）形成各絕緣膜5 2，6 4時相較下，能提高 電子放出特性之時效安定性。甚至，可縮短各絕緣膜5 2 ，6 4的形成時所伴隨之高溫下的熱處理時間。因此，如 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -80- 543209 A7 B7 五、發明説明（78) (請先閲讀背面之注意事項再填寫本頁} 第4 0圖之習知的電子源1 0 〃所示，在絕緣性基板1 1 上形成下部電極1 2時，玻璃基板可使用與石英玻璃相較 下價格較便宜的無鹼玻璃基板或低鹼玻璃基板等，而使能 夠謀求低成本化。並且，與實施形態7相較下，可降低各 絕緣膜5 2， 6 4中的缺陷，提升電子放出特性。又，因 爲是藉由溼式的陽極氧化處理來形成各微結晶矽6 3，所 以在陽極氧化處理後，可在不暴露於大氣中之下，在第1 氧化過程中，將氧化膜形成於各微結晶矽6 3及各晶粒 5 1的表面。因此，可防止在各微結晶矽6 3及各晶粒 5 1的表面形成自然氧化膜。藉此，在第1氧化過程中， 可於各微結晶矽6 3及各晶粒5 1的表面上形成良質的氧 化膜。 (實施形態1 2 ) 經濟部智慧財產笱員工消費合作社印製 以下，說明本發明之實施形態1 2。實施形態1 2之 電子源的製造方法與實施形態6之電子源的製造方法的不 同點是在於絕緣膜形成過程。因此，以下主要針對絕緣膜 形成過程進行說明。 在實施形態1 1的絕緣膜形成過程中，是藉由複數次 重複進行由氧化處理與氮化處理所構成的基本過程，來形 成各絕緣膜5 2，6 4。該氧化過程是藉由急速熱氧化法 ，在可防止對各微結晶矽（半導體微結晶）6 3產生損傷 的熱處理時間下進行，該氮化過程是藉由氧化處理後的急 速熱氮化法，在可防止對各微結晶矽（半導體微結晶） 本紙張尺度適用中國國家標準（CNS )八4規格（21〇Χ297公釐） -81 - 543209 A7 B7 五、發明説明（79) (請先閲讀背面之注意事項再填寫本頁) 6 3產生損傷的熱處理時間下進行。就氧化處理而言，是 在於氧化微結晶矽6 3的表面側，就氮化處理而言，是在 於改善膜質。 在此氧化過程中，是利用燈退火裝置，在例如氧氣的 環境中，在第1規定的熱處理溫度（例如，9 0 0 t )下 ’只以桌1規定的熱處理時間（例如，5分鐘）來進行氧 化。亦即，第1規定的熱處理時間與以往急速熱氧化法的 氧化過程的預定熱處理時間（1小時）相較下，可大幅度 的縮減。但，使基板溫度上升至第1規定的熱處理溫度爲 止之升溫期間的升溫速度最好是設定成2 0 °C / s e c以 上，更理想是1 50°C/s e c以上。 經濟部智慧財產局員工消費合作社印製 氮化過程是在藉由急速熱氧化法，在可防止對各微結 晶矽6 3產生損傷的熱處理時間（亦即，第2規定的熱處 理時間）下，使各氧化膜氮化。在此氮化過程中，是利用 燈退火裝置，在例如N 2〇氣體的環境中，在第2規定的熱 處理溫度（例如，9 0 0 °C )下，只以第2規定的熱處理 時間（例如，5分鐘）來進行氮化。但，使基板溫度上升 至第2規定的熱處理溫度爲止之升溫期間的升溫速度最好 是設定成2 0 °C / s e c以上，更理想是1 5 0 °C / s e c以上。就實施形態1 2而言，由於在氮化過程中是 使用N 2 ◦氣體，因此可與各氧化膜的氮化同時進行氧化。 其結果，各絕緣膜5 2，6 4會形成氮化氧膜（氮化氧矽 膜）。並且，在氮化過程中所使用的氣體並非只限於N 2〇 氣體，亦可使用NO氣體，NH 3氣體，N2氣體等含氮的 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -82- 543209 A7 ___ B7 五、發明説明（8〇) 氣體。 (請先閱讀背面之注意事項再填寫本頁) 若利用此製造方法，則基本上可取得與實施形態6同 樣的作用•效果。亦即，與以往藉由急速熱氧化法在較長 的熱處理時間（例如1小時）形成各絕緣膜5 2，6 4時 相較下，可提高電子放出特性之時效安定性。甚至，可縮 短各絕緣膜5 2，6 4的形成時所伴隨之高溫下的熱處理 時間。因此，如第4 0圖之習知的電子源1 〇 〃所示，在 玻璃基板等的絕緣性基板1 1上形成下部電極1 2時，玻 璃基板可使用價格較便宜的無鹼玻璃基板或低鹼玻璃基板 等，而使能夠謀求低成本化。並且，與實施形態7的製造 方法相較下，可降低各絕緣膜5 2，6 4中的缺陷，而使 能夠提高電子放出特性。 (實施形態1 3 ) 以下，說明本發明之實施形態1 3。 經濟部智慧財產局員工消費合作社印製 如第3 6 F圖所示，在實施形態1 3中，導電性基板 是使用：在由玻璃基板所構成的絕緣性基板1 1的一表面 上設置導電性層1 2 (例如，鉻膜等的金屬膜或I τ ◦膜 等）者。在使用如此的基板（在絕緣性基板1 1的一表面 側形成導電性層1 2 )時，與使用半導體基板來作爲導電 性基板時相較下，可使電子源大面積化及低成本化。 實施形態1 3之電子源1 0的基本構成是大致與第 4 0圖所示之以往的電子源1 〇 〃相同。亦即，在絕緣性 基板1 1上的導電性層1 2上形成有無摻雜質的多結晶矽 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ~ " 543209 A7 B7 五、發明説明（81) 層3 (半導體層）。在多結晶矽層3上形成有由氧化後白勺 (請先閱讀背面之注意事項再填寫本頁} 多孔質多結晶矽層所構成的飄移層6。在飄移層6上g $ 有表面電極7。表面電極7是使用功函數較小的材料（_ 如’金）。表面電極7的厚度是設定成3〜lSrim。；^ 關飄移層6的構造會在往後敘述。在第3 6 F圖所示自勺胃 子源1 0中，會使多結晶砂層3的一部份介於導電性層 1 2與飄移層6之間。但，亦可不介在多結晶矽層3，而 於導電性層1 2上形成飄移層6。 使電子從電子源1 0放出的程序是與第4 0圖所示之 以往的電子源1 0 〃時相同。亦即，以能夠對向於表面電 極7之方式來配設集極電極2 1 (參照第4 0圖），且使 經濟部智慧財產局員工消費合作社印製 表面電極7與集極電極2 1之間形成真空狀態。又，以表 面電極7能夠對導電性層1 2形成高電位（正極）之方式 ’在表面電極7與導電性層1 2之間施加直流電壓V p s 。並且，以集極電極2 1能夠對表面電極7形成高電位之 方式，在集極電極2 1與表面電極7之間施加直流電壓 V c。只要適當的設定各直流電壓v p s ，v c ，則由導 電性層1 2注入的電子便會飄移於飄移層6內，經由表面 電極7而釋放出。 以下，一邊參照第3 6A〜3 6 F圖，一邊說明實施 形態1 3之電子源1 0的製造方法。 首先，在絕緣性基板1 1的一表面側，藉由濺鍍法等 來設置導電性層1 2，而形成導電性基板，而取得第 3 6 A圖所示的構造。然後，在導電性基板的一表面側（ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） "" " -84- 543209 A7 B7 五、發明説明（82 ) 亦即，在導電性層1 2上），形成（成膜）預定的膜厚（ 例如1 · 5 // m )之無摻雜質的多結晶矽層3 (半導體層 (請先閲讀背面之注意事項再填寫本頁) )，而取得第3 6 B圖所示的構造。就多結晶矽層3的成 膜方法而言，例如可使用：C V D法（L P C V D法，電 漿C V D法，觸媒C V D法等），濺鍍法，及C S G ( Continuous Grain Silicon)法等。由於成膜溫度爲設定於 6 0 〇 °C以下，因此絕緣性基板1 1可例如使用無鹼玻璃 基板，低鹼玻璃基板，鹼石灰玻璃基板等較便宜的玻璃基 板，而使能夠謀求低成本化。 經濟部智慧財產苟員工消費合作社印製 其次，在形成無摻雜質的多結晶矽層3之後，供以只 在預定領域形成後述的多結晶矽層4之罩材（圖示省略） 。然後，使用一放進有電解液的陽極氧化處理槽（該電解 液是由：以1比1方式來混合5 5 w t %的氟化氫水溶液 與乙醇之混合液所形成），以白金電極（圖中未示）作爲 負極，及以導電性層1 2作爲正極，一邊對多結晶矽層3 進行光照射，一邊以預定的條件來進行陽極氧化。藉此來 形成多孔質多結晶砂層4。然後，除去光罩材，而取得第 3 6 C圖所示的構造。在實施形態1 3的陽極氧化處理中 ’是使陽極氧化處理的期間，及照射於多結晶砂層3表面 的光里’以及電流密度形成一定。但，此處理條件亦可適 當的予以變更（例如，使電流密度變化）。 在陽極氧化處理終了後，在1 ( m 〇 1 )的硫酸（ Η 2 S〇4 )水溶液中，針對多孔質多結晶矽層4進行電氣 化學性的氧化處理，而來形成飄移層6 -，取得第3 6 d 85- 543209 A7 B7 五、發明説明（83) 圖所示的構造。在此，進行電氣化學性的氧化時之水溶液 及濃度，並無特別加以限定。例如，可使用硝酸水溶液等 (請先閱讀背面之注意事項再填寫本頁) 〇 在形成飄移層6 >之後，在導電性基板的一表面側的 最上表面（在此爲飄移層6 /的表面）照射氫基，而來使 存在於飄移層6 >中的缺陷鈍化（passivation)(不動態化） ，取得第3 6 E圖所示的構造。第3 6 E圖中的6是表示 氫基照射後的飄移層。在往飄移層6 /的表面照射氫基的 氫基照射過程中，是將氫電漿中的氫基照射於導電性基板 的一表面側的最上表面。因此，可謀求氫基照射過程之製 程溫度的低溫化（6 0 0 °C以下的製程溫度）。並且，可 容易對應於電子源1 0的大面積化。而且，可對氫基照射 高頻或微波等來使電漿化，藉此使能夠適用於可產生氫電 漿的一般半導體製造裝置，謀求低成本化。 經濟部智慧財產局員工消費合作社印製 在氫電漿照射過程終了後，在飄移層6上，例如藉由 蒸鍍法來形成由導電性薄膜（例如，金薄膜）所構成的表 面電極7，取得第3 6 F圖所示構造的電子源1 〇。在此 ，表面電極7的形成方法，並非只限於蒸鍍法，例如亦可 使用濺鍍法。 藉由如此的製造方法而製成的電子源1 0的飄移層6 與第1圖所示的電子源1 0的電場飄移層6同樣的，至少 由：柱狀多結晶矽的晶粒5 1 ，及薄氧化矽膜5 2，及奈 米單位的微結晶矽6 3，以及氧化矽膜6 4所構成。但， 就實施形態1 3的電子源1 0而言，會在氧化多孔質多結 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -86- 543209 A7 B7 五、發明説明（84) (請先閲讀背面之注意事項再填寫本頁) 晶砂層4後所形成的飄移層6 /的表面照射氫基，而來形 成飄移層6。因此，可使存在於飄移層6 -中的缺陷（例 如’氧化矽膜5 2，6 4或微結晶矽6 3表面的缺陷）鈍 化（不動態化）或減少。藉此，可取得能夠提高電子放出 特性及可靠度的電子源1 〇。以如此製造方法所製成的電 子源1 0與第3 8圖所示的習知電子源1 〇 >同樣的，電 子放出特性的真空度依賴性小，且電子放出時不會發生跳 動現象，可安定地放出電子。 經濟部智慧財產局8工消費合作社印製 在上述電子源1 〇的製造方法中，雖是在氧化多孔質 多結晶矽層4後形成飄移層6 >之後進行氫電漿照射處理 ’但亦可在陽極氧化處理前進行氫電漿照射過程。或者在 陽極氧化處理後進行氫電漿照射過程。並且，在氫氣中的 退火處理中，與上述氫基照射同樣的，可使存在於飄移層 6 >中的缺陷（例如，氧化矽膜5 2，6 4或微結晶矽 6 3表面的缺陷）鈍化（不動態化）或減少。在此，退火 溫度只要設定於7 0 0 °C以下即可，最好是設定於6 0 0 °C以下。並且，氫氣可爲1 〇 〇%者，或者與其他氣體混 合的混合氣體。 在上述電子源1 0的製造方法中，雖是在氧化多孔質 多結晶矽層4後形成飄移層6 >之後進行氫電漿照射處理 ，但亦可在陽極氧化處理前進行氫電漿照射過程。或者在 陽極氧化處理後進行氫電漿照射過程。 又，在上述電子源1 0的製造方法中，雖是在氫電漿 照射過程中，將氫電漿中的氫基照射於導電性基板的一表 -87 - 本纸張尺度適用中國國家標準（CNS ) A4規格（21〇><297公釐） 543209 A7 B7 五、發明説明（85) (請先閲讀背面之注意事項再填寫本頁) 面側的最上表面，但如第3 7圖所示，亦可將利用氫氣與 鎢製觸媒體4 2的接觸分解反應而產生的氫基照射於導電 性基板的一表面側的最上表面（就第3 7圖所示的例子而 言，爲飄移層6 >的表面）。此情況，觸媒體4 2是藉由 來自電流源（未圖示）的電流來加熱至適當的溫度。導電 性基板是設置於基板夾具4 1上，且藉由加熱器（未圖示 )來適當地將基板夾具4 1加熱至1 0 0〜7 0 0°C。但 ，當導電性基板爲使用：在由玻璃基板所構成的絕緣性基 板1 1的一表面形成導電性層1 2者時，必須以絕緣性基 板1 1的溫度不會達到該絕緣性基板1 1的耐熱溫度之方 式來設定基板夾具4 1的溫度。 經濟部智慧財產笱員工消費合作社印製 因此，在氫基照射過程中，在將氫電漿中的氫基照射 於導電性基板的一表面側的最上表面時，有可能電漿會損 傷飄移層6。但，在氫基照射過程中，若氫基爲利用氫氣 的觸媒體4 2而分解產生者，則可防止此情況發生。因此 ，與照射氫電漿中的氫基時相較下，可取得能夠提高電子 放出特性及可靠度的電子源1 0。此外，在氫基照射過程 中，亦可將根據氫氣的熱分解或光分解而產生的氫基照射 於導電性基板的一表面側。此情況，與照射氫電漿中的氫 基時相較下，同樣可取得能夠提高電子放出特性及可靠度 的電子源1 0。 在實施形態1 3中，導電性基板是使用：在絕緣性基 板1 1 (由玻璃基板所構成）的一表面上形成導電性層 1 2者，但導電性基板亦可使用鉻等的金屬基板。或者， 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -88- 543209 Α7 ________________ Β7 五、發明説明（86) 亦可使用半導體基板（例如，阻抗率較接近導體的阻抗率 之n型砂基板，或一面側形成有作爲導電性層的η型領域 (請先閲讀背面之注意事項再填寫本頁) 之ρ型砂基板等）。又，絕緣性基板1 1除了玻璃基板以 外，可使用陶瓷基板等。 在貫施形態1 3中，表面電極7的材料是採用金，但 並非只限於此，例如亦可使用鋁，鉻，鎢，鎳，白金等。 又，亦可以層S於厚度方向的至少2層薄膜層來構成表面 電極7 °在以2層的薄膜層來構成表面電極7時，就上層 的薄膜層材料而言，例如可使用金等，就下層的薄膜層（ 飄移層6側的薄膜層）材料而言，可使用鉻，鎳，白金， 鈦，銥等。 經濟部智慧財產局員工消費合作社印製 在實施形態1 3中，雖是藉由氧化後的多孔質多結晶 砂層來構成飄移層6，但亦可以氮化後的多孔質單結晶矽 層或氧化·氮化後的多孔質多結晶矽層來構成飄移層6。 或者以其他氧化，氮化或氧化•氮化後的多孔質半導體層 來構成。當飄移層6爲氮化後的多孔質多結晶矽層時，只 要以氮化多孔質多結晶矽層4的過程來取代氧化多孔質多 結晶矽層4的過程即可。此情況，各氧化矽膜5 2，64 皆會形成氮化矽膜。當飄移層6爲氧化•氮化後的多孔質 多結晶矽層時，只要以氧化•氮化多孔質多結晶矽層4的 過程來取代氧化多孔質多結晶矽層4的過程即可。此情況 ，各氧化砂膜5 2，6 4皆會形成氧化•氮化砂膜。 以上，雖是說明有關本發明的特定實施形態，但除此 以外亦可實施其他多數的變形例及修正例。換言之，本發 本纸張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐） -89- 543209 A7 B7 五、發明説明（87) 明並非只限定於上述實施形態，只要不脫離申請專利範圍 的主旨範圍，亦可實施其他實施形態。 (請先閲讀背面之注意事項再填寫本頁) 〔產業上之利用可能性〕 如以上所述，本發明之電場放射型電子源及其製造方 法，特別是有助於提高電子放出效率及可靠度，適用於平 面光源，平面顯示器元件，及固體真空裝置等等之電子源 〔圖面之簡單說明〕 第1圖是表示本發明之實施形態1的電子源的要部槪 略剖面圖。 第2圖是表示第1圖之電子源的動作。 第3 A〜D圖是表示第1圖之電子源及其製造途中之 中間體的槪略剖面圖，爲該電子源的製造方法。 第4圖是表示有關第1圖之電子源及比較例的光致發 光測定的發光頻譜，爲對光致發光強度的波長之特性。 經濟部智慧財產局工消費合作社印製 第5圖是表示有關第1圖之電子源及比較例的X線光 電子分光分析法之構成元素的深度方向的分布圖，爲對原 子濃度的深度之特性。 第6A，B圖是分別表示第1圖之電子源的電子放出 原理。 第7 A，B圖是分別表示比較例之電子源的電子放出 原理。 -90- 本紙悵尺度適用中國國家標準（CNS ) A4規格（210X29?公釐） 543209 A 7 B7 五、發明説明（88) 第8 A，B圖是分別表示第1圖之電子源及比較例的 電子源的氧化過程。 (請先閱讀背面之注意事項再填寫本頁) 第9圖是表示第1圖之電子源及比較例的電子源的電 子放出效率的時效變化。 第1 0圖是表示第1圖之電子源及比較例的電子源的 電子放出特性。 第1 1圖是表示本發明之實施形態2的電子源的動作 〇 ^ 第12A〜D圖是表示第11圖之電子源及其製造途 中之中間體的槪略剖面圖，爲該電子源的製造方法。 第1 3圖是表示本發明之實施形態3的電子源的要部 槪略剖面圖。 第1 4圖是表示第1 3圖之電子源的動作。 第15A〜D圖是表示第13圖之電子源及其製造途 中之中間體的槪略剖面圖，爲該電子源的製造方法。 第1 6圖是表示本發明之實施形態3的電子源的絕緣 薄膜的形成手法，爲熱處理溫度的時效變化。 經濟部智慧財產苟員工消費合作社印製 第1 7圖是表示使用於第1 3圖之絕緣薄膜的形成的 熱處理裝置的槪略構成圖。 第1 8圖是表示升溫脫離氣體質量分析法的測定結果 圖，爲對離子電流的加熱溫度之變化特性。 第1 9 A〜G圖是表示本發明之實施形態4的電子源 及其製造途中之中間體的槪略剖面圖，爲該電子源的製造 方法。 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇Χ297公釐） 543209 A7 B7 五、發明説明（89) 第2 0圖是表示退火處理後之多孔質多結晶矽層的最 上表面的終端形態。 (請先閱讀背面之注意事項再填寫本頁) 第2 1 A〜F圖是表示本發明之實施形態5的電子源 及其製造途中之中間體的槪略剖面圖，爲該電子源的製造 方法。 第2 2 A〜C圖是分別表示在無退火處理的情況時， 以5 〇 〇 °C來進行退火處理時及以5 5 0 t：來進行退火處 理時，對電子源的電流密度的直流電壓V p s之變化特性 〇 第2 3圖是表示本發明之實施形態6的電子源的要部 槪略剖面圖。 第2 4圖是表示第2 3圖之電子源的動作。 第2 5 A〜D圖是表示本發明之實施形態6的電子源 及其製造途中之中間體的槪略剖面圖，爲該電子源的製造 方法。 第2 6圖是表示對第2 3圖之電子源的電流密度的直 流電壓V p s變化特性。 經濟部智慧財產局員工消費合作社印製 第2 7圖是表示對第2 3圖之電子源的電流密度的時 間之變化特性。 第2 8圖是表示對比較例之電子源的電流密度的直流 電壓V P s之變化特性。 第2 9圖是表示對比較例（與第2 8圖同一比較例） 之電子源的電流密度的時間之變化特性。 第3 0圖是表示對另一比較例之電子源的電流密度的 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -92- 543209 A7 __ B7 五、發明説明（9〇) 直流電壓V p s之變化特性。 (請先閱讀背面之注意事項再填寫本頁) 第3 1圖是表示對該比較例（與第3 0圖同一比較例 )之電子源的電流密度的時間之變化特性。 第3 2圖是表示對本發明之實施形態7的電子源的電 流密度的直流電壓V p s之變化特性。 第3 3圖是表示對本發明之實施形態7的電子源的電 流密度的時間之變化特性。 第3 4圖是表示對本發明之實施形態1 〇的電子源的 電流密度的直流電壓V p s之變化特性。 第3 5圖是表示對本發明之實施形態1 〇的電子源的 電流密度的時間之變化特性。 第3 6 A〜F圖是表示本發明之實施形態1 3的電子 源及其製造途中之中間體的槪略剖面圖，爲該電子源的製 造方法。 第3 7圖是表示本發明之實施形態1 3的電子源的製 造方法之氫基照射過程的處理手法。 第3 8圖是表示習知之電子源的動作圖。 經濟部智慧財產局員工消費合作社印製 第3 9圖是表示習知之電子源的要部槪略剖面圖。 第4 0圖是表示另一習知之電子源的動作圖。 第4 1圖是表示急速加熱法之熱處理溫度的時效變化 〇 第4 2圖是表示陽極氧化處理後之多孔質多結晶砂層 的最上表面的終端形態。 第4 3圖是表示急速加熱法後之多孔質多結晶砂層的 -93- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 543209 Α7 Β7 五、發明説明（91 ) 最上表面的終端形態。 (請先閱讀背面之注意事項再填寫本頁) 〔符號之說明〕 1 : η型矽基板 2 :歐姆電極 3 :多結晶矽層 4，4 / :多孔質多結晶矽層 6，6 —，6 〃 ：飄移層 7 :表面電極 1 0、1 0 / 、1〇〃：電子源 11:絶縁性基板 1 2 :下部電極（導電性層） 21:集極電極 4 1 :處理室 4 2 :放射温度計 4 3 :水分検出手段 4 4 :控制手段 經濟部智慧財產¾員工消費合作社印製 5 1 :晶粒 5 2、6 4 :薄絶縁膜（氧化矽膜） 6 3 :微結晶矽 8 0 :氧分子 8 1 :氧原子 π 0 :初期電子放出効率 τ :時定数 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -94- 543209 A7 B7 五、發明説明（92 ), 1T Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to Chinese National Standard (CNS) A4 (210X 297 mm) -62- 543209 A7 B7 V. DESCRIPTION OF THE INVENTION (60) The result of the change.  (Please read the precautions on the back before filling in this page) Figures 2 8 and 2 9 show that the heat treatment was performed only by rapid thermal nitridation during the formation of the insulating film (heat treatment temperature is 90 ° C, Heat treatment time is 5 minutes), the electron emission characteristics of the electron source of Comparative Example 1, And the results of aging changes in electron emission characteristics.  Figures 30 and 31 show the measurement of heat treatment using only rapid thermal nitridation during the formation of the insulation film (heat treatment temperature is 900 ° C, The electron emission characteristics of the electron source of Comparative Example 2 of the heat treatment time of 60 minutes), And the results of aging changes in electron emission characteristics.  Electron source 10 and Comparative Example 1, The measurement of the electron emission characteristics of the electron source 2 was performed as follows. that is, Introduction of an electron source 10 and a comparative example 1 into a vacuum processing chamber (not shown), 2 electron source. Then, As shown in Figure 3 8 A collector electrode 21 is arranged to face the surface electrode 7. and, The direct-current voltage V p s is applied so that the surface electrode 7 can form a high potential to the conductive layer 12, In addition, the DC voltage V c is applied in such a manner that the collector electrode 21 is large enough to form a high potential to the surface electrode 7.  Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Figures 28 and 30 show that the DC voltage Vc is a certain 100V, Measurement results of electron emission characteristics when the vacuum degree in the vacuum processing chamber is 5x 1 0_5P a. In these figures, The horizontal axis indicates the DC voltage Vp s' and the vertical axis indicates the current density. "P" is the current density representing the diode current I P s, "Q" represents the current density of the radiated current I e.  Brother 2 7 ′ 2 9 and 31 respectively show that the DC voltage V c is a certain 10 0V, The vacuum degree in the vacuum processing chamber is 5 × 1 0-5p ^ This paper size applies to China National Standard (CNS) A4 specifications (210X297 mm) -63- 543209 Α7 Β7 V. Description of the Invention (61) (Please read the precautions on the back before filling out this page) The measurement results of the aging change of the electron emission characteristics. In these figures, The horizontal axis indicates the aging after the start of the drive, The vertical axis on the left is the current density, The vertical axis on the right indicates the electron emission efficiency. "P" is the current density representing the diode current I p S, "Q" is the current density of the radiated current I e, "R" indicates the electron emission efficiency. but, Figure 29 shows the measurement results when the DC voltage V p s is constant 1 1 V. Figure 31 shows the measurement results when the DC voltage V p s is constant at 15 V.  As can be seen from Figures 2 6 to 31, Electron source 10 of Embodiment 6 and Comparative Example 1, Compared with the electron source of 2 It can improve the aging stability of the electron emission characteristics.  In the sixth embodiment, Although the lower electrode 12 is composed of the n-type silicon substrate 1 and the ohmic electrode 2, However, it can also be used on insulating substrates (for example, Glass base board, A ceramic substrate or the like) has a lower electrode 12 made of a metal material or a polycrystalline silicon layer doped with a high concentration of impurities on one surface side. and, During the anodizing process, a part of the surface side of the n-type silicon substrate 1 may be made porous. In this way, a porous silicon layer of a porous semiconductor layer is formed, An insulating film formation process is performed on the porous silicon layer.  Ministry of Economic Affairs Intellectual Property 笱 a (printed by the Industrial and Consumer Cooperatives (Embodiment 7)), A seventh embodiment of the present invention will be described. The manufacturing method of the electron source according to the seventh embodiment is different from the manufacturing method of the electron source according to the sixth embodiment in the insulating film formation process. therefore, The following description mainly focuses on the process of forming an insulating film. In the seventh embodiment, similarly to the sixth embodiment, an oxidation treatment and a nitridation treatment are performed during the formation of the insulating film.  This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) -64- 543209 A7 _ B7 V. Description of the Invention (62) (Please read the precautions on the back before filling this page) The oxidation treatment of Embodiment 7 is composed of an oxidation process and an annealing process. During the oxidation process, Is by electrochemical methods, An oxide film is formed on the surface of each microcrystalline silicon 63. The annealing process is performed after the oxidation process, Each oxide film is annealed.  in particular, The oxidation process is after the end of the anodizing process.  Wash with ethanol. then, Using electrochemical methods, That is, using a predetermined concentration (for example, lmo 1/1 / = 1M) sulfuric acid aqueous solution processing tank, A constant voltage is applied between the lower electrode 12 and the cathode (made of a platinum electrode). With this, An oxide film is formed on the surface of each of the crystal grains 5 1 and each of the microcrystalline silicon 6 3 with a thickness that can cause electron tunneling. and, The electrolyte used in the oxidation process is not limited to aqueous sulfuric acid. For example, an aqueous nitric acid solution can also be used, Wang Shui et al. Or An electrolytic solution obtained by dissolving a solute in an organic molten coal is used.  Printed by the Intellectual Property of the Ministry of Economic Affairs ^ Employee Consumer Cooperative During the annealing process, For example, using a lamp annealing device (even a normal furnace is fine), In the environment of N 2〇 gas, Perform a predetermined annealing time at a predetermined annealing temperature (for example, 450 ° C) (for example, χ hours). here, The annealing temperature can be set below 70 ° C. It is best to set it below 60 ° C. If we use electrochemical methods, The oxide film can be formed at room temperature. therefore, The annealing temperature can be set below 70 ° C, Compared with the sixth embodiment, Eliminates high temperatures from oxidation processes (e.g., 9 0 0 ° C). and, Because the annealing temperature can be set below 700 ° C, Therefore, when the lower electrode 12 is formed on an insulating substrate 11 such as a glass substrate (the conventional electron source 10 〃 shown in FIG. 40), The oxidation process does not affect the glass substrate.  This paper size applies to China National Standard (CNS) A4 (2ΐ〇χ297mm) -65-543209 A7 ___ B7 V. Description of the Invention (63) (Please read the notes on the back before filling out this page) Nitriding process is composed of nitriding process, The nitriding process is performed by the rapid M S nitriding method. In a hot place that prevents damage to each microcrystalline silicon 63, the time (hereinafter, Similar to the first embodiment, Called the second prescribed heat treatment time), Each oxide film is nitrided. During this nitriding process, Is the use of lamp annealing equipment, In an environment such as N 2 O gas, At the heat treatment temperature specified in Section 2 (for example, 9 0 0 ° C), Use only the heat treatment time specified in Section 2 (for example, 5 minutes). It can be known from the measurement results of the electron emission characteristics of the electron source 10 after manufacture, The second prescribed heat treatment time is preferably set to within 5 minutes. but, The temperature increase rate during the temperature increase period until the substrate temperature is increased to the second predetermined heat treatment temperature is preferably set to 20 ° C / s e c or more. More preferably, it is 15 (KC / s e c or more. In the seventh embodiment, Since N 2 gas is used in the nitriding process, Therefore, the oxidation can be performed simultaneously with the nitridation of each oxide film. the result,  Each insulating film 5 2 6 4 An oxygen nitride film (oxynitride silicon film) is formed. And the gas used in the nitriding process is not limited to N 2 gas, NO gas can also be used, NH3 gas, Nitrogen-containing gas such as N2 gas.  Intellectual Property of the Ministry of Economic Affairs ^ 7a (Printed by the Industrial and Consumer Cooperative) If the manufacturing method of the electron source 10 of Embodiment 7 is used, The same functions and effects as those of the sixth embodiment can be obtained. that is, For this manufacturing method, During the formation of the insulating film, Under the treatment that can prevent damage to each microcrystalline sand 6 3, An oxide film is formed on the surface of each microcrystalline silicon 63 to a thickness such that electron tunneling can occur. and, Under the treatment of forming a war film on the surface of the crystal grains 5 ′ and preventing damage to each microcrystalline sand 63, Nitride each oxide film, To improve film quality. Therefore, Compared with the previous method of rapid thermal oxidation in a longer heat treatment time (for example, the paper size of the industrial I applies the Chinese National Standard (CNS) A4 specification (210X297 mm)) "  --66-543209 A7 B7 Five, Description of the invention (64) (Please read the precautions on the back before filling this page) hours) to form each insulating film 5 2 ， At 6 o'clock, It can improve the aging stability of the electron emission characteristics. even, Can shorten each insulating film 5 2 The formation of 6 4 is accompanied by heat treatment time at high temperature. therefore, As shown in the conventional electron source 1 0 图 in Fig. 40, When the lower electrode 12 is formed on the insulating substrate 11, As the glass substrate, an alkali-free glass substrate or a low-alkali glass substrate, which is cheaper than quartz glass, can be used. This enables cost reduction. and, Compared with the first embodiment, It can also shorten the high temperature of the insulation film formation process (for example, 9 0 0 t). Again, Because each microcrystalline silicon 6 3 is formed by a wet anodizing process, So after anodizing, Without exposure to the atmosphere, During the oxidation process, An oxide film is formed on the surface of each microcrystalline silicon 63 and each crystal grain 51. therefore, It is possible to prevent the formation of a natural oxide film on the surfaces of each of the microcrystalline silicon 63 and each of the crystal grains 51. With this, During the oxidation process, A good oxide film can be formed on the surface of each microcrystalline silicon 6 3 and each crystal grain 51. Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figures 3 2 and 3 3 show the measurements made by the seventh embodiment. The electron emission characteristics of the electron source 10 made by the method, And the result of aging changes of electron emission characteristics.  The measurement of the electron emission characteristics of the electron source 10 of Embodiment 7 was performed as shown below. that is, An electron source 10 is introduced into a vacuum processing chamber (not shown). then, As shown in Figure 3 8 The collector electrode 21 is arranged to face the surface electrode 7. and, The direct-current voltage v p s is applied so that the surface electrode 7 can form a high potential to the conductive layer 12. And in order that the collector electrode 21 can form a high potential to the surface electrode 7, the Chinese standard (CNS) A4 specification (210X297 mm) is applied to this paper scale -67-543209 A7 B7 System five, DESCRIPTION OF THE INVENTION (65) A DC voltage v C is applied.  Fig. 32 shows that the DC voltage Vc is constant 100V, Measurement results of electron emission characteristics when the vacuum degree in the vacuum processing chamber was 5 X 1 0-5 Pa. In Figure 32, The horizontal axis represents the DC voltage V p s,  The vertical axis represents the current density. and, "P" is the current density representing the diode current I p s, "Q" indicates the current density of the radiated current I e.  Figure 33 shows that the DC voltage v c is constant at 100V. The DC voltage Vp s is a certain 16V, Measurement results of the aging change of the electron emission characteristics when the vacuum degree in the vacuum processing chamber is 5x 1 0 _ 5 Pa. In Figure 3 3, The horizontal axis indicates the aging after the start of the drive, The vertical axis on the left is the current density, The vertical axis on the right indicates the electron emission efficiency. And, "P" is the current density representing the diode current I p s, "Q" is the current density representing the radiated current I e, "R" indicates the electron emission efficiency.  From Figure 32 and Figure 33, And Comparative Example 1 described in Embodiment 6, It can be seen from the second 8 to 31 of the measurement result of 2 that The electron source 10 of Embodiment 7 and Comparative Example 1, Compared with the electron source of 2 It can improve the aging stability of electron emission characteristics.  (Embodiment 8) Hereinafter, Embodiment 8 of the present invention will be described. The manufacturing method of the electron source according to the eighth embodiment is different from the manufacturing method of the electron source according to the sixth embodiment in the insulating film formation process. therefore, The following is mainly for the formation of insulating films (please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 specifications (210X297 mm) -68- 543209 A7 B7 V. Invention Description (66) The process is explained. In the eighth embodiment, similarly to the sixth embodiment, an oxidation treatment and a nitridation treatment are performed during the formation of the insulating film.  (Please read the precautions on the back before filling this page) The oxidation treatment of Embodiment 8 is made by: The first oxidation process, Annealing process, And the second oxidation process. During the first oxidation process, Is by electrochemical methods, An oxide film is formed on the surface of each microcrystalline silicon 63. The annealing process is performed after the first oxidation process, Anodize each oxide film. The second oxidation process is performed after the annealing process, By the rapid thermal oxidation method, at a processing time that can prevent damage to each microcrystalline silicon 63, Each oxide film is oxidized.  Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs The first oxidation process is after the end of the anodizing process, Wash with ethanol. then, Using electrochemical methods, That is, using a predetermined concentration (for example, 1 m ο 1/1/2 1) of sulfuric acid aqueous solution processing tank, A constant voltage is applied between the lower electrode 12 and the cathode (made of a platinum electrode). With this, An oxide film is formed on the surface of each of the crystal grains 51 and each of the microcrystalline silicon 6 3 with a film thickness which can cause electron tunneling. and, The electrolytic solution used in the first oxidation process is not limited to an aqueous sulfuric acid solution. For example, an aqueous nitric acid solution can also be used, Wang Shui et al. or, An electrolytic solution obtained by dissolving a solute in an organic molten coal is used.  During the annealing process, For example, using a lamp annealing device (even a normal furnace is fine), In the environment of N2〇 gas, Perform a predetermined annealing time at a predetermined annealing temperature (for example, 450 ° C) (for example, 1 hour ). here, The annealing temperature can be set below 70 ° C. It is best to set it below 60 ° C. Because the annealing temperature can be set below 700 ° C, Therefore, the lower electrode 12 is formed on a glass substrate or the like. Description of the invention (67) When the flexible substrate 11 is mounted on the substrate (as shown in FIG. 40, the conventional electron source 10 〃), The oxidation process does not affect the glass substrate.  (Please read the notes on the back before filling this page) During the second oxidation process, Is using a lamp annealing device, For example, in an oxygen environment, Use the first heat treatment temperature (for example, 900 ° C) for only the first heat treatment time (for example, 5 minutes).  here, It can be known from the measurement results of the electron emission characteristics of the electron source 10 after manufacture, The first prescribed heat treatment time is preferably set within 5 minutes. but, It is preferable to set the heating rate during the temperature rising period up to the first predetermined heat treatment temperature at 20 ° C / sec or more. More ideal is 1 5 0 t:  / s e c or more.  Intellectual property of the Ministry of Economic Affairs ^ 7B (printed by the Industrial and Consumer Cooperative) Nitriding process is composed of nitriding process, The nitriding process is performed by rapid thermal nitridation. During the heat treatment time (i.e., Heat treatment time specified in Section 2), Each oxide film is nitrided. During this nitriding process, Is using a lamp annealing device, In an environment such as N 2〇 gas, At the heat treatment temperature specified in 2 (for example, 9 0 0 ° C), Only for the heat treatment time specified in Section 2 (for example, 5 minutes) for nitriding. It can be known from the measurement results of the electron emission characteristics of the electron source 10 after manufacture, The second prescribed heat treatment time is preferably set to within 5 minutes. but, It is preferable to set the temperature increase rate during the temperature increase period of increasing the substrate temperature to the second predetermined heat treatment temperature to be 20 t / s e c or more. More preferably, it is above 150 ° C / sec. In the eighth embodiment,  Since N 2 0 gas is used in the nitriding process, Therefore, the oxidation can be performed simultaneously with the nitriding of each oxide film. the result, Each insulating film 5 2 6 4 will form an oxygen nitride film (oxynitride silicon film). and, The paper size used in the nitriding process is in accordance with China National Standard (CNS) A4 (210X297 mm) -70- 543209 A7 ____ B7 V. DESCRIPTION OF THE INVENTION (68) Gas is not limited to N'2 ◦ gas, You can also use n〇 gas, NH3 gas, Nitrogen-containing gas such as N2 gas.  (Please read the precautions on the back before filling out this page.) If the manufacturing method of the electron source 10 in Embodiment 8 is used, The same functions and effects as those of the sixth embodiment can be obtained. that is, During the formation of the insulating film, Under the treatment capable of preventing damage to each of the microcrystalline silicon 63, an oxide film having a film thickness capable of generating a tunneling phenomenon of electrons is formed on the surface of each of the microcrystalline silicon 63, An oxide film is formed on the surface of the crystal grain 51. Then Under the treatment capable of preventing damage to each microcrystalline silicon 63, Nitride each oxide film, To improve film quality. therefore, Compared with the conventional method of forming each insulating film 5 2 ′ 6 4 by a rapid thermal oxidation method over a long heat treatment time (for example, 1 hour), Can improve the aging stability of electron emission characteristics. even, Can shorten each insulating film 5 2 The formation of 6 4 is accompanied by heat treatment time at high temperature. therefore, As shown in the conventional electron source 10 〃 in FIG. When the lower electrode 12 is formed on the insulating substrate 11,  As the glass substrate, an alkali-free glass substrate or a low-alkali glass substrate, which is less expensive than quartz glass, can be used. This enables cost reduction. and,  Compared with the manufacturing method of the seventh embodiment, Can reduce each insulating film 5 2  Defects in the printing of employee cooperatives by the Intellectual Property Bureau of the Ministry of Economic Affairs, Improve electron emission characteristics. also, Because each microcrystalline silicon 6 3 is formed by wet anodization, So after anodizing, Without exposure to the atmosphere, During the first oxidation process,  An oxide film is formed on the surface of each microcrystalline silicon 63 and each crystal grain 51. Therefore, It is possible to prevent the formation of a natural oxide film on the surface of each microcrystalline silicon 63 and each crystal grain 51. With this, During the first oxidation process, A good oxide film can be formed on the surface of each microcrystalline silicon 6 3 and each crystal grain 51.  This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) '' '' 543209 A7 B7 V. Description of the Invention (69) (Embodiment 9) (Please read the precautions on the back before filling out this page) The following, A ninth embodiment of the present invention will be described. The manufacturing method of the electron source of the ninth embodiment is different from the manufacturing method of the electron source of the sixth embodiment in the process of forming an insulating film. therefore, The following description mainly focuses on the process of forming an insulating film. In the ninth embodiment, similarly to the sixth embodiment, an oxidation treatment and a nitridation treatment are performed during the formation of the insulating film.  Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs The oxidation treatment of Embodiment 9 is composed of an oxidation process. That is, the oxidation process is by electrochemical method, An oxide film is formed on the surface of each microcrystalline silicon 63. In terms of the oxidation process, After the end of the anodizing process, Wash with ethanol. then, Using electrochemical methods, That is, using a predetermined concentration (for example, 1 m ο 1/1/2 1) of sulfuric acid aqueous solution processing tank, A constant voltage is applied between the lower electrode 12 and the cathode (made of a platinum electrode). With this, An oxide film having a film thickness capable of causing electron tunneling is formed on the surfaces of each of the crystal grains 51 and each of the microcrystalline silicon 63. and, The electrolytic solution used in the oxidation process is not limited to aqueous sulfuric acid. For example, an aqueous nitric acid solution can also be used, Wang Shui et al. or, An electrolytic solution obtained by dissolving a solute in an organic molten coal is used.  The annealing process is composed of the annealing process. This annealing process is performed by annealing each oxide film in an environment of a nitride gas. During the annealing process,  For example, using a lamp annealing device (even a normal furnace is fine), In the environment of Ν 2〇 gas, Perform only a predetermined annealing time at a predetermined annealing temperature (e.g., 450 ° C) (e.g., 1 hour). here, The annealing temperature can be set below 70 ° C. It is best to set at 6 0 0 This paper size is applicable to China National Standard (CNS) A4 specification (210X 297 mm) -72- 543209 A7 B7 V. Description of the Invention (70) (Please read the notes on the back before filling this page) C The following. Since the annealing temperature can be set below 700 ° C, when the lower electrode 12 is formed on an insulating substrate ii such as a glass substrate (the conventional electron source 1 shown in FIG. 40) ), The oxidation process does not affect the glass substrate.  Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Basically, the same functions and effects as those of the sixth embodiment can be obtained. that is, During the formation of the insulating film, Under the treatment that can prevent damage to each microcrystalline silicon 63, An oxide film having a film thickness which can cause electron tunneling is formed on the surface of each microcrystalline silicon 63. An oxide film is formed on the surface of the crystal grain 51. then, Under the treatment that can prevent damage to each microcrystalline silicon 63, Perform defect compensation for each oxide film, To improve film quality. therefore, In the past, each insulating film 5 2 was formed by a rapid thermal oxidation method over a long heat treatment time (for example, 1 hour). At 6 o'clock, It can improve the aging stability of electron emission characteristics. even, Can shorten each insulating film 5 2 The formation of 6 4 is accompanied by heat treatment time at high temperature. therefore, As shown in the conventional electron source 10 0 of Fig. 40, When the lower electrode 12 is formed on the insulating substrate 11, As the glass substrate, an alkali-free glass substrate or a low-alkali glass substrate, which is less expensive than quartz glass, can be used. This enables cost reduction. and, Compared with Embodiment 7, Can reduce each insulating film 5 2  6 4 Defects, Improve electron emission characteristics. also, Because each microcrystalline silicon 6 3 is formed by wet anodization, So after anodizing, Without exposure to the atmosphere, During the oxidation process, An oxide film is formed on the surface of each microcrystalline silicon 63 and each crystal grain 51. therefore,  Can prevent the formation of natural oxygen on the surface of each microcrystalline silicon 6 3 and each grain 51 1 This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) -73- 543209 Α7 _____ Β7 V. DESCRIPTION OF THE INVENTION (71) Chemical film During the oxidation process, A good oxide film can be formed on the surface of each microcrystalline silicon 63 and each crystal grain 51.  (Please read the precautions on the back before filling in this page) (Embodiment 10) The following description will describe Embodiment 10 of the present invention. The manufacturing method of the electron source according to the tenth embodiment differs from the manufacturing method of the electron source according to the sixth embodiment in the insulating film formation process. therefore, The following mainly describes the process of forming the insulating film. In the tenth embodiment, similarly to the sixth embodiment, an oxidation treatment and a nitridation treatment are performed during the formation of the insulating film.  Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs The oxidation treatment of Form 10 is composed of the i-th oxidation process.  That is, the first oxidation process is by an electrochemical method, An oxide film is formed on the surface of each microcrystalline sand 63. For the first oxidation process, After the end of the anodizing process, Wash with ethanol. then,  Using electrochemical methods, That is, a treatment tank containing a sulfuric acid aqueous solution having a predetermined concentration (for example, ′ 1 m ο 1/1/2 1 μ) is used, A constant voltage is applied between the lower electrode 12 and the cathode (made of a platinum electrode). Thereby, an oxide film having a film thickness capable of causing a tunneling phenomenon of electrons is formed on the surfaces of each of the crystal grains 51 and each of the microcrystalline silicon 63. and, The electrolytic solution used in the first oxidation process is not limited to an aqueous sulfuric acid solution. For example, an aqueous nitric acid solution can also be used, Wang Shui et al. or, An electrolytic solution obtained by dissolving a solute in an organic molten coal is used.  also, The annealing process is composed of the annealing process. This annealing process is performed by annealing each oxide film in an atmosphere of a nitride gas. During the annealing process, For example, using a lamp annealing device (even a normal furnace is fine),  This paper size applies to Chinese National Standard (CNS) Α4 specification (210X297 mm) -74- 543209 A7 B7 V. Invention Description (72) (Please read the notes on the back before filling out this page} In an N 2 ◦ gas environment, Perform a predetermined annealing time at a predetermined annealing temperature (e.g., 450 ° C) (e.g., 1 hour). here, The annealing temperature can be set below 70 ° C. It is best to set it below 60 ° C. Because the annealing temperature can be set below 700 ° C,  Therefore, when the lower electrode 12 is formed on an insulating substrate 11 such as a glass substrate (a conventional electron source 1 0 〃 as shown in FIG. 40), The oxidation process does not affect the glass substrate.  The insulating film forming process of the manufacturing method of Embodiment 10 has:  A second oxidation process; This second oxidation process is after the annealing treatment,  By rapid thermal oxidation, Under the heat treatment time that can prevent damage to each microcrystalline silicon 63, Oxidizing each oxide film; And nitriding process; This nitriding process is after the second oxidation process, By rapid thermal nitridation, Under the heat treatment time that can prevent damage to each microcrystalline silicon 63, Each oxide film is subjected to a nitriding treatment.  Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs During the second oxidation process, Is using a lamp annealing device, For example, in an oxygen environment, Use the first heat treatment temperature (for example, 900 ° C) for only the first heat treatment time (for example, 5 minutes).  here, The heat treatment time specified in Section 1 is compared with the heat treatment time (1 hour) specified in the conventional rapid thermal oxidation process. Can be greatly shortened. It can be known from the measurement results of the electron emission characteristics of the electron source 10 after manufacture, The first prescribed heat treatment time is preferably set to within 5 minutes. but, The temperature increase rate during the temperature increase period when the substrate temperature is increased to the first predetermined heat treatment temperature is preferably set to 20 ° C / sec or more.  More preferably, it is above 150 ° C / sec.  This paper size applies to China National Standard (CNS) A4 (210X297 mm) -75- 543209 A7 B7 V. Description of the Invention (73) (Please read the notes on the back before filling out this page) Nitriding process is composed of nitriding process, The nitriding process is performed by rapid thermal nitridation. During the heat treatment time that can prevent damage to each microcrystalline silicon 63 (i.e., Heat treatment time specified in Section 2), Each oxide film is nitrided. During this nitriding process, Is using a lamp annealing device, In an environment such as N 2〇 gas, At the heat treatment temperature specified in 2 (for example, 9 0 0 ° C), Only for the heat treatment time specified in Section 2 (for example, 5 minutes) for nitriding. It can be known from the measurement results of the electron emission characteristics of the electron source 10 after manufacture, The second prescribed heat treatment time is preferably set to within 5 minutes. but, It is preferable to set the temperature increase rate during the temperature increase period to increase the substrate temperature to the second predetermined heat treatment temperature at 20 ° C / sec or more. More preferably, it is above 150 ° C / sec. As far as Embodiment 1 is concerned, Since N 2 0 gas is used in the nitriding process, Therefore, the oxidation can be performed simultaneously with the nitriding of each oxide film. the result, Each insulating film 5 2 6 4 will form an oxygen nitride film (oxynitride silicon film). and, The gas used in the nitriding process is not limited to N 2 gas. Can also use No gas, N Η 3 gas, Nitrogen-containing gas, such as N2 gas.  Printed by the Ministry of Economic Affairs ’Smart Money / I ^ 7M Industrial and Consumer Cooperatives If the manufacturing method of Embodiment 10 is used, Basically, the same operations and effects as those of the sixth embodiment can be obtained. that is, During the formation of the insulating film, Under the treatment that can prevent damage to each microcrystalline silicon 63,  An oxide film is formed on the surface of each of the microcrystalline silicon 6 3 to produce a film tunneling phenomenon. An oxide film is formed on the surface of the crystal grain 51. then, Under the treatment that can prevent damage to each microcrystalline silicon 63, Nitride each oxide film, To improve film quality. therefore, As in the past, each insulating film is formed by a rapid thermal oxidation method for a long heat treatment time (for example, 1 hour). 5 2 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 543209 A7 B7. Invention Description (74) (Please read the notes on the back before filling out this page) It can improve the aging stability of electron emission characteristics. Even, Can shorten each insulating film 5 2 The formation of 6 4 is accompanied by a heat treatment time at a high temperature. therefore, As shown in the conventional electron source 10 in FIG. 40, When the lower electrode 12 is formed on the insulating substrate 11, As the glass substrate, an alkali-free glass substrate or a low-alkali glass substrate, which is less expensive than quartz glass, can be used. This enables cost reduction. and, Compared with the manufacturing method of Embodiment 7, Can reduce each insulating film 5 2 Defects in 6 4 Improve electron emission characteristics. also, Because each microcrystalline silicon 6 3 is formed by a wet anodic oxidation process, So after anodizing,  Without exposure to the atmosphere, During the first oxidation process, An oxide film is formed on the surface of each microcrystalline silicon 63 and each crystal grain 51. therefore, It is possible to prevent the formation of a natural oxide film on the surface of each microcrystalline silicon 63 and each crystal grain 51. With this, During the first oxidation process, A good oxide film can be formed on the surface of each microcrystalline silicon 63 and each crystal grain 51.  Figures 34 and 35 show the electron emission characteristics of the electron source 10 manufactured by the manufacturing method of Embodiment 10, respectively. And the results of aging changes in electron emission characteristics.  Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The measurement of the electron emission characteristics of the electron source 10 was performed as shown below. that is, An electron source 10 is introduced into a vacuum processing chamber (not shown). then, As shown in Figure 3 8 The collector electrode 21 is arranged to face the surface electrode 7. and, The direct-current voltage V p s is applied so that the surface electrode 7 can form an electric potential to the conductive layer 1 2, The DC voltage V c is applied in such a manner that the collector electrode 21 can supply a high potential to the surface electrode 7.  This paper size applies to Chinese National Standard (CNS) A4 (210X 297 mm) 543209 A7 B7 V. DESCRIPTION OF THE INVENTION (75) FIG. 34 shows that the DC voltage v c is a constant 100 V, Measurement results of the electron emission characteristics when the vacuum degree in the vacuum processing chamber is 5x 1 0-5 Pa. In Table 3 4 The horizontal axis represents the DC voltage V p s,  The vertical axis represents the current density. and, "P" is the current density representing the diode current I p s, "Q" indicates the current density of the radiated current I e.  Fig. 35 shows that the DC voltage vc is constant 100 volts. The DC voltage V p s is a certain 15 V, Measurement results of the aging change of the electron emission characteristics when the vacuum degree in the vacuum processing chamber is 5x 1 0-5 Pa. In Figure 35, The horizontal axis indicates the aging after the start of the drive, The vertical axis on the left is the current density, The vertical axis on the right indicates the electron emission efficiency. And, "P" is the current density representing the diode current I p s, "Q" is the current density representing the radiated current I e, "R" indicates the electron emission efficiency.  From Figures 3 4 and 35, And Comparative Example 1 described in Embodiment 6, It can be seen from the second 8 to 31 of the measurement result of 2 that Implementation of electron source 10 of state 10 and comparative example 1, Compared with the electron source of 2 It can improve the aging stability of the electron emission characteristics.  (Embodiment 11) Hereinafter, Embodiment 11 of the present invention will be described. The manufacturing method of the electron source according to the eleventh embodiment is different from the manufacturing method of the electron source according to the sixth embodiment in the insulating film forming process. therefore, The following mainly describes the process of forming the insulating film. This embodiment 11 is the same as the embodiment 6 in the same paper size as the Chinese National Standard (CNS) A4 specification (210 × 297 mm) (please read the precautions on the back before filling out this page) and fill in the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by Employee Consumer Cooperatives-78- 543209 A7 B7 V. DESCRIPTION OF THE INVENTION (76) An oxidation treatment and a nitridation treatment are performed during the formation of the insulating film.  (Please read the precautions on the back before filling out this page) Embodiment 1 The oxidation treatment of 1 is composed of the first oxidation process.  That is, the first oxidation process is by an electrochemical method, An oxide film is formed on the surface of each microcrystalline sand 63. For the first oxidation process, After the end of the anodizing process, Wash with ethanol. then,  The electrochemical method ’is to use a treatment tank containing a sulfuric acid aqueous solution having a predetermined concentration (for example,‘ 1 m ο 1/1/2 1 M), A constant voltage is applied between the lower electrode 12 and the cathode (made of a platinum electrode). Thereby, an oxide film having a film thickness capable of causing a tunneling phenomenon of electrons is formed on the surfaces of each of the crystal grains 51 and each of the microcrystalline silicon 63. and, The electrolytic solution used in the first oxidation process is not limited to an aqueous sulfuric acid solution. For example, an aqueous nitric acid solution can also be used, Wang Shui et al. or, An electrolytic solution obtained by dissolving a solute in an organic molten coal is used.  Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs During the annealing process, For example, using a lamp annealing device (even a normal furnace is fine), In the environment of N 2〇 gas, Perform a predetermined annealing time at a predetermined annealing temperature (for example, 450 ° C) (for example, 1 hour ). here, The annealing temperature can be set to less than 7 0 t, It is best to set it below 60 0 t. If we use electrochemical methods, The oxide film can be formed at room temperature. therefore, The annealing temperature can be set below 70 ° C, Compared with the sixth embodiment, Eliminates high temperatures from oxidation processes (e.g., 9 0 0 ° C). and, Because the annealing temperature can be set below 700 ° C, Therefore, when the lower electrode 12 is formed on an insulating substrate 11 such as a glass substrate (the conventional electron source 10 〃 shown in FIG. 40), The oxidation process does not affect the glass substrate.  -79- This paper size is applicable to Chinese National Standard (cns) A4 (210X297 Public Director 543209 A7 B7 V. Description of the Invention (77) (Please read the precautions on the back before filling this page) During this nitriding process, Is using a lamp annealing device, In an environment such as N 2 0 gas, At the heat treatment temperature specified in 2 (for example, 9 〇 〇 c), Only for the heat treatment time specified in Section 2 (for example, 5 minutes) for nitriding. From the measurement results of the electron emission characteristics of the electron source 10 after manufacture, it can be understood that the heat treatment time specified in the '2' is preferably set to within 5 minutes. However, it is preferable to set the temperature increase rate during the temperature increase period of increasing the substrate temperature to the second predetermined heat treatment temperature to be 20 ° C / sec or more.  More preferably, it is above 150 ° C / sec. As far as Embodiment 11 is concerned,  Since N 2 gas is used in the nitriding process, Therefore, the oxidation can be performed simultaneously with the nitriding of each oxide film. the result, Each insulating film 5 2 6 4 will form an oxygen nitride film (oxynitride silicon film). and, The gas used in the nitriding process is not limited to N2 gas. You can also use n ◦ gas, NH3 gas, Nitrogen-containing gas such as N2 gas.  Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs If the manufacturing method of the electron source 10 of the embodiment 11 is used, Basically, the same operations and effects as those of the sixth embodiment can be obtained. that is, In terms of this manufacturing method, During the formation of the insulating film, Under the treatment that can prevent damage to each microcrystalline silicon 63, An oxide film is formed on the surface of each microcrystalline silicon 6 3 with a film thickness that can cause electron tunneling. An oxide film is formed on the surface of the crystal grain 51. then, Under the treatment capable of preventing damage to each microcrystalline silicon 63, Nitride each oxide film, To improve film quality. therefore, As in the past, each insulating film 5 2 is formed by a rapid thermal oxidation method over a long heat treatment time (for example, 1 hour). At 6 o'clock, It can improve the aging stability of the electron emission characteristics. even, Can shorten each insulating film 5 2, The heat treatment time at high temperature accompanied by the formation of 64. therefore, For example, this paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -80- 543209 A7 B7 V. Description of the Invention (78) (Please read the precautions on the back before filling out this page} The conventional electron source 1 0 〃 shown in Figure 40, When the lower electrode 12 is formed on the insulating substrate 1 1, As the glass substrate, an alkali-free glass substrate or a low-alkali glass substrate, which is less expensive than quartz glass, can be used. It enables cost reduction. and, Compared with Embodiment 7, Can reduce each insulating film 5 2 ，  6 4 Defects, Improve electron emission characteristics. also, Because each microcrystalline silicon 6 3 is formed by a wet anodizing treatment, So after anodizing, Without exposure to the atmosphere, During the first oxidation, An oxide film is formed on the surface of each microcrystalline silicon 63 and each crystal grain 51. therefore, It is possible to prevent the formation of a natural oxide film on the surfaces of each of the microcrystalline silicon 63 and each of the crystal grains 51. With this, During the first oxidation process,  A good oxide film can be formed on the surface of each microcrystalline silicon 63 and each crystal grain 51.  (Embodiment 1 2) Printed by the Intellectual Property of the Ministry of Economic Affairs and the Consumer Consumption Cooperative. Embodiment 12 of the present invention will be described. The manufacturing method of the electron source according to the twelfth embodiment differs from the manufacturing method of the electron source according to the sixth embodiment in the insulating film formation process. therefore, The following mainly describes the process of forming the insulating film.  During the formation of the insulating film in Embodiment 11, The basic process consisting of oxidation treatment and nitridation treatment is repeated multiple times. To form each insulating film 5 2 6 4. The oxidation process is by rapid thermal oxidation, The heat treatment time is to prevent damage to each microcrystalline silicon (semiconductor microcrystal) 63, The nitriding process is performed by rapid thermal nitridation after oxidation treatment. In order to prevent the microcrystalline silicon (semiconductor microcrystal), the paper size applies the Chinese National Standard (CNS) 8-4 specifications (21 × 297 mm) -81-543209 A7 B7 V. Description of the invention (79) (Please read the precautions on the reverse side before filling out this page) 6 3 Perform the heat treatment at the time when the damage occurred. In terms of oxidation treatment, Is on the surface side of the oxidized microcrystalline silicon 6 3, As far as nitriding is concerned, It is to improve film quality.  During this oxidation process, Is using a lamp annealing device, In an environment such as oxygen, At the first heat treatment temperature (for example, 9 0 0 t) ’with only the heat treatment time specified in Table 1 (for example, 5 minutes) for oxidation. that is, The heat treatment time specified in Section 1 is compared with the predetermined heat treatment time (1 hour) of the conventional rapid thermal oxidation oxidation process. Can be greatly reduced. but, The temperature increase rate during the temperature increase period when the substrate temperature is raised to the first predetermined heat treatment temperature is preferably set to 20 ° C / sec or more. More preferably, it is above 150 ° C / s e c.  Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs The nitriding process is performed by rapid thermal oxidation, During the heat treatment time that can prevent damage to each microcrystalline silicon 6 3 (ie, Heat treatment time specified in Section 2), Each oxide film is nitrided. During this nitriding process, Is using a lamp annealing device, In an environment such as N 2 0 gas, At the heat treatment temperature specified in Section 2 (for example, 9 0 0 ° C), Only for the heat treatment time specified in Section 2 (for example, 5 minutes). but, The temperature increase rate during the temperature increase period to increase the substrate temperature to the second predetermined heat treatment temperature is preferably set to 20 ° C / sec or more. More preferably, it is above 150 ° C / sec. As far as Embodiment 12 is concerned, Since N 2 gas is used in the nitriding process, Therefore, the oxidation can be performed simultaneously with the nitridation of each oxide film.  the result, Each insulating film 5 2 An oxide nitride film (oxynitride silicon film) is formed. and, The gas used in the nitriding process is not limited to N 2O gas. You can also use NO gas, NH 3 gas, N2 gas and other nitrogen-containing paper sizes are applicable to China National Standard (CNS) A4 specifications (210X297 mm) -82- 543209 A7 ___ B7 V. Description of the invention (80) gas.  (Please read the notes on the back before filling out this page) If you use this manufacturing method, Basically, the same functions and effects as those of the sixth embodiment can be obtained. that is, As in the past, each insulating film 5 2 is formed by a rapid thermal oxidation method over a long heat treatment time (for example, 1 hour). 6 4 o'clock compared, It can improve the aging stability of electron emission characteristics. even, Can shorten each insulating film 5 2 ， The formation of 6 4 is accompanied by a heat treatment time at a high temperature. therefore, As shown in the conventional electron source 10 in FIG. 40, When the lower electrode 12 is formed on an insulating substrate 11 such as a glass substrate, For the glass substrate, a cheaper alkali-free glass substrate or a low-alkali glass substrate can be used. This enables cost reduction. and, Compared with the manufacturing method of the seventh embodiment, Can reduce each insulating film 5 2 6 4 Defects, This makes it possible to improve electron emission characteristics.  (Embodiment 1 3) Hereinafter, Embodiments 13 of the present invention will be described.  Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs In Embodiments 13 and 13, Conductive substrates are used: A conductive layer 1 2 is provided on one surface of an insulating substrate 1 1 made of a glass substrate (for example, Metal film such as chromium film or I τ ◦ film, etc.). When such a substrate is used (the conductive layer 1 2 is formed on one surface side of the insulating substrate 1 1), Compared with the case of using a semiconductor substrate as a conductive substrate, Larger area and lower cost of electron source.  The basic configuration of the electron source 10 of Embodiment 13 is substantially the same as the conventional electron source 10 〃 shown in FIG. 40. that is, Non-doped polycrystalline silicon is formed on the conductive layer 1 2 on the insulating substrate 1 1 This paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm) ~ "  543209 A7 B7 V. DESCRIPTION OF THE INVENTION (81) Layer 3 (semiconductor layer). A drift layer 6 composed of a porous polycrystalline silicon layer is formed on the polycrystalline silicon layer 3 (read the precautions on the back before filling this page). There is a surface electrode 7 on the drift layer 6. The surface electrode 7 is made of a material having a smaller work function (_ such as 'gold'). The thickness of the surface electrode 7 is set to 3 to 1 Srim. ; ^ The structure of the Guan drift layer 6 will be described later. In Figure 3 6 F, A part of the polycrystalline sand layer 3 will be interposed between the conductive layer 12 and the drift layer 6. but, It is not necessary to interpose the polycrystalline silicon layer 3, A drift layer 6 is formed on the conductive layer 12.  The procedure for discharging electrons from the electron source 10 is the same as that of the conventional electron source 10 hours shown in Fig. 40. that is, The collector electrode 2 1 is arranged so as to face the surface electrode 7 (refer to FIG. 40), And the vacuum state is formed between the surface electrode 7 and the collector electrode 21 printed by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. also, In a manner that the surface electrode 7 can form a high potential (positive electrode) to the conductive layer 12, a direct voltage V p s is applied between the surface electrode 7 and the conductive layer 12. and, In a manner that the collector electrode 21 can form a high potential to the surface electrode 7, A DC voltage V c is applied between the collector electrode 21 and the surface electrode 7. As long as each DC voltage v p s is appropriately set, v c, The electrons injected from the conductive layer 12 will drift in the drift layer 6, It is released via the surface electrode 7.  the following, While referring to Figures 3 6A to 3 6 F, A method for manufacturing the electron source 10 according to the embodiment 13 will be described.  First of all, On one surface side of the insulating substrate 1 1, The conductive layer 12 is provided by a sputtering method or the like, To form a conductive substrate, The structure shown in Fig. 36A is obtained. then, On one surface side of the conductive substrate (this paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) " "  "  -84- 543209 A7 B7 V. Invention Description (82) That is, On the conductive layer 12), Forming (forming) a non-doped polycrystalline silicon layer 3 (semiconductor layer (please read the precautions on the back before filling this page)) with a predetermined film thickness (eg 1 · 5 // m), The structure shown in Fig. 3 6B is obtained. In terms of the method for forming the polycrystalline silicon layer 3, For example, you can use: C V D method (L P C V D method, Plasma C V D method, Catalyst C V D method, etc.), Sputtering And C S G (Continuous Grain Silicon) method. Since the film formation temperature is set below 600 ° C, Therefore, the insulating substrate 11 can be, for example, an alkali-free glass substrate. Low alkali glass substrate, Cheaper glass substrates such as soda-lime glass substrates, This enables cost reduction.  Printed by the Intellectual Property of the Ministry of Economic Affairs and Consumer Cooperatives Secondly, After the undoped polycrystalline silicon layer 3 is formed, A cover material (not shown) for forming a polycrystalline silicon layer 4 described later only in a predetermined area is provided. then, Use an anodizing tank containing an electrolyte (the electrolyte is: It is formed by mixing a 5 5 wt% hydrogen fluoride aqueous solution with ethanol in a 1: 1 manner), With a platinum electrode (not shown) as the negative electrode, And using the conductive layer 12 as a positive electrode, While illuminating the polycrystalline silicon layer 3, Anodization was performed under predetermined conditions. Thereby, a porous polycrystalline sand layer 4 is formed. then, Remove the mask material, The structure shown in Fig. 36C is obtained. In the anodizing treatment of Embodiment 13 'is the period during which the anodizing treatment is performed, The light radiated on the surface of the polycrystalline sand layer 3 and the current density are constant. but, This processing condition can also be appropriately changed (for example, Make current density change).  After the anodizing process is completed, In a 1 (m 〇 1) sulfuric acid (Η 2 S〇4) aqueous solution, Electrochemical oxidation treatment of porous polycrystalline silicon layer 4, To form the drift layer 6-, Get 3rd 6d 85- 543209 A7 B7 V. Description of the Invention (83) The structure shown in the figure. here, Aqueous solution and concentration when performing electrochemical oxidation, It is not particularly limited. E.g, Aqueous nitric acid solution can be used (please read the precautions on the back before filling this page) 〇 After forming the drift layer 6 > after that, The uppermost surface of one surface side of the conductive substrate (here, the surface of the drift layer 6 /) is irradiated with hydrogen radicals, Come to exist in the drift layer 6 > Defect passivation (not dynamic), The structure shown in Fig. 3E is obtained. Reference numeral 6 in Fig. 3E shows a drift layer after hydrogen-based irradiation. During the hydrogen-based irradiation of the surface of the drift layer 6 /, The uppermost surface of one surface side of the conductive substrate is irradiated with hydrogen groups in the hydrogen plasma. therefore, It is possible to reduce the process temperature of the hydrogen-based irradiation process (process temperature below 600 ° C). and, It can easily cope with the large area of the electron source 10. and, It can irradiate hydrogen base with high frequency or microwave to make plasma, This makes it applicable to general semiconductor manufacturing equipment capable of generating hydrogen plasma, To reduce costs.  Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. On drift layer 6, For example, a conductive thin film (for example, Gold thin film) surface electrode 7, An electron source 10 having a structure shown in Fig. 36F was obtained. here , Method for forming the surface electrode 7, Is not limited to evaporation For example, a sputtering method may be used.  The drift layer 6 of the electron source 10 produced by such a manufacturing method is the same as the electric field drift layer 6 of the electron source 10 shown in FIG. 1, By at least Grains of columnar polycrystalline silicon 5 1, And thin silicon oxide film 5 2, And nanocrystalline silicon 6 3, And a silicon oxide film 64. but,  As for the electron source 10 of Embodiment 13, Will be oxidized porous multi-junction This paper size applies Chinese National Standard (CNS) A4 specifications (210X297 mm) -86- 543209 A7 B7 V. Description of the Invention (84) (Please read the precautions on the back before filling this page) The surface of the drift layer 6 formed after the crystal sand layer 4 is irradiated with hydrogen radicals Then, a drift layer 6 is formed. therefore, The defects existing in the drift layer 6-(for example, the 'silicon oxide film 5 2', 6 4 or microcrystalline silicon 6 3 Defects on the surface) blunt (not dynamic) or reduced. With this, An electron source 10 capable of improving electron emission characteristics and reliability can be obtained. The electron source 10 manufactured in this way and the conventional electron source 1 shown in FIG. 38 are shown in FIG. same, The degree of vacuum dependence of electron emission characteristics is small, And no jumping phenomenon occurs when the electrons are released, Can release electrons stably.  Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and the Industrial Cooperative Cooperative. Although the drift layer 6 is formed after the porous polycrystalline silicon layer 4 is oxidized > The hydrogen plasma irradiation treatment is performed thereafter ', but the hydrogen plasma irradiation process may be performed before the anodizing treatment. Alternatively, the hydrogen plasma irradiation process may be performed after the anodizing treatment. and, In the annealing process in hydrogen, Same as the above hydrogen-based irradiation, Can exist in the drift layer 6 > Defects in (for example, Silicon oxide film 5 2, 6 4 or microcrystalline silicon 6 3 Surface defects) passivation (not dynamic) or reduced. here, The annealing temperature can be set below 70 ° C. It is best to set it below 60 ° C. and, Hydrogen can be 100%, Or a mixed gas mixed with other gases.  In the above-mentioned manufacturing method of the electron source 10, Although the drift layer 6 is formed after the porous polycrystalline silicon layer 4 is oxidized > After that, a hydrogen plasma irradiation treatment is performed, However, the hydrogen plasma irradiation process can also be performed before the anodizing treatment. Alternatively, the hydrogen plasma irradiation process may be performed after the anodizing treatment.  also, In the above-mentioned manufacturing method of the electron source 10, Although it is in the process of hydrogen plasma irradiation, A table that radiates the hydrogen groups in the hydrogen plasma to the conductive substrate < 297 mm) 543209 A7 B7 V. Description of the invention (85) (Please read the precautions on the back before filling this page) The uppermost surface on the side, but as shown in Figure 37, you can also use hydrogen and The hydrogen group generated by the contact decomposition reaction of the tungsten contact medium 42 is irradiated to the uppermost surface on the one surface side of the conductive substrate (in the example shown in FIG. 37, the surface of the drift layer 6 >). In this case, the contact medium 42 is heated to an appropriate temperature by a current from a current source (not shown). The conductive substrate is set on the substrate holder 41, and the substrate holder 41 is appropriately heated to 100 to 700 ° C by a heater (not shown). However, when a conductive substrate is used: when a conductive layer 12 is formed on one surface of an insulating substrate 1 1 made of a glass substrate, the temperature of the insulating substrate 1 1 must not reach the insulating substrate 1. The temperature of the substrate holder 41 is set as a heat-resistant temperature of 1. Printed by the Intellectual Property of the Ministry of Economic Affairs and the Consumer Consumption Cooperative. Therefore, during the hydrogen-based irradiation, when the hydrogen group in the hydrogen plasma is irradiated to the uppermost surface of one surface side of the conductive substrate, the plasma may damage the drift layer 6. However, during the hydrogen-based irradiation, if the hydrogen group is decomposed and generated by using the hydrogen-based contact medium 42, this situation can be prevented. Therefore, it is possible to obtain an electron source 10 capable of improving the electron emission characteristics and reliability as compared with the case where the hydrogen radical in the hydrogen plasma is irradiated. In addition, in the hydrogen-based irradiation process, one surface side of the conductive substrate may be irradiated with hydrogen groups generated by thermal decomposition or photodecomposition of hydrogen gas. In this case, it is possible to obtain an electron source 10 which can improve the electron emission characteristics and reliability as compared with the case where the hydrogen radical in the hydrogen plasma is irradiated. In Embodiment 13, the conductive substrate is one in which a conductive layer 12 is formed on one surface of an insulating substrate 11 (consisting of a glass substrate), but a metal substrate such as chromium may be used as the conductive substrate. . Alternatively, this paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) -88- 543209 Α7 ________________ B7 V. Description of the invention (86) A semiconductor substrate (for example, the resistivity is closer to that of a conductor) N-type sand substrate, or η-type area where a conductive layer is formed on one side (please read the precautions on the back before filling this page), etc.). In addition to the glass substrate, the insulating substrate 11 can be a ceramic substrate or the like. In Embodiment 13, the material of the surface electrode 7 is gold, but it is not limited to this. For example, aluminum, chromium, tungsten, nickel, platinum, etc. may be used. In addition, the surface electrode 7 may be composed of at least two thin film layers in the thickness direction. When the surface electrode 7 is composed of two thin film layers, for example, as the material of the upper film layer, for example, gold may be used. As the material of the lower film layer (the film layer on the side of the drift layer 6), chromium, nickel, platinum, titanium, iridium, etc. can be used. Printed in Embodiment 13 by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Although the drift layer 6 is formed by an oxidized porous polycrystalline sand layer, a porous single crystalline silicon layer or an oxidized layer may also be used. The nitrided porous polycrystalline silicon layer constitutes the drift layer 6. Alternatively, it may be composed of another porous semiconductor layer after oxidation, nitridation, or oxidation-nitridation. When the drift layer 6 is a nitrided porous polycrystalline silicon layer, the process of oxidizing the porous polycrystalline silicon layer 4 may be replaced with a process of nitriding the porous polycrystalline silicon layer 4. In this case, each of the silicon oxide films 5 2 and 64 forms a silicon nitride film. When the drift layer 6 is an oxidized / nitrided porous polycrystalline silicon layer, the process of oxidizing / nitriding the porous polycrystalline silicon layer 4 may be used instead of the process of oxidizing the porous polycrystalline silicon layer 4. In this case, each of the oxide sand films 5 2 and 6 4 will form an oxide / nitride sand film. Although the specific embodiments of the present invention have been described above, many other modifications and corrections may be implemented in addition to this. In other words, the paper size of this issue applies to the Chinese National Standard (CNS) A4 specification (210 × 297 mm) -89- 543209 A7 B7 V. Description of the invention (87) The description is not limited to the above embodiments as long as it does not depart from applying for a patent The main scope of the range may be implemented in other embodiments. (Please read the precautions on the back before filling in this page) [Industrial possibilities] As mentioned above, the electric field emission type electron source of the present invention and its manufacturing method are particularly helpful for improving the efficiency and reliability of electron emission It is suitable for electron sources such as flat light sources, flat display elements, and solid-state vacuum devices. [Simplified description of the drawing] FIG. 1 is a schematic cross-sectional view showing a main part of the electron source according to the first embodiment of the present invention. Fig. 2 shows the operation of the electron source of Fig. 1. Figs. 3A to 3D are schematic cross-sectional views showing the electron source of Fig. 1 and the intermediates in the process of producing the electron source in Fig. 1 and showing a method of manufacturing the electron source. Fig. 4 is a graph showing the light emission spectrum of the photoluminescence measurement of the electron source of Fig. 1 and the comparative example, which is a characteristic of the wavelength of photoluminescence intensity. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Industrial and Consumer Cooperatives. Figure 5 is a diagram showing the depth distribution of the constituent elements of the X-ray photoelectron spectroscopy method of the electron source of Figure 1 and the comparative example. . 6A and 6B are diagrams showing the electron emission principles of the electron source of Fig. 1, respectively. Figures 7A and B show the electron emission principles of the electron source of the comparative example, respectively. -90- The standard of this paper is applicable to the Chinese National Standard (CNS) A4 specification (210X29? Mm) 543209 A 7 B7 V. Description of the invention (88) Figures 8A and B are the electron source and the comparative example respectively showing Figure 1. Process of the electron source. (Please read the precautions on the back before filling out this page.) Figure 9 shows the time-dependent changes in the electron emission efficiency of the electron source of Figure 1 and the electron source of the comparative example. Fig. 10 shows the electron emission characteristics of the electron source of Fig. 1 and the electron source of the comparative example. Fig. 11 is a diagram showing the operation of the electron source according to the second embodiment of the present invention. Figs. 12A to 12D are schematic cross-sectional views showing the electron source of Fig. 11 and the intermediates in the manufacturing process. Production method. Fig. 13 is a schematic cross-sectional view showing a main part of an electron source according to a third embodiment of the present invention. Fig. 14 shows the operation of the electron source shown in Fig. 13; Figs. 15A to D are schematic cross-sectional views showing the electron source of Fig. 13 and the intermediates in the manufacturing process thereof, and a method for manufacturing the electron source. Fig. 16 is a view showing a method for forming an insulating film of an electron source according to a third embodiment of the present invention, and shows the aging change of the heat treatment temperature. Printed by the Intellectual Property of the Ministry of Economic Affairs and the Consumer Cooperatives. Figure 17 is a schematic diagram showing the structure of a heat treatment device used to form the insulating film shown in Figure 13 Fig. 18 is a graph showing the measurement results of the temperature rising desorption gas mass spectrometry, and it shows the change characteristics of the heating temperature to the ion current. Figs. 19A to G are schematic cross-sectional views showing an electron source according to a fourth embodiment of the present invention and intermediates in the process of manufacturing the electron source, and are methods for manufacturing the electron source. This paper size applies Chinese National Standard (CNS) A4 specification (21 × 297 mm) 543209 A7 B7 V. Description of the invention (89) Figure 20 shows the uppermost terminal of the porous polycrystalline silicon layer after annealing treatment form. (Please read the precautions on the back before filling in this page.) Figures 2 to A through F are schematic cross-sectional views showing the electron source and intermediates in the manufacturing process according to the fifth embodiment of the present invention. method. Figures 2 A to C show the DC current density of the electron source when the annealing process is performed at 500 ° C and when the annealing process is performed at 5 50 t: without annealing. Variation characteristics of voltage V ps. Fig. 23 is a schematic cross-sectional view showing a main part of an electron source according to a sixth embodiment of the present invention. Fig. 24 shows the operation of the electron source shown in Fig. 23; Figs. 2A to 5D are schematic cross-sectional views showing an electron source according to a sixth embodiment of the present invention and intermediates in the process of manufacturing the electron source, showing a method for manufacturing the electron source. Fig. 26 is a graph showing the change characteristics of the DC voltage V p s with respect to the current density of the electron source of Fig. 23; Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 27 shows the time-varying characteristics of the current density of the electron source in Figure 23. Fig. 28 is a graph showing the change characteristics of the DC voltage V P s with respect to the current density of the electron source of the comparative example. Fig. 29 is a graph showing the time-varying characteristics of the current density of the electron source of the comparative example (the same comparative example as Fig. 28). Fig. 30 shows the current density of the electron source of another comparative example. This paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -92- 543209 A7 __ B7 V. Description of the invention (9) Variation characteristics of DC voltage V ps. (Please read the precautions on the back before filling out this page.) Figure 31 shows the time-varying characteristics of the current density of the electron source in this comparative example (the same comparative example as in Figure 30). Fig. 32 is a graph showing the change characteristics of the DC voltage V p s with respect to the current density of the electron source according to the seventh embodiment of the present invention. Fig. 33 is a graph showing the time-varying characteristics of the current density of the electron source according to the seventh embodiment of the present invention. Fig. 34 is a graph showing the change characteristics of the DC voltage V p s with respect to the current density of the electron source according to Embodiment 10 of the present invention. Fig. 35 is a graph showing the time-varying characteristics of the current density with respect to the electron source according to Embodiment 10 of the present invention. Figures 36A to F are schematic cross-sectional views showing an electron source according to Embodiment 13 of the present invention and intermediates in the process of manufacturing the same, showing a method for manufacturing the electron source. Fig. 37 is a diagram showing a processing method of a hydrogen-based irradiation process in the method of manufacturing an electron source according to Embodiment 13 of the present invention. Fig. 38 is a diagram showing the operation of a conventional electron source. Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 39 is a schematic cross-sectional view of the main part of a conventional electron source. Fig. 40 is an operation diagram showing another conventional electron source. Figure 41 shows the aging change of the heat treatment temperature of the rapid heating method. Figure 42 shows the terminal form of the uppermost surface of the porous polycrystalline sand layer after anodizing. Figure 4-3 shows the -93- porous polycrystalline sand layer after the rapid heating method. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 543209 Α7 B7 5. The top surface of the description of the invention (91) Terminal form. (Please read the precautions on the back before filling this page) [Explanation of Symbols] 1: η-type silicon substrate 2: Ohm electrode 3: Polycrystalline silicon layer 4, 4 /: Porous polycrystalline silicon layer 6, 6 —, 6 〃: drift layer 7: surface electrodes 10, 10 /, 10 〃: electron source 11: insulating substrate 1 2: lower electrode (conductive layer) 21: collector electrode 4 1: processing chamber 4 2: Radiation thermometer 4 3: Moisture extraction means 4 4: Control means Intellectual property of the Ministry of Economics ¾ Printed by employee consumer cooperatives 5 1: Grain 5 2, 6 4: Thin insulating film (silicon oxide film) 6 3: Microcrystalline silicon 8 0: Oxygen molecule 8 1: Oxygen atom π 0: Initial electron emission efficiency τ: Time fixed number of paper size Applicable to Chinese National Standard (CNS) A4 specification (210X297 mm) -94- 543209 A7 B7 V. Description of the invention (92)

Ips :二極體電流Ips: diode current

Ie :發射電流（放出電子電流）Ie: emission current (emission of electron current)

Vps、Vc :直流電圧 P:二極體電流Ips的電流密度 Q :發射電流Ie的電流密度 R :電子放出効率 ----1----裝-- (請先閱讀背面之注意事項再填寫本頁)Vps, Vc: DC current 圧 P: Current density of diode current Ips Q: Current density of emission current Ie R: Electron emission efficiency ---- 1 ---- install-(Please read the notes on the back first (Fill in this page)

、1T 經濟部智慧財產苟員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） -95-、 1T Printed by the Intellectual Property of the Ministry of Economic Affairs, Employees' Cooperatives, This paper size applies to China National Standard (CNS) Α4 specification (210X 297 mm) -95-

Claims (1)

543209 A8 B8 C8 D8 _ 六、申請專利範圍 1 1、 一種電場放射型電子源，是屬於一種具備： 導電性基板；及 (請先閲讀背面之注意事項再填寫本頁) 形成於導電性基板上的強電場飄移層；及 形成於強電場飄移層上的表面電極； 並且，強電場飄移層具有： 形成於構成該強電場飄移層的半導體層的一部份之奈 米單位的多數個半導體微結晶；及 形成於各半導體微結晶的表面，具有比半導體微結晶 的結晶粒徑還要小的膜厚之多數的絕緣膜； 而且，在表面電極與導電性基板之間，以表面電極能 夠形成高電位之方式來施加電壓，藉此從導電性基板注入 強電場飄移層的電子會飄移於強電場飄移層內，經由表面 電極而放出之電場放射型電子源； 其特徵爲： 形成於各半導體微結晶的表面之絕緣層具有會產生電 子的穿隧現象的膜厚。 經濟部智慧財產局員工消費合作社印製 2、 如申請專利範圍第1項之電場放射型電子源，其 中形成於各半導體微結晶的表面之絕緣膜中所含的水分實 質爲0。 3、 如申請專利範圍第1項之電場放射型電子源，其 中在構成強電場飄移層的半導體層與導電性基板的界面介 在有由半導體與金屬所構成的化合物層或合金層。 4、 如申請專利範圍第1項之電場放射型電子源，其 中在構成強電場飄移層的半導體層與導電性基板的界面 本紙張尺度適用中國國家標準（CNS ) A4規格（2ΐ〇χ297公釐） -96 - 543209 A8 B8 C8 ____D8 々、申請專利範圍 2 半導體層幾乎會被結晶化。 (請先閱讀背面之注意事項再填寫本頁) 5、 一種電場放射型電子源的製造方法，是屬於一種 具備： 導電性基板；及 形成於導電性基板上的強電場飄移層；及 形成於強電場飄移層上的表面電極； 並且，強電場飄移層具有： 形成於構成該強電場飄移層的半導體層的一部份之奈 米單位的多數個半導體微結晶；及 开夕成於各半導體微結晶的表面，具有會產生電子的穿 隧現象的膜厚之多數的絕緣膜； 而且’在表面電極與導電性基板之間，以表面電極能 夠形成高電位之方式來施加電壓，藉此從導電性基板注入 強電場飄移層的電子會飄移於強電場飄移層內，經由表面. 電極而放出之電場放射型電子源的製造方法； 其特徵爲： 經濟部智慧財產局員工消費合作社印製 藉由電氣化學性方法，急速熱氧化法，急速熱氮化法 及急速熱氧化•氮化法的其中之一，或其組合來進行往半 導體微結晶表面之絕緣膜的形成。 6、 如申請專利範圍第5項之電場放射型電子源的製 造方法，其中在往半導體微結晶表面之絕緣膜的形成後， 在真空中，惰性氣體中，形成氣體中，或氮化氣體中進行 7 0 〇 t以下的溫度之退火處理。 7、 如申請專利範圍第5項之電場放射型電子源的製 -97- 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐） 543209 A8 Β8 C8 D8 六、申請專利範圍 3 (請先閲讀背面之注意事項再填寫本頁) 造方法，其中在往半導體微結晶表面之絕緣膜的形成後， 在含氧化類或氮化類的環境中，以6 0 0 °C以上的溫度來 進行急速加熱法之熱處理。 8、 如申請專利範圍第5項之電場放射型電子源的製 造方法，其中在往半導體微結晶表面之絕緣膜的形成後， 在惰性氣體的環境中，以6 0 0 °C以上的溫度來進行急速 加熱法之退火處理。 9、 如申請專利範圍第5項之電場放射型電子源的製 造方法，其中在半導體微結晶的形成後，在真空中或惰性 氣體中進行退火處理。 1 〇、如申請專利範圍第5項之電場放射型電子源的 製造方法，其中在導電性基板上形成半導體層後，在真空 中或惰性氣體中進行退火處理。 1 1、如申請專利範圍第5項之電場放射型電子源的 製造方法，其中分別進行1次或複數次下列3個處理過程 的其中至少2個處理過程； 經濟部智慧財產局員工消費合作社印製 第1處理過程：在往半導體微結晶表面之絕緣膜的形 成後，在真空中，惰性氣體中，形成氣體中，或氮化氣體 中進行7 0 0 °C以下的溫度之退火處理，及利用可缺陷補 償的氣體類之退火處理的至少其中之一； 第2處理過程：在含氧化類或氮化類的環境中，以 6 0 0 °C以上的溫度來進行急速加熱法之熱處理； 第3處理過程：在惰性氣體的環境中，以6 0 0 t以 上的溫度來進行急速加熱法之退火處理。 本紙張尺度適用中國國家樣準（CNS ) A4規格（210X297公釐） -98 - 543209 A8 B8 C8 D8 六、申請專利範圍 4 1 2、如申請專利範圍第5項之電場放射型電子源的 製造方法，其中在形成半導體層後，及在形成半導體微結 晶後，以及在半導體微結晶表面形成絕緣膜後的至少其中 之一時期，進行氫氣中的退火處理，氫基照射處理或氫基 照射退火處理。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -99 -543209 A8 B8 C8 D8 _ 6. Scope of patent application 1 1. An electric field emission type electron source belongs to a type with: a conductive substrate; and (please read the precautions on the back before filling this page) formed on a conductive substrate A strong electric field drifting layer; and a surface electrode formed on the strong electric field drifting layer; and the strong electric field drifting layer has: a plurality of semiconductor micrometers in nanometer units formed in a part of a semiconductor layer constituting the strong electric field drifting layer; A crystal; and an insulating film formed on the surface of each semiconductor microcrystal and having a film thickness smaller than the crystal grain size of the semiconductor microcrystal, and having a film thickness smaller than that of the semiconductor microcrystal; and a surface electrode can be formed between the surface electrode and the conductive substrate. A high potential method is used to apply a voltage, whereby electrons injected into the strong electric field drift layer from the conductive substrate will drift in the strong electric field drift layer, and the electric field emission type electron source emitted through the surface electrode; It is characterized in that: formed on each semiconductor The insulating layer on the surface of the microcrystal has a film thickness that causes electron tunneling. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 2. If the electric field emission type electron source of the first patent application scope, the moisture contained in the insulating film formed on the surface of each semiconductor microcrystal is essentially zero. 3. For example, the electric field emission type electron source in the scope of application for patent No. 1 includes a compound layer or an alloy layer composed of a semiconductor and a metal at the interface between the semiconductor layer constituting the strong electric field drift layer and the conductive substrate. 4. For the electric field emission type electron source in item 1 of the scope of the patent application, in which the interface between the semiconductor layer and the conductive substrate constituting the strong electric field drift layer is in accordance with the Chinese National Standard (CNS) A4 specification (2 × 0 × 297 mm) ) -96-543209 A8 B8 C8 ____D8 々, patent application scope 2 The semiconductor layer will almost be crystallized. (Please read the precautions on the back before filling this page) 5. A method for manufacturing an electric field emission type electron source belongs to a method that includes: a conductive substrate; and a strong electric field drift layer formed on the conductive substrate; and A surface electrode on the strong electric field drift layer; and the strong electric field drift layer includes: a plurality of semiconductor microcrystals in nanometer units formed in a part of a semiconductor layer constituting the strong electric field drift layer; and formed on each semiconductor The surface of the microcrystal has an insulating film with a majority of the thickness of the film that can cause tunneling of electrons. Furthermore, a voltage is applied between the surface electrode and the conductive substrate in such a way that the surface electrode can form a high potential. The electrons injected into the strong electric field drifting layer of the conductive substrate will drift in the strong electric field drifting layer, and the manufacturing method of the electric field radiation type electron source released through the surface electrode. It is characterized by: printed by the Intellectual Property Bureau staff of the Ministry of Economic Affairs Electrochemical method, rapid thermal oxidation method, rapid thermal nitridation method and rapid thermal oxidation-nitridation method , Or a combination thereof to form an insulating film for a semiconductor of the surface of the microcrystalline. 6. The manufacturing method of the electric field emission type electron source according to item 5 of the patent application scope, wherein after the formation of the insulating film on the surface of the semiconductor microcrystal, in a vacuum, an inert gas, a forming gas, or a nitriding gas The annealing treatment is performed at a temperature of 700 t or less. 7. For the production of electric field radiation type electron source according to item 5 of the scope of patent application -97- This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) 543209 A8 B8 C8 D8 6. Application scope of patent 3 ( Please read the precautions on the back before filling this page.) The manufacturing method, after forming the insulating film on the surface of the semiconductor microcrystals, in an environment containing oxides or nitrides, at a temperature above 60 ° C To perform the heat treatment of the rapid heating method. 8. The manufacturing method of an electric field emission type electron source according to item 5 of the patent application, wherein after the formation of the insulating film on the surface of the semiconductor microcrystals, the temperature is above 60 ° C in an inert gas environment. Annealed by the rapid heating method. 9. The method for manufacturing an electric field emission type electron source according to item 5 of the patent application, wherein after the formation of semiconductor microcrystals, annealing is performed in a vacuum or in an inert gas. 10. The method for manufacturing an electric field emission type electron source according to item 5 of the patent application, wherein the semiconductor layer is formed on a conductive substrate and then annealed in a vacuum or an inert gas. 1 1. The manufacturing method of the electric field radiation type electron source according to item 5 of the scope of patent application, wherein one or more of the following three processes are performed at least two of the following three processes respectively; The first treatment process: after the formation of the insulating film on the surface of the semiconductor microcrystal, the annealing treatment is performed at a temperature below 700 ° C in a vacuum, an inert gas, a forming gas, or a nitriding gas, and At least one of the annealing treatments using a defect-compensable gas; the second treatment process: the heat treatment by rapid heating method at a temperature of more than 600 ° C in an environment containing an oxidation type or a nitride type; The third treatment process: the annealing process of the rapid heating method is performed at a temperature of 600 t or more in an inert gas environment. This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) -98-543209 A8 B8 C8 D8 6. Application for patent scope 4 1 2. Manufacture of electric field emission type electron source such as item 5 of patent scope A method in which an annealing treatment in hydrogen, a hydrogen-based irradiation treatment, or a hydrogen-based irradiation annealing treatment is performed at least one of after forming a semiconductor layer, after forming a semiconductor microcrystal, and after forming an insulating film on the surface of the semiconductor microcrystal. . (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210X297 mm) -99-
TW91108459A 2001-04-24 2002-04-24 Field-emission type electron source and method of manufacturing the same TW543209B (en)

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JP2001159625 2001-05-28
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