TW541577B - Process for fabricating semiconductor structures and devices utilizing the formation of a compliant substrate for materials used to form the same and including an etch stop layer used for back side processing - Google Patents

Abstract

Highly controlled, highly aligned monolithic integration of devices in a high quality monocrystalline material layer (26) with vias (211, 231) fabricated in an underlying monocrystalline substrate (22) in a single monolithic three dimensional architecture (20, 34). Excellent compliancy is achieved in a monolithic semiconductor structure (20, 34) by processes described herein while at the same time fabrication of via openings (211, 231) in the monocrystalline substrate (20, 34) can be made in a controlled, aligned manner to the back side (263) of a high quality monocrystalline film (26). Conductive connections (219, 239) can be made to devices (271, 273) in the high quality monocrystalline layer (26) from its backside (263).

Description

541577 A7 B7

The present application has been filed on July 16, 2001 with the application of the ancient ancient evening Mm by the Jiao Jiaozhi State Patent Application No. 09 / 905,110. FIELD OF THE INVENTION The present invention relates to a semiconductor structure and device and a method for manufacturing the resulting structure, and more particularly, to a semiconductor structure and device and a method for semiconductor structure, and uses thereof, including a single crystal compound semiconductor layer and a single crystal semiconductor substrate, wherein the semiconductor substrate The wood department uses the last name to prevent the layer processing.发明 背景 # Semiconductor devices usually include multiple layers of conductors and semiconductor layers. In general, the properties required for this layer are layer goodness. For example, the migration and interstitial space of the half-four layers will improve when the crystallization of the layers increases. Similarly, the free electron concentration of the conductive layer and the charge transfer and electron energy recovery of the insulating or dielectric film will be improved as the crystallinity of these layers increases. Over the years, attempts have been made to grow a variety of single crystal films on an outer substrate. However, in order to achieve the best characteristics of various single crystal layers, a single crystal film with high crystal quality is required. Attempts have been made, for example, to grow various single crystal layers on substrates such as germanium, silicon, and various insulating materials. These attempts were generally unsuccessful because of the low crystal quality of the resulting single crystal material layer due to the inconsistency of the main crystal and the intercrystalline lattice of the growing crystal. Based on the manufacturing cost of the device starting from the integrated wafer of semiconductor material or the flexible film of the material on the integrated wafer of semiconductor material, various semiconductor devices can be advantageously manufactured using the film at low cost. In addition, if the thin film of high-quality single crystal material can start with a whole wafer such as a silicon wafer,

541577 V. Description of the invention (2) The device structure can achieve the best properties of both silicon and plutonium-quality single crystal materials. Therefore, the current demand for a semiconductor structure is to provide a high-quality single crystal thin film or layer on another single crystal material, and a method of manufacturing the structure. In other words, it is necessary to provide a flexible single crystal substrate with a high-quality single crystal material layer, so the actual two-dimensional growth can be directed to the formation of high-quality semiconductor structures, devices, and growth single crystals with the same crystal orientation as the underlying substrate. Thin ^ product circuit. The single crystal material layer may be composed of a semiconductor material, a compound semiconductor material, and other types of materials such as metals and non-metals. There is also a need for such a semiconductor structure that can be a highly controlled, highly aligned monolithic device in a high quality single crystal material layer having a structure fabricated in a single crystal substrate. The etching termination of the prior art includes a method for thinning all of the wafer layers for bonding of device layers, including a layer transfer method in which a predetermined thin and uniform layer of wafer layers on a hard device wafer is transferred to a desired substrate. Material, that is, on the processed wafer. This layer transfer-like Shi Xi is formed by bonding and chemically describing the Shi Xi device wafer, which is thin and uniformly formed on the termination. It is known to use implanted active impurities such as side, butterfly / germanium, carbon, nitrogen, or oxygen to form the last stop layer. However, the problem is that it is accompanied by the inference in the ^^ to obtain the money-cutting termination layer, such as the problem of the diffusion of the _ | bond H. Furthermore, these previous terminations of money are not designed for complex monolithic blocks. Therefore, it is necessary to resolve the discrepancy between the apparent lattice constants of the two identical knife layers formed from different single crystalline semiconductor materials. Brief Description of the Drawings The present invention is illustrated by examples, and the number of references is not limited by the drawings, and similar elements are indicated, among which the paper size is suitable for SS home standards_) Α4 ^ ϋχ297 public love) 541577 A7 B7 V. Invention Explanation (3 Figs. 1, 2 and 3 are schematic cross-sectional views illustrating the device structure of various specific examples of the present invention; Fig. 4 illustrates the relationship between the maximum achievable film thickness and the uncoordinated lattice between the main crystal and the upper growth crystal; Fig. 5 illustrates High-resolution transmission electron micrographs containing the structure of the single crystal-regulated buffer layer; Figure 6 illustrates the ray diffraction spectrum of the structure containing the single-crystal-regulated buffer layer; Figure 7 illustrates the high-resolution transmission electron display containing the structure of the amorphous oxide layer Photomicrograph; Figure 8 illustrates the diffraction pattern of the structure including the amorphous oxide layer; Figure 9-12 illustrates a schematic cross-sectional view of the device structure formation of another specific example of the present invention; Figure 13-16 illustrates the structure of Figure 9-12 Illustrated device structure of the movable molecular binding structure; σ σ Figure 17-20 illustrates a schematic cross-sectional view of the device structure formation of yet another specific example of the present invention; Figure 2 1-23 illustrates another specific example of the present invention A schematic cross-sectional view of the device structure formation; FIGS. 24 and 25 are schematic cross-sectional views illustrating device structures that can be used in various specific examples of the present invention; FIGS. 26-30 include the compound semiconductor portion, bipolar portion, and MOS portion shown in this text. Description of a part of the integrated circuit cross-section diagram; Figure 31-37 contains a sectional view of a part of another integrated circuit including a semiconductor laser and a MOS transistor shown herein;

Binding

Line -6-

V. Description of the invention (4 • A brief cross-sectional view of the composite semiconductor structure of the present invention for backside processing; FIG. 39 is a brief cross-sectional illustration using FIG. 38 (Figure ㈠, _ a specific example of the present invention is etched from the backside of the composite semiconductor structure Method of processing; FIG. 40 is a schematic cross-section illustrating a method of etching the back side of a composite semiconductor structure using the structure of FIG. 3 according to another specific example of the present invention; FIG. 4U1 illustrates a cross-section using the structure of FIG. 38 according to the present invention. For example, the method of etching the back side of the composite semiconductor structure; Figure 42-4 illustrates the structure of the gate 38 in a cross section. According to a specific example of the present invention, another method of etching the back side of the composite semiconductor structure and forming a channel therein is shown. A different method; FIG. 45 is a schematic cross-section illustrating a method for forming a conductive channel in the composite semiconductor structure of FIG. 3 according to a specific example different from that illustrated in FIGS. 42 and 44; FIG. 46 is a schematic cross-section illustrating the structure of FIG. Specific Example 'Method of Forming a Thermal Channel in a Semiconductor Structure; and FIG. 47 is a schematic cross-sectional view illustrating a method of forming a flexible semiconductor structure according to another specific example. The method of direct-facing laser. Those skilled in the art should understand that the components in the figure are only for simple and clear explanation, and do not need to indicate the size. For example, the size of some originals in the figure can be enlarged relative to other components to Improve the understanding of the specific examples of the present invention. Detailed description of the drawings The present invention relates to the control of the height of the single-dimensional three-dimensional structure of a single-layered material of southern quality such as a iii_v group semiconductor layer with a channel manufactured in the underlying single-crystal substrate A monolithic device arranged in a linear arrangement. The following description can be understood by borrowing 4 541577 A7 B7. 5. Description of the invention (5 The method described in this article can be used to obtain a monolithic semiconductor structure. The method of controlling and arranging is performed on the moon side of the high-quality single-layer film. Therefore, for example, the conductive connection can be made in the device to produce a high-quality single-crystal layer with an overdue backside. In addition, this can be used more efficiently. Area @ on high quality single crystal thin film. In addition, the channel opening can be formed like a hot channel to eliminate the heat of the device in the high quality single crystal layer. #Outside, the channel opening can pass through the single crystal Money is engraved to the backside of the optoelectronic device in the high-quality single crystal layer to provide light produced by the surface-emission field emission, light-emitting diode, or other similar optoelectronic device produced in the light-quality single crystal layer through the vertical hole emission at the bottom. Other exits for light irradiation. In processing the composite semiconductor structure of the present invention, generally, anisotropic etching is performed through the patterning and exposed area of the single crystal semiconductor substrate until the etching stop layer including the metal oxide is exposed. So far, the metal includes different metal elements, such as perovskite oxide metal. According to a specific example, the fabrication is anisotropic wet etching, which is a crystalline name of the semiconductor substrate related to orientation. At the moment, it is terminated at the end of the metal oxide. According to another specific example, the dry etching process is performed on the semiconductor substrate, and it is easy to detect the terminal when it reaches the metal oxide termination film by spectrometry. As for another specific example, these wet and dry precursors can be used to etch the beginning and end of the channel, respectively, to facilitate the overall removal of thirst etching at a relatively high speed, and the adjustment may be performed by dry etching. High-precision endpoint debt measurement technology. Χ Due to the thickness variation and slicing and overlapping of semiconductor wafers, wetting and drying of semiconductor substrates usually require over-etching. For example, Shi Xijing's paper size is applicable to China National Standard (CNS) A4 specifications (210X 297) (Centi) -8 · 541577 V. Description of the invention (6 rounds about 150 / 〇 excessive name engraving to avoid insufficient name engraving. Lauchin ore oxide buffer layer can avoid the process of forming a channel in the semiconductor material layer by the single crystal material layer It was invaded with money by an uncontrollable last name. Therefore, the oxide buffer layer of Maqin Mine can also be used as an etching stop layer. According to another embodiment of the present invention, the channel formed in Qian QI crystal base # is aligned. The exposed part of the etch stop area at the bottom is etched, so that the channel opening or hole passes (extends) the etch stop layer until the back side of the high-quality single crystal material layer. The trowel is violent. The method of the present invention can ensure high quality The channels on the back side of the stand-alone material layer are well aligned with the original ㈣σ starting on the single crystal substrate. Another advantage of the present invention is that the perovskite oxide buffer / etch stop layer is processed in accordance with the present invention. Semiconductors are multiplexed. In other words, one of their roles is to form a permanent adjustment buffer layer in a composite structure that does not match the grid, making it possible to ask. The mouthfeel, relatively thin single crystal material layer can form the smallest crystal And displacement defects caused by the inconsistency of the crystal lattice of the semiconductor substrate. In addition, as mentioned above, the buffer layer can be used as a termination layer in the process of starting the channel in the semiconductor substrate of the composite semiconductor structure. The example is briefly explained in Figs. 38-47, which will be explained in more detail below. Eight. The manufacture of flexible semiconductor structures used as materials for backside processing of the present invention is explained below with reference to Figure U3, followed by examples and Figures 38-47 illustrate the back-side processing of particular interest in this article in more detail. Figure 1 illustrates a schematic cross-sectional view of a portion of a semiconductor structure 20, which is a specific example of the present invention. The semiconductor structure 2G includes a single crystal substrate 22, including a single crystal material The adjustment buffer layer 24 ′ and the single base material layer 26. In this paper, “,” and “Single Crystal” paper size is applicable to China National Standard (CNS) A4 specification (210X 297 mm) 54 1577 A7

Order

F. Description of the invention (8 compound semiconductor material or high-quality junction type material in the additional layer 26 such as metal or non-metallic crystal structure. The single crystal material phase is preferably selected with the underlying substrate and cover material. Layer: The material is in accordance with the single-crystal material layer that is subsequently coated. = The material belonging to the titanium ^ ㈣ layer contains metal oxides, such as soil test metal salt, soil test metal salt, and soil test metal salt. , Test salt, alkaline-earth metal ruthenate, alkaline-earth metal niobate, alkaline-earth metal vanadate, tin-based ore ore, shao acid steel, steel mirror oxygen; and emulsified rhenium. Various kinds of nitrides such as gallium nitride, aluminum nitride, and nitride can also be used as a buffer layer for adjustment. Most of these materials are insulating materials, and nitrogen such as ruthenic acid is generally a conductor. Generally, these materials Both are metal oxides or metal nitrides, and more particularly these metal oxides or nitrides generally contain at least two types of structures. In some special applications, 'metal oxides or nitrides may contain three or more different metal elements The amorphous interface layer 28 is preferably composed of The oxide formed on the surface of 22, and preferably contains silicon oxide. The thickness of layer 28 is sufficient to release the stress caused by the inconsistency between the lattice constant of the substrate 22 and the adjusted buffer layer 24. Generally, the thickness of layer 28 About 0.5 to 5 nanometers. The material of the single crystal material layer 26 can be selected according to the specific structure or application as required. For example, the single crystal structure of the layer 26 can include the IIIA group and the VA that can be selected according to the requirements of the special semiconductor structure. Compound semiconductors of any of group III elements (group III-V semiconductor compounds), mixed group III-V semiconductor compounds, group π (A or B) & νι group A elements (^ ... semiconductor compounds) and mixed II-VI compounds 541577 A7 _ B7 V. Description of the Invention (9) Examples include gallium arsenide (GaAs), indium gallium arsenide (GalnAs), gallium arsenide chain (GaAlAs), indium phosphide (InP), sulfide (CdS), Silver telluride (CdHgTe), zinc selenide (ZnSe), zinc selenide (ZnSSe), etc. However, the single crystal material layer 26 also includes other semiconductors used to form semiconductor materials, devices, and / or integrated circuits Material, metal, or non-metal material. Template 30 of When the material is described below, the appropriate template material in the orientation of the single crystal material layer 26 is attached to select positions for providing nucleation and provide positions for chemical bonding to the surface of the adjustment buffer layer 24. When used, the thickness of the template layer 30 is between Between about 1 to about 10 single layers. Fig. 2 illustrates a cross section of a part of a semiconductor structure 40, which is another specific example of the present invention. The structure 40 is similar to the semiconductor structure 20 described above, but the buffer layer 24 and the single crystal material are adjusted. An additional buffer layer 32 is disposed between the layers 26. In particular, an additional buffer layer silicon is disposed between the template layer 30 and the cover layer of the single crystal material. The additional buffer layer (when the single crystal material layer 26 includes a semiconductor or a compound semiconductor material) (Formed by semiconductor or compound semiconductor material) can be used for lattice compensation when the lattice constant of the adjusted buffer layer cannot be coordinated with the covered single crystal semiconductor or compound semiconductor material layer. FIG. 3 illustrates a cross-sectional view of a portion of a semiconductor structure 34 as another specific example of the present invention. Structure 34 is the same as structure 20, but structure 34 includes an amorphous layer 36 ' instead of a buffer layer 24 for conditioning, an amorphous interface layer 28, and an additional single crystal layer 38. As described in detail below, the amorphous layer 36 is a buffer layer and an amorphous interface layer that are first adjusted in a similar manner as described above. A single crystal layer 38 is then formed (by epitaxial growth) to cover the single crystal conditioned buffer layer. Adjusting buffer L _—___- 12- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 x 297 mm) V. Description of the invention (10 layers === In the process, the buffer layer for adjustment is converted to none The shaping layer comes from the adjusted buffer layer and the medium 36 can be used as a temple or without amalgamation. Therefore, an amorphous layer is formed between the layers% and the additional single crystal layer stress, and the post-processing is provided. The flexible substrates between the release layers 22 and 38. The actual formation of the single crystal material layer 26 and the aforementioned processes for the formation of the single crystal material layer 26 is suitable for growing the single crystal material layer on the single crystal substrate. The process described in 3 (including the replacement of the single crystal with an amorphous oxide layer) is better for the growth of #s β " ^ a early Japanese material layer, because it stresses any stress in the relaxation layer 26. = = Crystal layer 38 may include any of the single crystal materials described in this application Γ half == material of punch layer 32. For example, when single crystal material layer 26 encapsulates a conductor or a compound semiconductor material, the single crystal compound material β I s earlier said that the five private or Z of the present invention-a specific example, the additional single crystal layer 38 can be used in the layer Qingcheng = Covered by fire 'or used as a stiffener for the subsequent formation of the single crystal material layer 26. Therefore,' the better thickness of layer 38 is to provide layer 26 growth (at least f) is a suitable template 'and is thin enough to form layer 38 substantially There is no defect on the material at an early date. According to another specific example of the present invention, the additional single crystal material layer 38 includes a single material (such as the material of the single crystal layer 26 described above), which is then sufficient to form Z f in the layer M. In this case, the semiconductor structure of the present invention does not include a single crystal material, which is 26. In other words, the semiconductor structure of this specific example includes only a paper size that is arranged on the upper paper scale and is applicable to the TSS Standard (CNS) A4 specification (210 & 7 Publications) 13 541577 V. Description of the invention (11 single crystal layer on the amorphous oxide layer 36 described below. The following non-limiting, illustrative examples illustrate the yttrium structures 20, 40 and 34 used in various specific examples of the present invention. Various combinations of materials. These examples are only for illustration, and the present invention is not limited by these illustrative examples. Example 1 According to the specific example of the present invention, the single crystal substrate 22 is in the direction of (ι〇〇) Oriented evening substrate 1¾ A stone evening substrate may be, for example, Generally, it is used to manufacture the shixi substrate of the metal oxide semiconductor (CM0S) integrated circuit with a diameter of about-millimeters. According to a specific example of the present invention, the adjusted buffer layer 24 is a single crystal layer of SrzBai-zT103. Among them, 2 is between 0 and 1, and the amorphous intermediate layer is a layer of silicon oxide (Si0x) formed at the interface between the Shixi substrate and the regulating: punching layer. The Z value is selected to obtain $ Xi. A lattice constant that closely matches the corresponding lattice constant of the layer 26 to be formed later. The thickness of the adjusted buffer layer is between about 2 and about 100 nanometers (nm) and the thickness is preferably about 5 nanometers. Generally, the adjusted buffer layer is thick enough to isolate the single crystal material layer 26 from the substrate to obtain the desired electrical and optical properties. Layers thicker than 100 nanometers usually provide a little extra benefit, but add unnecessary costs, however, thicker layers can be made if needed. The thickness of the amorphous intermediate layer of the oxidized stone is between about 0.05 and 5 nanometers, and preferably about 1 to 2 nanometers. According to another specific example of the present invention, the single-crystal material layer 26 is an atheized gallium (GaAs) or a sanded gallium (GaAs) with a thickness of about 0.5 μm to 100 μm (m) and preferably a thickness of about 0.5 μm to about μm. A1GaAs) compound semiconductor layer. Its thickness depends on the application of the layer to be prepared. In order to assist Shi Shenhualu or Pinghua Aluminium in the orientation and growth of oxides on early oxides, it is covered by the oxide gutter, paper, silver scale, and national standard (CNS). ) • 14-

The layer forms a template layer. Template layer comparison

Sr-Ga-O, or Sr A1 n-Ti-As, Sr_〇-As,

Sr 〇a 〇. 1. The fine specific example, 1-2 single layer of Ti-As or

Sr-Ga-〇 to illustrate the layer of successful growth. Example 2 According to another specific example of the present invention, the single substrate 22 is a silicon substrate as described above. The buffer layer is a three-dimensional orthorhombic phase, or a barium zirconate or a osmium salt, and the + + + + y, said lice compound, and is based on silicon Material and adjustment buffer layer ^ ^^ Amorphous intermediate layer of oxidized stone. The thickness of the buffer layer is adjusted to ~ 2 nanometers, and the thickness is preferably at least 5 nanometers # to ensure proper mouth and day and mouth mouthshell, and is made of single crystal ^ Zγ〇3, β & Zγ〇3 , SrHf〇3,

BaSnO3 or B side 3 is formed. For example, a single crystal oxide layer of B_3 can be grown at a temperature of 700 C / deck. The crystal structure of the obtained crystalline oxide exhibits a 45-degree rotation with respect to the silicon lattice structure of the substrate. The adjustment buffer layer formed by such osmate or osmate materials is suitable for the growth of a single crystal material layer including a compound semiconductor material in the indium scale system, and the compound semiconductor material may be, for example, phosphating Indium (InP) Indium gallium (InGaAs), aluminum indium arsenide (A1InAs), or aluminum gallium indium arsenide phosphide (AlGalnAsP) has a thickness of about 10 nanometers to 10 micrometers. Suitable templates for this structure are ι-ίο single-layer zirconium-arsenic (Zr_As), thorium · phosphorus (Zγ · ρ), thorium · arsenic (Hf ·

As) gives-^ 4 (Hf-P), Ming H (sr-〇_As), IgH (Sr-OP), Barium-O-As, Ba-O-As, In-ft (In- Sr-O), or barium-oxygen province (BaO-P), and is preferably one of these materials in a 1-2 monolayer. By way of example, the buffer layer is adjusted for barium-zirconium, terminated with a 1-2 single layer of zirconium, and then a 1-2 single layer of arsenic is deposited to form a Zr-As template. Then on the template layer, the disc_layer of the system is layered. 15- This paper size is in accordance with China National Standard (CNS) A4 (210X297 mm).

Binding

541577 A7

The compound nitrogen conductor material grows. The lattice structure of the obtained compound semiconductor material exhibits a 45-degree rotation with respect to the lattice structure of the adjusted buffer layer, and is inconsistent with the lattice of (ι〇〇) ΐηρ by less than 2.5%, and preferably less than about 1.0. %. Example 3 According to another specific example of the present invention, the growth of a single crystal material oriented epitaxial film including a group of two or six materials suitable for covering a silicon substrate is provided. The substrate is preferably a silicon wafer as described above. A suitable material for the adjustment buffer layer is SrxBanTi (where X is 0 to 1), its thickness is about 2-100 nm, and the thickness is preferably 5 nm. When the single crystal layer includes a compound semiconductor material, the group two or six compound semiconductor material may be, for example, zinc selenide (ZnSe) or zinc selenide (ZnSSe). The template suitable for this material system contains 1-10 single layers of zinc · oxygen (Zn_〇), followed by 1-2 single layers of excess zinc, followed by selenization of zinc on the surface. In addition, the template layer has 1-10 early layers of sulfur-sulfur (Sr-S) followed by ZnSeS. Example 4 This specific example of the present invention is an example of the structure 40 illustrated in FIG. 2. The substrate 22, the adjustment buffer layer 24, and the single crystal material layer 26 are all the same as those described in Example 1. In addition, an additional buffer layer 32 may be used to alleviate the stress caused by the mismatch between the lattice of the buffer layer and the lattice of the single crystal material. The buffer layer 32 may be a layer of germanium or GaAs, aluminum germanium arsenide (AlGaAs), indium germanium dish (inGaP), scaled aluminum germanium (AlGaP), indium gallium arsenide (InGaAs), aluminum gallium phosphide (AllnP), GaAsP or InGaP stress-compensated superlattice. According to another purpose of the specific example, the buffer layer 32 includes a GaAsxPNx (where X is 0 to 1) superlattice. By changing the values of X and y, the lattice constant can be between the lower limit and the upper limit of the entire superlattice, so that it can be covered with the lattice constant of the underlying oxide. ) A4 size (210X297 mm)

Binding

Line (14) Fifth, the description of the invention (compound semiconductor material in this example) "other compound semiconductor material composition 7". Change the lattice constant of layer 32 in the same way. Super C change 5. -100 nanometers, and thick households: The thickness of the cup i σ day 4 is about 100-200 nanometers. The connection can be the same as described in the example! In addition, the buffer Chess board is 50 nm and it is better to produce A2 layer 2. The thickness of the layer is 1-rare and it is good, the single crystal is 2-20 nm. Or, the single crystal material layer (in this example, a compound semiconductor material) is used as a branch or early layer to cover the subsequent single crystal germanium deposition, when the nuclei position. The gill or titanium in the early layer provides bismuth. Single-layer germanium nucleation site I junction Example 5 This example illustrates the materials used in the structure 40 as illustrated in Figure 2. The material 22 adjusts the buffer layer 24, the single-crystal material layer 26, and the template layer 30 are in the soil. The same is described. In addition, an additional buffer layer is interposed between the adjustment buffer layer and the covered single crystal material layer. The buffer layer (including the semiconductor material A premature material) can be, for example, a layer of indium gallium arsenide (InGaAs) or indium aluminum arsenide (I ^ As). According to one purpose of this specific example, the buffer layer of Ebu contains InGaAs, where the indium composition is 〇 to about 50%. The thickness of the additional buffer layer η is preferably about 10-30 nm. The composition of the buffer layer is changed from GaAs to InGaAs to provide the lower single crystal oxide material and the single crystal material of the cover layer. (In this example, the compound semiconductor material) matches the lattice. If there is a lattice mismatch between the adjusted buffer layer 24 and the single crystal material layer 26, the buffer layer is particularly advantageous. V. Description of the invention (15) Examples 6 This example provides the enumerated materials used in structure 34, as described in the appropriate material 22, template layer 30, and single crystal in Figure 3. 〃 The above-mentioned amorphous layer 36 is an amorphous oxide layer, which is suitable for A combination of forming an intermediate layer material (such as the layer 28 material described above) and adjusting the above-mentioned layer 24). For example, the amorphous layer 36 may include SrzBa 丨 · ζΤι03 (where 2 is between 0 and 1) ) Of the people = and or at least part of it, forming a type 2 fire 2 process t 疋The thickness of the mold layer 36 may vary depending on the application, and may depend on the insulating properties required for the layer 36, the type of single crystal material including the layer 26, etc. According to one of the purposes listed, the thickness of the layer 36 is about 2 nanometers. The meter to ㈣ is preferably about 1-10 nanometers, and more preferably about 5-6 nanometers. ', Κ layer 38 includes a single two that can be oriented to grow on a single crystal oxide material', such as: to form a regulating buffer layer The material of 24. According to the method, layer 38 includes the same material as those including layer 26. For example, if the heart: Γ: 38, then the layer 38 also includes GaAs. However, according to the present invention: and = Xing Ϊ Γ can be included A material different from that used to form the layer 26. According to a specific example of the present invention, the layer 38 has a thickness of about 1 single layer to about 100 single layers. 4 Reference Γ Two substrates 22 are single crystal substrates, such as single crystals, gallium: gallium: materials: in a similar manner, the number of daily grid cells of the core material of the adjusted buffer layer must match, or one of the crystals Paper scale ^ Broken ^^ (210 X 297 public love) -18-541577 A7 _____ B7 V. Description of the invention (16) The orientation needs to be rotated relative to other crystal orientations to achieve a substantially consistent lattice constant. In this article, the terms “substantially equal” and “substantially coincide” mean that the lattice constants are sufficiently similar to each other so that a high-quality crystalline layer can grow on the lower layer. Figure 4 does not illustrate the relationship between the thickness that can be achieved by a growing crystal layer of high crystal quality as a function of the inconsistency between the main crystal and the growing crystal. Curve 42 illustrates the boundaries of high crystalline quality materials. The area to the right of curve 42 represents a layer with a large number of defects. If there is no inconsistent crystal lattice, theoretically, a high-quality oriented epitaxial layer can be grown on the main crystal. When the incoherence in the lattice constant increases, the thickness of the achievable high-quality crystal layer decreases rapidly. As for the reference point, for example, if the lattice constant between the main crystal and the growth layer does not match more than 2%, a single crystal orientation epitaxial layer exceeding about 20 nm cannot be achieved. According to a specific example of the present invention, the substrate 22 is a (100) or (111) -oriented single-day Japanese-Japanese-Japanese-Yen 'and the adjusted buffer layer 24 is a lithium barium titanate layer. The lattice constants of the kappa shells between these two materials are achieved by the crystal orientation rotation of the titanate material at 45 degrees relative to the crystal orientation of the silicon substrate wafer. If the structure of the amorphous interface layer 28 (the silicon oxide layer in the example) is sufficiently thick, the titanate can be reduced, and the crystals of the titanate layer that can lead to the main stone and the growing layer can be reduced. Any inconsistent stress in the lattice constant. Therefore, according to a specific example of the present invention, a south-quality, thick single crystal titanate layer can be achieved. Still referring to FIGS. 1-3, the layer 26 is a layer of oriented single crystal material with long growth, and the 亥, ’σ positive material is also characterized by a crystal lattice constant and a crystal orientation. According to a specific example of this month, the lattice constant of layer 26 is different from the lattice constant of layer 22. The high crystalline quality in the orientation-attached long single crystal layer is not achieved, so the adjusted buffer layer product is of the south crystalline quality. In addition, in order to achieve high crystallinity in layer 26

541577 A7 B7 V. Description of the invention (17 quality, so in this case Φ. -4; AL · a 〇〇〇 and the lattice constant of the buffer layer and the growth crystal between the main and the day-to-day early crystal adjustment Substantial coordination. Suitable material selection, the substantially consistent lattice constant can be achieved by rotating the crystal orientation of the growing crystal relative to the orientation of the main crystal. For example, if the growing crystal is atheized gallium, atheized aluminum gallium, selenium Or selenium zinc selenide, and the adjusted buffer layer is single crystal srzBai-zTi〇3 ', the lattice constant of the two materials can be substantially matched, and the crystal orientation of the growth layer is also relative to the main single crystal oxidation The orientation of the object is rotated by 45 degrees. The same 'if the main material is a wrong acid inscription or pin, or for acid recording or locking, or tin oxide', and the compound semiconductor layer is Wei surface or atheized indium, or a deified marriage The real coordination of the crystal lattice constant can be achieved by the orientation of the crystal layer with a rotation of 45 ° relative to the main oxide Λ # A 'emulsification day. In some cases, linear and growing single crystal materials Interlayer crystalline semiconductor buffer layer can be used to reduce The stress in the growing single crystal material layer that will cause small differences in the lattice constants. Therefore, the better crystalline quality in the growing single crystal material layer can be obtained. The following examples illustrate the manufacture of the semiconductor material of the present invention-a specific example, as shown in Fig. 3. The method of describing the structure. The method begins by providing a substrate including broken or germanium conductors. According to a preferred embodiment of the present invention, the semiconductor substrate = (100) oriented Shi Xi wafer. The substrate is preferably an axis or at most 4 Axis two of the degree: At least a part of the semiconductor substrate has an exposed surface. Other: The two substrates (such as the following) may include other structures. In this article, the meaning of the ~ ~ Road 1 + Siyin jb substrate surface has passed Cleaning to remove any oxide = other foreign substances. As is known to the naked stone Xi is highly reactive /, and two: that is to form a natural oxide. ,, the naked, the word will be wrapped. 6 Yong Daran Oxygen can also intentionally grow thin silicon oxide on semiconductor substrates:

541577 A7 B7 V. Description of the invention (18) Silicon is basically not the method of the present invention. In order to make the single crystal oxide layer covered on the single crystal substrate oriented and grow, it is necessary to remove the natural oxide layer first to expose the crystal structure of the underlying substrate. The following methods are preferably performed with molecular beam orientation epiphysis (MBE), but other orientation epiphytic processes can also be used in the present invention. Natural oxides can be thermally deposited by first depositing, locking, or combining barium, or other alkaline earth metals or alkaline earth metals in a MBE device. When lithium is used, the laminate is heated to a temperature of about 7500C to react lithium with the natural silicon oxide layer. Lithium can reduce the silicon oxide layer, leaving no oxidation surface. The resulting surface (presenting an ordered 2x1 structure) contains gills, oxygen, and silicon. The ordered 2 X 1 structure forms a template for the ordered growth of the single crystal oxide cap layer. The template provides the required chemical and physical properties and becomes the subject of the crystalline growth of the cover layer. According to another specific example of the present invention, natural silicon oxide can be transformed, and alkaline earth metal oxides such as lithium oxide, lithium barium oxide, or barium oxide can be deposited on the surface of the substrate by MBE at low temperature, and then The structure is heated to a temperature of about 75 ° C to prepare a substrate surface for growing a single crystal oxide layer. At this temperature, the solid state reaction between the gill oxide and the natural silicon oxide causes the natural silicon oxide to be reduced, leaving an ordered 2x1 structure with lithium, oxygen, and silicon on the surface of the substrate and forming a subsequent ordered single crystal oxide layer. Growth template. After removing the oxidized stone from the surface of the substrate according to a specific example of the present invention, the substrate is cooled to a temperature of about 200-80 ° C, and a layer of titanate gills is grown on the template layer by molecular beam orientation epigenesis. MBE The process is to open the shutter in the MBE device to expose strontium, titanium, and oxygen sources. The ratio of gill and titanium is about 1: 1. The partial pressure of oxygen is first set to the maximum value, so that the chemical dose of strontium titanate is about 〇3_ 〇 · 5 does not come / grow at the rate of the clock. After the growth of the first acid recording, the oxygen points are repeated 541577 A7 B7 V. Description of the invention (19) ----- Increase exceeds the maximum value of Killer. The force of the oxygen causes the growth of the amorphous silicon oxide layer at the interface between the underlying substrate and the growing lithium titanate layer. The growth of the silicon oxide layer is caused by the diffusion of oxygen through the growing gill carbonate layer to the interface. The stone evening reaction on the surface of the stone evening substrate is formed. The acetic acid pin grows into a (100) single crystal with a (100) crystal orientation rotated at 45 degrees relative to the underlying substrate. Because the silicon substrate and the growing crystal The small amount of lattice constants are inconsistent and stress release may occur in lithium titanate In the amorphous silicon oxide intermediate layer. After the lithium titanate layer has grown to the required thickness, cover the 3 single crystal lithium titanate with a template layer to perform the subsequent growth of the required epitaxial layer of the single crystal material. For example, for Subsequent growth of the single crystal compound semiconductor material layer of gallium arsenide, MBE growth of the lithium titanate single crystal layer is by using K2 single layer of titanium, 1-2 single layer of titanium_oxygen or 1-2 single layer of strontium -Oxygen terminates growth cover. After the cover layer grows, arsenic is accumulated to form Ti-As bond, Ti-0-As bond, or Sr-0-As bond. Any of these can form deposits and form Suitable template for gallium arsenide single crystal layer. After the template is formed, gallium reacts with arsenic and gallium arsenide forms. In addition, gallium can be deposited on top of the hafnium layer to form an Sr-o-Ga bond and then with gallium GaAs is introduced. FIG. 5 is a high-resolution transmission electron micrograph (TEM) of a semiconductor material manufactured according to a specific example of the present invention. The single-crystal SrTi03-adjusted buffer layer 24 is oriented to grow on the silicon substrate 22 During the growth process, an amorphous interface layer 28 is formed, which is released due to the inconsistency of the crystal lattice 〇aAs compound semiconductor layer 26 is then oriented using the template layer 30 to grow. Figure 6 illustrates the x-ray diffraction spectrum of a structure including a GaAs single crystal layer 26 grown on a silicon substrate 22 using an adjusted buffer layer 24 The peak of the spectrum shows ^ paper size "^^ Standard (CNS) A4 size (210 X 297 mm) 541577 A7 B7 V. Description of the invention (20) Adjusted buffer layer 24 and GaAs compound semiconductor. Body layer 26 is single crystal And (100) orientation. The structure illustrated in FIG. 2 can be formed by the above-mentioned method by adding an additional buffer layer deposition step. The additional buffer layer 32 is formed by covering the template layer before depositing the single crystal material layer. If the buffer layer is a single crystal material including a compound semiconductor layer, the superlattice may be deposited in MBE on, for example, the template described above. If the buffer layer is a single crystal material layer including germanium, the above process can be changed to cover the single crystal layer of gill titanate with a final layer of lithium or titanium, and then deposit germanium to react with strontium or titanium. The germanium buffer layer can then be sunk directly on top of the template. The structure 34 illustrated in FIG. 3 can form an amorphous oxide layer on the substrate 22 by growing the adjusted buffer layer as described above, and grow and form a semiconductor layer 38 on the adjusted buffer layer. The adjusted buffer layer and the amorphous oxide layer can be re-exposed to the annealing process sufficient to change the crystal structure of the adjusted buffer layer from a single crystal to an amorphous shape, thus forming an amorphous [amorphous oxide layer and a new amorphous adjustment buffer The combination of layers forms a single amorphous oxide layer 36. Layers are then grown on layer 38. Alternatively, an annealing process may be performed after the layer is grown. -According to a specific example of the present invention, the layer 36 is formed by exposing the substrate 22, the adjustment buffer layer, the amorphous oxide layer, and the single crystal layer 38 to a maximum temperature of about 100 GC 'and a processing time of about 5 seconds to About 1 () minutes of rapid thermal return. However, other suitable annealing processes can also be used to convert the conditioning and punching layers into the amorphous layer of the present invention. For example, the laser annealing, electric shape: Π general " thermal annealing process (in an appropriate environment) can be used 8 "When the general thermal annealing is used to form the layer 36, the layer 30 is required

Binding

Thread This paper is suitable for Λ + ㈣ turn standard (CNS -23- X 297 mm) 541577 A7 B7

Overpressure of one or more components' to prevent degradation of layer 38 during the annealing process. For example, when the layer 38 contains GaAs, the annealing environment preferably contains an overpressure of arsenic to mitigate the degradation of the layer 38. As mentioned above, the layer 38 of the structure 34 may comprise any suitable material for the layers 32 or 26. Therefore, the deposition or growth methods described for layers 32 or 26 can be used for depositing layer 38. FIG. 7 is a high-resolution TEM of a semiconductor material manufactured according to the specific example of the present invention illustrated in FIG. 3. FIG. According to this specific example, the high-crystallinity-modifying buffer layer is oriented and grown on the silicon substrate 22. During this growth process, an amorphous interface layer is formed as described above. Next, an additional single crystal layer 38 including a compound semiconductor layer of GaAs is formed on the adjustment buffer layer, and the adjustment buffer layer is exposed to the annealing process to form an amorphous oxide layer 36. FIG. 8 illustrates an X-ray diffraction spectrum of a structure including an additional single crystal layer 38 including a GaAs compound semiconductor layer and an amorphous oxide layer 36 formed on a silicon substrate 22. As shown in FIG. The peak in the spectrum shows that the GaAs compound semiconductor layer 38 is single crystal and is (100) oriented, and the display layer 36 is amorphous with a peak reduction of about 40 to 50 degrees. The method described above illustrates a method of forming a semiconductor structure including a silicon substrate, a covering oxide layer, and a semiconductor layer including an atheized gallium compound by molecular beam orientation epitaxy. The method can also be used for chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), orientation epitaxy (MEE) to promote migration, atomic layer orientation epitaxy (ALE), physical vapor deposition (PVD), chemical solutions Deposition (CSD), pulsed laser deposition (pld), etc. In addition, other single crystal adjustment buffer layers, such as alkaline earth metal titanates, malates, osmates, tantalates, vanadates, ruthenates, and niobates, can be grown by similar methods. ___- 24-This paper size applies to China National Standard (CNS) A4 (210X 297 mm)

Binding

Line 541577 A7

Alkali earth metal tin-based perovskite, lanthanum aluminate, lanthanum oxide lanthanum, and oxide. In addition, by similar methods such as MBE, other single crystal material layers including Group III, V, and Group 26 single crystal compound semiconductors, semiconductors, metals, and non-metals can be deposited to cover the single crystal oxide adjustment buffer layer. Various single crystal material layers and single crystal oxide adjustment buffer layers use suitable templates for the growth of the initial single crystal material layer. For example, if the adjusted buffer layer is an alkaline earth metal osmium salt, the oxide may be covered with a thin layer of rhenium. After plutonium deposition, arsenic or phosphorus can be deposited and made to react with plutonium as a precursor to deposit indium gallium indium, indium aluminum arsenide, or indium phosphide, respectively. Similarly, if the single crystal oxide-adjusted buffer layer is an alkaline earth metal osmium salt, the oxide layer may be covered with a thin layer of rhenium. After deposition, arsenic or phosphorus can be deposited and made to react with plutonium as a precursor to grow the indium gallium arsenide, indium aluminum arsenide, or indium phosphide layers, respectively. In the same way, the titanate chain can be covered with a layer of oxygen or oxygen, and the barium titanate can be covered with a layer of barium lock and oxygen. After each of these depositions, arsenic or phosphorus is deposited and reacts with the covering material 'to include a single crystal material layer of compound semiconductors such as Shishenhua copper, Kunhuashao indium and indium phosphide. The formation of the device structure of another specific example of the present invention is explained with reference to the cross-sectional view of Fig. 9 · 12. As in the specific examples described previously in FIGS. 1-3, this specific example of the present invention includes a method for forming a flexible substrate using a single crystal oxide orientation epitaxial growth, such as forming the adjustment buffer layer 24 described above with reference to FIGS. 1 and 2 and the foregoing Referring to the amorphous layer 36 in FIG. 3, and forming a template layer 30. However, the specific examples illustrated in Figures 9-12 use a template including a surfactant ' to assist the growth of layers and interlayer single crystal materials. Referring to FIG. 9, the amorphous intermediate layer 58 is formed by the substrate -25-

This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) 541577 A7 B7 V. Description of the invention (23) 52 oxidation, on the substrate at the interface between the substrate 52 and the growth adjustment buffer layer 54 Grow, which is preferably a single crystal crystalline oxide layer. Layer 54 is preferably a single crystal oxide material, such as a single crystal layer of SrzBa ^ TiOK where z is 0 to 1). However, layer 54 may also include any of the aforementioned compounds, with reference to layer 24 in FIGS. 1-2, and any of the compounds in layer 36 in layer 3, which are referred to layers 24 and 28 in FIGS. 1 and 2. form. The layer 54 is formed by lithium (Sr) on the terminal surface indicated by the dashed line 55 in FIG. 9, and then a template layer 60 is added, which includes an interface active agent layer 61 and a cover layer 63, as illustrated in FIGS. 10 and 11. The interfacial active agent layer 61 may include (but is not limited to) elements such as A1, In, and Ga, but it depends on the composition of the layer 54 and the single crystal material cover layer for the best results. According to one specific example, gallium (Ga) is used in the interface active layer 61 and used to improve the surface and surface energy of the layer 54. Preferably, as shown in FIG. 10, the interface active agent layer 61 is formed by molecular beam orientation epitaxy (MBE) orientation epitaxy to a thickness of one to two monolayers, but other orientation epitaxy methods can also be used, such as Chemical Vapor Deposition (CVD), Metal Organic Chemical Vapor Deposition (MOCVD), Orientational Epiphysis (MEE) for Ascension, Atomic Layer Orientation (ALE), Physical Vapor Deposition (PVD), Chemical Solution Deposition (CSD) , Pulsed laser deposition (PLD), etc. The interfacial active agent layer 61 is then exposed to a Group 5 element such as God to form a cover layer as illustrated in FIG. The interfacial active agent layer 61 may be exposed to a variety of materials to produce a cover layer 63 such as (but not limited to) As, P, Sb, and N. The interface active layer 61 and the cover layer 63 are combined to form a template layer 60. The single-crystal material layer 66 (which in this example is a compound semiconductor such as GaAsN) is then passed through MBE, CVD, MOCVD, MEE, ALE, PVD, CSD, -26- This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 541577 A7 B7 V. Description of the invention (24) PLD and other deposits form the final structure illustrated in FIG. 12. Figures 13-16 illustrate possible molecular bonding structures of the GaAsN compound semiconductor structure formed in the specific examples illustrated in Figures 9-12 of the present invention. In particular, Figures 13-16 illustrate the growth of GaAsN (layer 66) on the end-capping surface of barium titanate hafnium single crystal oxide (layer 54) using a surfactant with a template (layer 60). The growth of the single crystal material layer 66, such as GaAs, on the adjustment buffer layer 54, such as barium hafnium titanium oxide, on the amorphous interface layer 58 and the substrate layer 52 (both include the aforementioned reference layers 28 and 1 in FIGS. 1 and 2 respectively) The material of 22) shows that the critical thickness is about 1000 Angstroms, in which secondary primary (2D) and tertiary primary (3D) growth transitions are generated because they include surface energy. In order to maintain the actual layer by layer growth (Frank Van der Mere growth), the following relationship must be satisfied: δ STO> (S INT + S GaAs) where the surface energy of the single crystal oxide layer 54 needs to be greater than that of gallium on the surface of the GaAs layer 66 The surface energy of the amorphous interface layer 58 on the energy. Because the formula cannot be satisfied, a template-containing surfactant is used, as described in Figures 10-12 above, to increase the surface energy of the single crystal oxide layer 54 and also convert the template's crystal structure to the original GaAs. The layer is flexible like a diamond structure. Fig. 13 illustrates the molecular bonding structure of the barium-terminated surface of the barium-titanium single crystal oxide layer. The gallium and aluminum interface active agent layer is deposited on the barium-terminated surface and is bonded to the surface, as illustrated in FIG. 14, which reacts to form a single layer of Al2Sr including the molecular bond structure illustrated in FIG. 14. A layer that forms a diamond-like structure with sp3 mixed capped surface that is flexible with compound semiconductors such as GaAs. The structure is then exposed to As to form a layer of As, as shown in Figure 15. The GaAs layer is then nitrided, and the GaAs is deposited to form the points illustrated in Figure 16. -27- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) Γ41577 V. Description of the invention (25 = : It has been obtained by 2D growth. Yang can grow to the thickness of other conductors, ions, devices, or integrated circuits. Soil testing metals such as group M are better elements for forming the covering surface of the early-crystal oxide layer 54 , Because it can form the required molecular structure with aluminum.… ^ In this specific case, the surfactant with the template layer assists the formation of various material layers containing three or five compounds to form high-quality semiconductor structures, devices, and integrated circuits. Circuits. For example, 'template-containing surfactants are used for mono-blocks of single crystal materials, such as layers including germanium (Ge) to form high-efficiency photocells. Referring again to 17-20, another specific aspect of the present invention is The formation of the device structure of the example is described in section. This specific example is used to form a flexible substrate, which is oriented to form a long single crystal oxide on silicon and then oriented to grow a single crystal on the oxide. Adjustment buffer layer 74 such as single crystal oxide The layer is prior to the substrate layer ", such as the amorphous interface layer 78 grown on silicon, as illustrated in Figure π. The single crystal oxide layer% may be composed of any of the materials described with reference to layer 24 in Figures 1 and 2, but without The shaping interface layer 78 preferably includes any of the materials of the layer 28 previously described with reference to the drawing. The substrate 72 (preferably silicon) may also include any of the materials of the substrate 2 2 previously described with reference to FIGS. 1-3. Next, the Shi Xi layer 81 is deposited on the single crystal oxide layer 74 via MBE, CVD, MOCVD, MEE, ALE, PVD, CSD, PLD, and as shown in FIG. 18, its thickness is hundreds of Angstroms. However, the thickness is preferably about 50 angstroms. The thickness of the single crystal oxide layer 74 is preferably about 20 to 100 angstroms. Next, in the presence of a carbon source such as a block or methane, for example, about 8000 c to 1 〇〇〇 It is subjected to rapid thermal annealing at its temperature to form a cover layer 82 and a silicon oxide amorphous paper. Standard Paper® National Standard (CNS) A4 specification (2i × 297 public love) 541577 A7

1577 A7

5. Description of the invention (28) layer) Bonding is a weak covalent bond. Sr will be precipitated with two different types of bonds, and the part of its charge will reach the oxygen atom in the lower regulating buffer layer 104 including SrzBai zTi03, causing one of the ionic bonds to precipitate, and its covalent charge will The other parts will be supplied to A1 in the same way that Zintl does to the material. The amount of charge transfer depends on the relative negative electrical properties of the elements in the template layer 130 and the distance between the atoms. In this example, A1 is assumed to be sp3 hybrid and can be easily bonded to the single crystal material layer 126, which in this example includes the compound semiconductor material GaAs. The flexible substrate manufactured using the Zintl type template used in this specific example can absorb large stresses without significant energy cost. In the above example, the bond strength of A1 is adjusted to change the volume of the SrAh layer, so that the device can be transformed into special applications, including single blocks of Group III and Si devices, and the high level for CMOs technology- k Monolithic body of borrowing material. Obviously, these specific examples having a structure of a compound semiconductor portion and a group semiconductor portion are described in particular to illustrate the present invention, but not to limit the present invention. It includes the multiplicity of other combinations and other specific examples of the invention. For example, the present invention includes the manufacture of single crystals that include other layers such as metal and non-metal layers that can be used to form semiconductor structures, devices, and integrated circuits.

GaAs layer method. In particular, the present invention includes structures and methods of forming flexible substrates for manufacturing semiconductor structures, devices, and integrated circuits. By using specific examples of the present invention, today's simpler integrated circuits include semiconductors and compound semiconductor materials, as well as other devices that are used to form with semiconductors or compound semiconductor materials that are easier or easier and / or easier to form in semiconductors or compound semiconductor materials.晶 层。 Crystal layer. This reduces the size of the device, reduces manufacturing costs, and increases yield and reliability. This paper is a national standard (5 ^ s) A4 size (21 (^ 297mm)) 1577 V. Description of the invention (29 According to a specific example of the present invention, a single crystal semiconductor or compound semiconductor wafer can be used. A single crystal material is formed on the wafer. In this way, the wafer basically manufactures semiconductor electronic components, 'processing,' wafers covering the single crystal layer of the wafer. Therefore, electrical components can be at least 200 microns in diameter, And it may be formed in semiconductor materials on wafers of about micrometers. Due to the use of such substrates, which are relatively cheap, processing, wafers will be placed on a relatively more durable and easier to manufacture base material, Overcome the fragile nature of compound semiconductor or other single crystal material wafers. Therefore, integrated circuits can be formed so that all electrical components, especially all active electronic devices, can be formed or used in the single crystal material layer, even the substrate itself Single crystal semiconductor materials can also be included. Use of compound semiconductors other than monolithic materials should be reduced, and other devices should be used because they are relatively small and fragile substrates (such as general compound semiconductor crystals). ) In comparison, larger substrates can be more economical and easier to handle. Figure 24 briefly illustrates the device structure% of another specific example in cross section. Device structure 50. 3 single semiconductor substrate 52, preferably single crystal silicon Wafer. The single crystal conductor substrate 52 includes two regions, 53 and 57. Generally, the electrical semiconductors are indicated by dashed lines, and the components are formed at least partially in the region 53. The electrical components may be resistors, capacitors, active semiconductor components such as Diodes or transistors or integrated circuits such as CMOS integrated circuits. For example, the electrical semiconductor component 56 may be constructed to form a CMOS integrated circuit to perform digital signal processing or other functions that are fully applicable to a body circuit. The electrical semiconductor components in area 53 can be widely used in the semiconductor health industry by commonly known semiconductors plus H. Insulating materials such as silicon dioxide layers can cover electrical semi-specialized components 56. K-sheet scales are applicable China x 297 mm) • 32 · 1577 A7 —--- — B7_ V. Description of the invention (30) " --- Insulation 2 materials 59 formed or deposited during the processing of semiconductor components 56 in area 53 and Any other layer goes from the surface of area 57 In addition, the exposed silicon surface is obtained in the area. As is known, the exposed silicon surface is highly reactive and can quickly form a natural stone oxide layer on the exposed surface. The layer of lock or lock and oxygen is deposited in the area 57 On the surface of the natural oxide layer, it reacts with the oxidized surface to form a first template layer (not shown). According to a specific example, silicon is epitaxially formed by the molecular beam process orientation to form a cover template layer. Single crystal oxide layer. Reactants containing barium, titanium, and oxygen are deposited on the template layer to form a single crystal oxide layer. At the beginning of the deposition process, the partial pressure of oxygen is at a minimum value close to the required time, which is related to barium It reacts fully with titanium to form a single crystal cascade layer. It then increases the partial pressure of oxygen to obtain overpressured oxygen, allowing oxygen to diffuse through the grown single crystal oxide layer. The oxygen diffused through the barium titanate reacts with the surface of the region 57 to form an amorphous layer of silicon oxide 62 on the second region 57 and the interface between the silicon substrate 52 and the single crystal oxide layer 仏. Layers 65 and 62 can be annealed as shown in Figure 3 above to form a single amorphous adjustment layer. According to a specific example, the step of depositing the single-crystal oxide layer 65 may be terminated by depositing a second template layer 64 (which may be a single layer of ", barium, barium, and oxygen, or oxygen and oxygen). Then, a single-crystal compound semiconductor material layer 66 is deposited on the template 64 by a layer of Kun deposition to cover the second template layer. After this initial step, gallium and arsenic are deposited to form single crystal gallium arsenide 66. In the above examples, barium may be replaced by lithium. According to another specific example, a semiconductor device (generally indicated by a dotted line 68) is formed in the compound semiconductor layer 66. The semiconductor component 68 can be formed by processing steps generally used to manufacture gallium arsenide or other III-V compound semiconductor devices. It is applicable to China Standards (CNS) A4 specifications (21GX 297 $ ----- A7 B7 5 Description of the invention (31. Semiconductor component 68 can be any active or passive component, and preferably semiconductor laser, light emitting diode, light detector, hybrid junction bipolar transistor (HBT), high frequency MESFE Ding Or other components which are beneficial to the physical properties of the compound semiconductor material. The metal conductor shown by the line 70 icon can be opened > into an electrical coupling device 68 and a device 56, so it can be manufactured to include at least one substrate 52 The body device formed above and the device formed on the single crystal compound semiconductor material layer%. Although the structure 50 has been described as having been formed on the silicon substrate 52, and has a barium titanate (or hafnium) layer 65 and The structure of the gallium arsenide layer 66 is described. Nitrogen can also use other substrates, single crystal oxide layers, and other compound semiconductor layers to make similar structures, as shown in the disclosure. Figure 25 illustrates the semiconducting of another specific example. Body structure 71. Structure 71 includes a single crystal semiconductor substrate 73, such as a single crystal silicon wafer including regions 75 and 76. The electrical components illustrated by dashed lines 79 are processed using general system devices commonly used in the semiconductor industry Technology formation. The processing steps used are similar to those described above, forming the single crystal oxide layer 80 and the intermediate amorphous silicon oxide layer 83 to cover the region "region 76. The template layer 84 and subsequent single crystal semiconductor layers" are formed to cover the single The crystalline oxide layer 80. According to another specific example, an additional single crystal oxide layer 88 and a cover layer are formed by similar steps to those used to form the layer 80, and by similar processing steps as the formation layer 87 An additional single crystal semiconductor layer 90 is formed to cover the single crystal oxide layer 88. According to a specific example, at least-layers of the layer% and 90 are formed of a compound semiconductor material. The annealing process forms a single amorphous adjustment layer. The semiconductor component represented by the dashed line 92 forms at least a part of the single: semiconductor layer ^ According to its specific example, the semiconductor component 92 may include a portion having a portion of the private ruler. Applicable to China National Standard (CNS) A4 specification (210X297 mm) -34- 1577 A7

1577 A7 B7

1577 V. Description of the invention (34) The surface of Shi Xi on the road, for example, in the manner described above. As illustrated in FIG. 27, a buffered sound chirp is formed on the substrate 110. The tuned buffer layer will be adjusted with a single crystal layer on the surface of the exposed barium in the appropriate barium (that is, with an appropriate template layer) in part 1022 ^: and in part 1024 and deleted The portion of the layer 124 formed; = because it is formed on a non-single-crystal material, and therefore non-forming: Early sweet growth. The adjusted buffer layer 124 is usually a single crystal metal oxide layer 'and the thickness is generally between about 2] nanometers. According to a special strict buffer layer, about 5-15 nanometers thick. In the formation of the adjustment buffer layer, an amorphous intermediate sound is formed along the uppermost silicon surface of the integrated circuit 103. The shaped intermediate layer m generally contains an oxide of silicon 'and has a thickness of about "5 ..." 1. After the intermediate layer 122 is formed, a template layer is then formed, between about-to ten single-layer materials. According to a special specific example, This material = Chin-Shen, Lu-O-arsenic, or other similar materials described in the aforementioned Figure W. = Orientationally formed long single crystal compound semiconductor layer 132, as shown in FIG. 28, covered with a single layer of the adjustment buffer layer 124 Crystal portion. The portion of the layer 132 that is not single crystal grown on the portion of layer 124 may be polycrystalline or amorphous. The compound half-layer can be formed in many ways and usually includes, for example, Shishenhualu, Shaluozhonghua 2. Indium phosphonate, or other compound semiconductor materials as described above. The thickness is between about 1-5000 nanometers, and more preferably 10000 nanometers. It can be further in the layer 132. An additional single crystal layer is formed on it, as described in detail. Τ According to this particular specific example, each element in the template layer is also present in the adjustment buffer a scale A4 specifications (2; • 37 X 297 mm) 1577 A7 B7 V. Description of the invention (35) ^ layer 124, single crystal compound semiconductor layer 132, or both Therefore, the template layer 125 and its two adjacent layers will appear during processing. Therefore, when the = transmission electron microscope (TEM) picture is taken, the adjustment buffer layer 124 and the single crystal compound semiconductor layer 13 2 will be seen. Area When at least part of the layer 132 is formed in 1022, the layers 122 and 124 may be subjected to an annealing process as described in FIG. 3 to form a single-layer-free adjustment layer. Before the annealing process, only one part of the layer 132 is formed, and the rest will be Deposited on the structure 103 before another process. At this time, the part of the compound semiconductor layer 132 and the adjustment buffer layer 124 (or the amorphous adjustment buffer layer, if the above annealing process has been performed) is self-covered bipolar trowel 1024. The part of the MOS part 1026 is removed as shown in FIG. 29. After removing the part of the compound semiconductor layer and the adjusted buffer layer 124, an insulating layer 142 is formed on the protective layer 1/22. The insulating layer 142 Many materials can be included, such as oxides, nitrides, oxynitrides, low-electricity materials, etc. As used herein, low-k is a material with a dielectric constant not higher than about 3.5. After the insulating layer 142 is deposited, Polished or etched, shifted An insulating layer 142 partially covering the single crystal compound semiconductor layer 132. One transistor 144 is formed in the single crystal compound semiconductor portion 1022. A gate electrode 148 is then formed over the single crystal compound semiconductor layer 132. Then, a single A doped region 146 is formed in the crystalline compound semiconductor layer 132. According to this specific example, the transistor 144 is a metal-semiconductor field effect transistor (MESFET). If the MESFET is an n-type MESFET, the doped region 146 and at least a part of The single crystal compound semiconductor layer 132 is also a type dopant. If it is formed, the doped region 146 and at least part of the single crystal compound semiconductor layer 132 have exactly -38-1577 A7.

541577 V. Description of the invention (37) 'But none of it is illustrated in the figure. Furthermore, additional insulation layers and connections may be formed as needed to form appropriate connections between the components in the integrated circuit 103. It can be seen from the previous specific examples that active devices of both compound semiconductors and group IV semiconductor materials can be integrated into a single-integrated circuit. Because it may be difficult to add both the bipolar transistor and the Mos transistor to the same integrated circuit, it is possible to move some of the components in the bipolar portion 1024 to the compound semiconductor portion 1022 or the MOS component 1026. Therefore, it is possible to omit special manufacturing steps required mainly for manufacturing a bipolar transistor. Therefore, for the integrated circuit, only the compound semiconductor portion and the MOS portion may be required. According to another specific example, an integrated circuit may be formed in a semiconductor region of the same integrated circuit as a semiconductor circuit so as to include an optical laser in an aurora connection (waveguide) of a compound semiconductor portion. Figure 31-37 contains a description of one specific example. FIG. 31 includes an illustration of a cross-sectional view of a part of the integrated circuit 16O of a single crystal wafer 161. An amorphous intermediate layer 162 and an adjusted buffer layer 164 (the same as described above) are formed on the wafer 161. According to this particular example, the laser required to form the optical laser is formed first, and then the laser required to form the transistor. For example, the first, second, and fifth films in the Lightning Ray: may include materials such as deified marrying, and the second, fourth, and sixth films in the lower mirror layer 166 may include clock compounds and the like. Laser 168 contains an active area for generating photons. The upper mirror layer 170 is formed in a similar manner as the Shi Xi layer mirror layer 166, and contains different compound semiconductor films. According to its specific example, 'the upper mirror layer 170 may be a type-doped compound semiconductor material' and the lower mirror layer 166 may be an? -Type hetero compound semiconductor material. In addition, the adjustment buffer layer 172 is similar to the adjustment buffer layer 64, and is formed on the upper mirror layer -40- the paper standard itnet g household materials (CNS) V. Description of the invention (38) 170. According to another specific example, the adjusted buffer layers 164 and 72 may include different materials. However, their functions are basically the same, and each of them is used to cause transmission between the compound semiconductor layer and the single semiconductor group. The laser 172 can be annealed as shown in FIG. 3 to form an amorphous adjustment layer. The single crystal ιν semiconductor-free layer m is formed on the adjustment buffer layer 172. According to two aspects, the single crystal w-group semiconductor layer 174 includes tungsten, germanium, and silicon carbide, and the like: The MOS portion in FIG. 32 is processed to form an electrical component in the upper single-crystal semiconductor semiconductor w. As shown in Fig. 32, "Self-partial layer" 171. The interlayer dielectric layer 173 is formed on the layer-upper path, and the first interlayer layer 2 is formed; 5 = closed = the electrical layer M. The doped region m is used for the power supply crystal. In other words, the electrode, emitter, or source / emitter regions are as shown in the figure. The vertical planes of the side wall separator M-series "gate electrode 175 are adjacent. At least part of the layer 174 is made into other components. These other components include other transistor channels), capacitors, transistors, diodes, and so on. ^ The single crystal group 1v semiconductor layer is longer than the doping driver 177 for orientation. The upper part is P + doped 'and the lower part 182 maintains a substantial native state (not changed, as illustrated in Figure 32. This layer can be formed using selective orientation epitaxy. According to its specific example, the insulating layer (not shown) is It is formed on the transistor-isolated region 171. The pattern of the insulating layer has been defined to expose the exposed region π of the doped region 177. At least at the beginning, it is an oriented epitaxial layer that is formed without dopants. All The selective orientation epitaxial layer can be the original or the layer forms a knot when it is close to the selective orientation. When added, 'if the selective orientation epitaxial layer is the original, the doping step is performed by implantation or by doping. Miscellaneous formation. Regardless of how p + upper part 814 is formed, the heart 541577 A7 __B7 V. Description of the invention (39) The insulation layer is removed to form the final structure shown in Figure 3.2. The next set of steps is performed to define the light laser As shown in Figure 33. The field effect isolation region 171 and the adjusted buffer layer 172 are removed from the compound semiconductor portion of the integrated circuit. ^ Additional steps are performed to define the mirror layer n0 and the active layer on the light laser 80. 168. Side surface essence of the upper mirror layer 170 and the active layer 168 The upper part is continuous. The knife forms contact points I% and 188 which are in electrical contact with the upper mirror layer 170 and the lower mirror layer 166, as shown in Figure 33. The contact 186 is ring-shaped, so that light (photons) can leave the upper mirror layer 170 reaches the subsequently formed optical waveguide. Next, an insulating layer 190 is formed and a pattern is formed to define a light opening extending to one of the contact layer 186 and the doping driver 177, as shown in Fig. 34. The insulating material may be any number Different materials, including oxides, nitrides, oxynitrides, low-k dielectrics, or any combination thereof. After defining the opening 192, a higher refractive index material 202 is then formed in the opening to fill and deposit the layer on Above the insulating layer 190, as shown in Figure 35. For the higher refractive index material 202, the higher refractive index is higher than the insulating layer 190 material (that is, the material 202 has a higher refractive index than the insulating layer 190). Coefficient). Depending on the situation, a relatively thin, low-refractive-index film can be formed before the higher-refractive-index layer 202 is formed (the hard-shielding layer 204 and the high-refractive-index layer 202 are not shown) are removed from the portion covering the opening and reached Close to the area on the side of Figure 3 5 The others that form the optical waveguide (which is an optical connection) are illustrated in Figure 36. A deposition process (possibly a dep-etching process) is performed to effectively generate the backside segment 212. In this specific example, the backside segment 212 is Made of the same material as material 202. The hard masking layer 204 is then removed, and the high refractive index materials 212 and 202 and

541577 A7 B7

V. Description of the invention (The low refractive index layer 2i4 (lower than the material 202 and layer 212) is formed on the exposed portion of the 4Q edge layer 19o. The dashed line in FIG. 36 illustrates the high refractive index material between 202 and 212. Edge. The name is to distinguish between two materials made of the same material but formed at different times. Continuous processing to form a substantially complete integrated circuit, as shown in Figure 37. Then, a passive layer 22 is formed on the light laser 180 and the MOSFET transistor 181. 〇. Although “but the components in the circuit can ride other electrical or optical connections” is not shown in FIG. 37. These connections may include other optical waveguides or may include metal connections. According to other specific For example, other types of lasers can be formed. For example, another type of laser can replace vertical light (photons) horizontally. If it emits light horizontally, a M0SFET transistor can be formed in the substrate 16i, and it will form light. The waveguide thus properly couples the laser to the transistor (optical connection). According to a special and systematic method, the "slow guide" can include at least part of the adjustment buffer layer. Other structures are possible. Obviously, these have Specific examples of the integrated circuit of the compound semiconductor portion and the group IV semiconductor portion are for illustration only, and do not exclude or limit all possibilities. There are multiple other possible combinations and specific examples. For example, the compound semiconductor portion may contain a light emitting diode Devices, photodetectors, diodes, etc., and family semiconductors can include digital logic memory arrays and most of the structures that can be formed with general MOS integrated circuits. By using the illustrations and descriptions in this article, ' Nowadays, it is easier to integrate devices that work better in compound semiconductor materials with other components that work better in family semiconductor materials. This makes the device smaller, reduces manufacturing costs, and increases yield and reliability. Financial standards (CNS) Μ specifications (⑽χ 297 public love) 43.541577 A7

541577 A7 B7 V. Description of the invention (42 For the notification processing circuit with the external electronic circuit box, the composite integrated circuit is an electrical signal connected to the device and the external electronic circuit. The composite integrated circuit may have an internal communication connection to enable the composite integrated circuit The processing circuit is connected to the external circuit. The optical components in the composite integrated circuit can provide optical communication connection, which can electrically isolate the electrical signal in the communication connection from the processing circuit. At the same time, the electrode optical communication connection can be used for communication information such as Data, control, timing, etc. The light component pairs (light source components and light detector components) in the composite integrated circuit can be constructed to pass data. The data received or transmitted between the optical pairs can be external circuits and composite products. Electrical communication between body circuits. Optical components and electrical communication connections can form communication connections between processing circuits and external circuits, while providing electrical isolation for processing circuits. If necessary, the complex integrated circuit can include many optical component pairs to provide Many communication connections and provide isolation. For example, a complex integrated circuit that receives many data fragments can include a pair Optical components used for communication of various data fragments. 'Operation can be constructed, for example, a pair of components' during operation to generate light (such as photons) based on receiving electrical signals from electrical signals connected to the external circuit of the disk. Optical detection in the component pair The measuring unit can be optically connected to the light source unit to generate an electrical signal based on the light generated by the light source unit. The information transmitted between the light source detector units can be digital or analog. If necessary, use the opposite This structure. The light source component corresponding to the processing circuit on the board can be lightly connected with the optical debt detector component, so that the light source component generates an electrical signal for communication with external circuits. Many pairs of this optical component can be used to provide a two-way phase ^. For synchronization needs Some applications' can consume the first pair of optical components to provide data communication for seven, and the second pair can provide synchronous information for communication. X 297 mm) This paper standard is applicable @ g 家; ^ (CNS) M specifications "-45 541577 A7 A_ B7 V. Description of the invention (43) For the sake of brevity, the light debt detector components discussed below are mainly discussed in the article of light price detector components, which have been discussed in the review. It is formed in the compound semiconductor portion of the integrated circuit. In use, the photodetector component can be formed in many suitable ways (for example, from silicon, etc.). The integrated integrated circuit generally has electrical connections for power and ground. Power and Grounding is in addition to the above-mentioned communication connections. Processing circuits in composite integrated circuits may include electrically separated communication connections, and include electrical connections for power and grounding. For most known applications, power and grounding are usually electrical circuits Full protection to prevent harmful external signals from reaching the composite integrated circuit. The communication ground can be isolated from the ground signal in the communication connection using the ground communication signal. Example 7 Used on materials and as shown in Figure 38-47 in more detail below The etch agreement described is not limited to the processing of the composite semiconductor structure starting materials as listed in FIG. 1, but can also be used in its different composite structures described in this article, for example, refer to FIGS. 2, 3, 12, 20 , 23, 24, 25, 29, 30, and 37. Moreover, only the special materials described in the discussion of Figs. 38-47 will be described. Semiconductor substrates often have significant thickness variations, and even on uniform etching, silicon substrates can have undesired disadvantages of holes or trenches due to insufficient etching, excessive etching, or a combination of the two. Both overlap technology and chemical mechanical polishing (CMP) planarization techniques can be used to reduce surface unevenness. However, the thickness of the semiconductor substrate must be maintained to provide a robust wafer that can withstand processing and use. The present invention provides an etching stop layer used in combination with a semiconductor wafer substrate (such as a silicon wafer) in a composite semiconductor structure, so that it can reach -46--This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297) Love) 541577 A7 B7 V. Description of the invention (44) An anisotropic engraving that completely passes through the opening of the hole in the thickness of the substrate of Shi Xi, and will not cause damage to the back side, especially the thin high-quality single crystal layer. Excessive moment. As mentioned above, and referring to FIG. 38, the present invention uses the buffer layer 24 already existing in the integrated composite structure 20, which not only can slow down and eliminate the problem of lattice mismatch, but also can be used as a subsequent manufacturing active device and / Or it can be used as an additional role of etching termination during the connection between the main sides of the opposite side of the integrated structure 20, as shown in Figures 39-47. The present invention provides the etching stop function without adversely affecting the crystal quality and the release of non-conforming stresses in the crystallites achieved in the composite semiconductor structure. The method of forming the semiconductor structure 20 (including the layers 22, 28, 24, 30, and 26) has been described herein and is used herein as a reference. The single crystal silicon substrate 22 includes a front surface 221 and a back surface 223. The perovskite oxide film has a side surface 241 facing the silicon substrate 22, and a reverse surface 243 facing the compound semiconductor layer%. The single crystal compound conductor layer 26 has a side surface 263 facing the catalyzed oxide film and a back surface 261. To illustrate FIG. 38.47, the single crystal compound semiconductor layer 26 may be a group two or five semiconductor material, such as the foregoing. Metal oxide thin film materials, such as SrTi03 (STO), have previously been used as borrowing materials for various electronic devices, such as capacitors; however, the present invention introduces the use of stO and other perovskite metal oxides as composite semiconductor materials. The anisotropy terminates with the remainder. A) Reproduction reaches the end of the engraving. The wet cook used in Bu Xizi 丨 As shown in Fig. 39, the sun and the moon are selectively etched on the monocrystalline Yuki i22 oriented by _). The single-crystal silicon substrate 22 can be patterned by a method generally known in the art using a cover for wet etching. For example, the surface can be oxidized, followed by lithography money 541577

Carved, patterned, leaving a dioxy-cut or nitrided capping area on the Shixi substrate 221. The area of the hole or groove of the thickness of the substrate 22 is defined as a storm road and an uncovered area. . Preferably, the masking layer 29 is a layer comprising silicon dioxide, which is an oxide that is thermally grown on the exposed surface of the silicon substrate or is deposited using low pressure vapor deposition (LpcvD). A photoresist (not shown) is then used to expose a portion of the dioxy-shielding layer on the upper side of the monocrystalline substrate. Apply additional photoresist (not shown) or other suitable removable cover on the opposite side of the composite semiconductor structure 20 to etch and process the silicon substrate surface completely and uniformly during the process. % High quality single crystal semiconductor layer on the opposite side (front) of the composite structure. Then use a wet etching solution (such as buffered hydrofluoric acid or R] [E to etch (for example, using CF4 / H2)) to remove the part of the silicon dioxide masking layer covering the silicon substrate, and expose the surface area below the substrate surface. come out. The wafer can also be placed in a fixture that protects the front surface of the wafer from the wet etching solution. As shown in FIG. 39, the anisotropic crystalline wet etching is performed on the exposed and uncovered surface area of the silicon substrate 22 using the cover layer 29 as a cover, and is performed from the silicon substrate at a rate according to the direction of the crystalline state. Remove the entire material. That is, the process of wet etching is related to orientation. It is necessary to understand that the (100) orientation of the wet-type engraving agent, which is mainly composed of gas oxides, and the directional orientation of the eve of the eve of the eve will produce accurate V-shaped grooves 2 11 and 23 1 with side edges formed on the (100) surface. 54.7 degree angle (111) plane, and not straight or vertical wall hole when obtained with (110) silicon. Therefore, care must be taken to ensure that each etched window created by the patterned mask 29 for wet and wet etching (100) silicon is sufficiently large so that the V-groove can reach before the V-groove is complete and includes etching. Qian Ke terminates -48- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 541577

Layer 24. As illustrated in Figure 39, this will result in a hole opening (a V-shaped groove with a flat bottom at the tip). It should be understood that one or any type of hole opening may be formed in the silicon substrate 22 depending on its application. For the anisotropic crystalline etching process and other (11) silicon substrates, the following descriptions preferably include alkaline solutions that can generate hydroxide ions, such as tetramethylammonium hydroxide (TMAH) Wait. However, it is also possible to use crystalline planes that can be used to selectively etch single crystal silicon, including cesium hydroxide, ethylenediamine pyrocatechol (EDP), ethylenediamine / pyrocatechol / water (Epw), ethylenediamine / Solutions of pyrocatechol / quinazoline / water (modified EPW), potassium hydroxide, lithium hydroxide, sodium hydroxide, or other chemicals that generate hydroxide ions. The single crystal silicon substrate 22 may also have a plane cut along the (1 丨 υ or (110)) crystalline plane, which is used to arrange the single crystal silicon substrate 22 and the equipment for semiconductor processing. Wet etching will be performed until no Until the oxide layer 28 is shaped, the etching is stopped at the interface of the silicon substrate 22 and the buffer / etch stop layer 24. The selective wetting used on the silicon substrate 22 is etched], as described below, and it is not possible to engrav the money. Buffer / etch stop layer 24. The silicon oxide transition region 28 is not significantly affected by the selective etchant used on the silicon substrate 22. The 2 shaped silicon oxide layer 28 existing at the bottom of the holes 211, 231 is located in the substrate 22. After etching, it can be removed from the etchant by a short storm road, for example, by wet etching with buffer (etching rate of 1000 angstroms / minute), or dry etching with CK / H2 ruler (45 °). Angstrom / minute etch rate). The hydroxide-based wet etching technique described herein will not significantly attack the buffer / etch stop layer 24, at least for a short time. However, it is not desirable to buffer / Etch stop layer to extend the wetting used on silicon In the etchant, it may cause some of the same anisotropy -49- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 541577 A7 ______B7 V. Description of the invention (47) Etching. Although calcium The crystal orientation of the titanite oxide film 24 is the same as that of the silicon substrate 22 of the preferred embodiment of the present invention, but the wet etchant used on the substrate 22 not only selectively etches the crystalline state, but also etches specific materials. Figure 40 In another specific example illustrated in the figure, the starting material of the semiconductor structure is the structure 34 of FIG. 3 as described in this document, instead of the structure 20 of FIG. 22 terminates at the side 245 of the amorphous oxide layer 36. In FIG. 40 and FIG. 45, the layer 38 illustrated in the strength includes the above-mentioned template formed of the components of the at least one single-layered single crystal compound semiconductor layer 26, and The single-layer masking layer 30 functions to form a layer 26 oriented to form a long template. Other materials for the layer 38 can also be used. Referring to another method illustrated in FIG. 41, the main exposure of the single-crystal silicon substrate 22 is as follows. The surface is specific to that description It is used in the (11) crystal plane as an example. In order to form holes or grooves 213 and 233 in the silicon substrate 22, a selective wetting coin is used to remove only the single crystal substrate 22 in the (110) plane. The exposed part. As for the 4 selective wetting process, the wetting process will expose any plane with (111) orientation, which can be used to define the opening of the hole. The width of the trench structures 213 and 233 is two parallel (111 ) Surface definition. Because silicon etching is anisotropic, the bottom of the trench structure is in the (11) crystal plane 'and is substantially parallel to the upper surface 221 of the single crystal substrate 22. Used on a silicon substrate The advantages of selective wet etching to form holes or trenches are shown in Figures 39-41. The rate of wet etching is relatively faster than most anisotropic RIE etching techniques used to etch single crystal silicon. In addition, selective wetting etching can form small openings because significant residues are not left on the sidewall or bottom of the hole during the etching operation. For example, the standard of the time scale (CNS) M specifications (training 297 public love)-541577 A7 ____B7_ V. Description of the invention (48) Selective wet etching can form sub-micron openings on the silicon substrate, and Compared with single wafer RIE processing, selective wet etching can be processed in batches to increase output. B) i End-Detection Dry Etching Path for Terminating Etching Referring to FIG. 42 below, dry etching such as plasma-assisted etching can also be used to form holes or trenches 2 1 5 and 235 in a single crystalline silicon substrate 22. For example, RIE etching can pass through the silicon substrate 22 more slowly than selective wet etching, but it can provide the advantage of detecting the end point of the etching in time when the re-etching reaches the buffer / etch stop layer 24, and can form high aspect ratio holes. As for the specific example of the wet etching shown in FIG. 41, dry etching can also be used to form holes having substantially vertical sidewalls formed in the silicon substrate 22. For example, the reactive ion etching (RIE) process can be used to dry the holes 21 5 and 235 in the etching-based substrate (22). The RIE process can provide an anisotropic engraving of the Shi Xi substrate 22 with appropriate etching selectivity, such as used to define the opening on the surface 221 of the Shi Xi substrate 22 between the Shi Xi and the cover layer 29. It is generally known to include RIE using, for example, SF0 / C12. Appropriate masking layers for silicon RIE processes are also known, including silicon dioxide and silicon dioxide in combination with other dielectric layers, and the like. Suitable techniques for patterning such masks are also known. The thickness of the cover is sufficient to withstand any type of sputtering (physical impact) corrosion consistent with the chemical removal mechanism used in the RIE process. The endpoint test means that it can be used in conjunction with this RIE process, because many standard dry etchant used for anisotropic etching of Shi Xi will also attack the perovskite metal oxide buffer / etch stop layer material which is better for the present invention. For example, standard reactions for silicon containing halogenated gases (such as chlorinated, fluorinated, or brominated gases) 1-51-This paper is commonly used in the SS Home Standard (CNS) A4 specification (2 Mongolian 297 mm) ---------- 541577 A7 ____B7 V. Description of the invention (49) The sub-etch plasma is not sufficiently selective for the perovskite metal oxide materials in the silicon substrate 22 and layer 24. As previously mentioned, the thickness of the perovskite film 24 (or the amorphous oxide layer 36) may be as small as 2 to about 100 nanometers. In order to determine that the RIE used to form the holes 215 and 235 passing through the Shixi substrate 22 does not advance through the buffer film 24, and before the termination of the etching process, the high-quality single crystal compound semiconductor film 26 is attacked in an uncontrolled manner. On the back side, the end point detection is used to quickly terminate the RIEs that make holes 215 and 235 when they reach layer 24 again. In this way, the layer 24 can provide a buffer zone, so that the hole etching process through the silicon substrate 22 can be safely reached and terminated before any uncontrolled etching attack of the single crystal film occurs. In order to stop the etching of the holes 215 and 235 when the thickness of the silicon substrate 22 and the exposed layer 24 is removed, the end point of silicon is detected in situ and in real time by appropriate spectrum analysis technology. Appropriate endpoint detection between the semiconductor substrate 22 and the etch stop layer 24 can be performed using light endpoint detection systems (including optical interference techniques) that are generally known and used for semiconductor manufacturing techniques. End point detection using laser reflected light technology can also be used, which uses methods and equipment known in the art for that purpose. Alternatively, mass spectrometry analysis of the etching plasma can be used to detect when the material in the metal oxide etching stop layer 24 is released into the plasma from the surface of the etching stop layer 24. The interface of the substrate 22 and the etch stop layer 24 assumes that the re-plasma spectrum analysis shows that the materials and reaction products containing the etch stop layer 24 have already arrived, such as strontium at the time of the ST0 layer 24. At this point, the rie process is terminated. One basic strategy that can be used for endpoint detection involves exposing the semiconductor substrate 22 to a plasma discharge suitable for use in an exposed surface area anisotropically etched into the semiconductor substrate, and optionally detecting it by passing a portion of the electromagnetic radiation. Detect half-52- This paper size applies to China National Standard (CNS) A4 specifications-541577

The end of the hole formation step at the interface of the conductor substrate 22 and the etch stop layer 24 is equivalent to the release of the radiation detector from the semiconductor substrate 22 or the etch stop layer M by plasma discharge. The frequency of preselected excitation species combination = ° The radiation detector generates an input related to the intensity of some light shots. II: When the detected output signal reaches a predetermined threshold, the rie process is terminated.

For example, the continuous detection of part of the electromagnetic radiation in the RIE process by radiation detection is equivalent to the frequency of radiation generated by preselected excitation related to the material released from the etch stop layer by plasma discharge, as contained in it Metal, and by detecting that the output signal that exceeds the threshold value rises, it can reach the predetermined threshold value (★ when the mouth reaches the substrate / etch stop layer interface at any time). At this point, the rie process is terminated. In addition, the portion corresponding to the detected electromagnetic radiation corresponding to the radiation frequency and the predetermined threshold value generated by the preselected excited species including the material released from the semiconductor substrate by plasma discharge (e.g., Shi Xi) is borrowed. It is reached by detecting the output signal falling below the threshold (for example, when the interface of the substrate / etch stop layer is reached at a time). At this point, the RIE process is terminated. Order

Because the oxide film 28 in FIG. 42 is extremely thin (5 to 50 angstroms), it is etched away by the RIE etchant used on the silicon substrate 22 in most cases, or it can be etched by the separated CH4 RIE. After the etching is completed, the bottom of the hole 215 or 235 is removed through the thickness of the substrate 22. -Ion milling (such as argon) is not a good method for dry etching silicon substrate 22 because it will increase debris, increase the risk of contamination, increase crystal damage, and non-selectivity between the substrate and the etch stop layer. Wait. c) The technology of hybrid etching with discontinued engraving. The selective wet etching process as described above with reference to Figures 39-41 can also be used for other -53-

541577

Partially but not entirely through the thickness of the monocrystalline silicon substrate 22 is etched, followed by a dry last engraving process (as described in FIG. 42) with an end-point debt measurement, which can be used to make holes until the buffer / etch stop layer 24 is reached. This method can provide relatively rapid etching through the entire substrate 22 via wet etching, and has the accuracy of instant endpoint detection possible with dry etching. It is also possible to collect debris along the sidewalls and bottom of the hole due to the sputtering effect of the RIE process. D) File of buffer / etch stop layer "1" With reference to Figure 43 below, when it is necessary to advance the hole formed by any part of the processing material shown in Figure 39, 42 or 43 through the buffer etch stop layer 24 until it reaches the single Up to the back surface 263 of the crystalline material layer 26, the following procedure can be used. For example, when the back is to be connected to the single crystal material layer 26, the last name is required. These connections need to be made directly, as are the metal oxide materials for the etch stop layer 24 described herein, and are generally dielectrics and electrical insulators, with the exception of ruthenate gills. ". The step can be performed using dry and wet after-etching techniques. For example, the perovskite oxide material in the material of the money-cut stop layer 24 can be wet-etched with anisotropic etching with light enhancement. Therefore, the metal oxide film can be formed with The exposed metal oxide film portion is contacted with a liquid solution of hydrochloric acid and / or hydrofluoric acid, and then an acidic solution (for example, 12M hydrochloric acid) is exposed to electromagnetic radiation generated by a radiation source (for example, a 200 watt mercury xenon arc lamp). (Such as direct visible light / ultraviolet radiation), which can initiate anisotropic, liquid-phase photochemical etching of perovskite metal oxide films. Unless this procedure is performed by photolysis, hydrochloric acid will anisotropically attack metal oxides , Increasing the risk of sidewall corrosion. Sidewall corrosion is not desirable because when it advances through the perovskite oxide layer, it will eventually be chemically modified. • 54-541577

. When the back surface of the semiconductor layer is exposed, the aspect ratio of the holes is reduced. Because the thickness of the perovskite oxide layer 24 is known to the material, and the etching rate of the wet etching system can be pre-charged for the material, it can be predicted by the function of time f to reach the back of the single crystal material layer 263 Time, and this% can stop the etching of the buffer / etch stop layer 24 at an appropriate time. As for the dry etching technique used for the etch stop layer 24, the selectivity of the etchant to the titanite oxide material should be higher than that of the cover (not shown) formed on the silicon substrate 221. The etching of the layer 24 can be performed using a rie process, using one or more halogen or chemical gas (such as fluorine, a, Cf4), at a high temperature (generally greater than 400 ° C, and preferably 500-800t) ;), Combined with a hard cover (not shown) on the silicon surface. For example, the hard covering may be formed of oxides of transition metals BN 023, A1N, and the like. After the last name has passed through the layer 24, it can be removed by any standard etching process used for this purpose. For example, an organic release layer can be provided on a hard cover at the surface of the silicon substrate to facilitate subsequent removal of the cover. Shell gas (such as argon) can be included in the plasma engraving to give a grinding effect to increase the removal rate on perovskite oxides, but ion milling is not selective for perovskite oxides and covers The thickness must be sufficient to withstand sputtering. Moreover, the etch plasma may contain oxidation or oxygen compounds to help avoid the reduction of metal oxides in layer 24 during the RIE process. When the back surface 263 of the single crystal material layer 26 is reached during the rie process used for the etching layer 24, it can also be detected using the spectral endpoint detection technology (as described above), and the etching of each stop layer 24 is terminated at this time. For illustration, FIG. 43 shows that this process step is performed on the layer 24 as if it were performed on a starting material mainly composed of the intermediate structure shown in FIG. 42. It should be understood that the above-mentioned etching procedure described in Figure 39-43 is included in its package -55- This paper size applies to China National Standard (CNS) A4 specifications (210X297 public love)

Binding

541577 A7 B7, including single perovskite oxide materials (as shown in Figure j), can be used to make holes open, over buffer / #etch stop layer 24, "In addition, it includes In the case of a hafnium oxide material, it can also be used to advance holes through the buffer / etch stop layer 36. Because the total thickness of the cover layer 30 and the template layer 38 (structure 34) is a single layer and contains the components of the cover layer 30 and the layer 26, for the sake of illustration, compared to these two layers, When a very thin interface is formed between layers 36 and 26, no special etching process is required. Therefore, no matter whether the etching of the layer 36 is arranged, or the end point detection is used when the layer 26 arrives, the existence of the cover / stencil interface 30/38 is not an obvious factor. E) The back surface connected to the single crystal material layer is described below with reference to FIG. 44. Conductive hole connections 219 and 239 are formed in holes 217 and 23 (see Figure 43). These connections 219 and 239 can be made into active regions or electronic circuits 271 and 273 existing in the single crystal compound semiconductor material layer 26. These conductive hole connections can be formed by generally known methods, i.e., using industrial methods for general purposes. For example, hole linings (such as Ding or TiN) and metals (such as cranes, copper, or aluminum) can be deposited in the holes 217 and 237 to form holes connected to discrete locations on the back surface 263 of the single crystal material layer 26. According to another specific example illustrated in FIG. 45, the conductive hole connection may be formed in the conductor structure of FIG. To achieve this, the etching process used to advance the holes through the alumite layer 24 to the back surface 263 of the layer may be the same technique as described in FIG. 43. Next, the formation of the hole connections 219 and 239 can be performed as described in FIG. Example 8 The illustration of the cross-section diagram of FIG. 46 is according to another specific example of the present invention. Using L-_ _-56- of FIG. 3 8 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 541577

, ', Mouth structure, forming a hot hole connection in the composite semiconductor structure. This specific example can also be performed on other semiconductor structures described herein, including the structure 40 in FIG. 2 or the structure 34 in FIG. 3. The structure includes conductive hole connections 2 19 and 239 as shown in FIG. 44, but the desired conduction here It's heat, not electricity. The hole dynamic connection 219 and 239 transfer the heat conduction in the devices 27 丨 and 263 in the single crystal compound semiconductor layer 26 to the heat absorbers 281 and 283 deposited on the exposed surface 221 on the opposite side of the monolithic substrate 22.

Example 9 Binding

Referring to FIG. 47, the vertical cavity surface type laser structure i8 丨 is based on another specific example of the present invention, using the back surface processing technology as shown in FIGS. 42-43 above, and is installed in the composite semiconductor structure of FIG. 37, and here Suggested for reference. The single crystal silicon wafer 161 is equivalent to the silicon substrate 22. The amorphous intermediate layer 162 and the adjusted buffer layer 164 are compatible with layers 28 and 24, respectively, of Figures 42-44 above. The layers 162 and 164 may be annealed as described in FIG. 3 above to form a single amorphous adjustment layer. According to this specific example, the layers required for light lasers are formed first, and then the layers required for MOS transistors are formed, as shown in Figures 31-37 above, and for reference. The compound semiconductor layers 166 and 170 include another single crystal compound semiconductor material, as shown in Fig. 3 1-37 above. According to a specific example of a vertical cavity laser, a light exit hole 217 is made through a silicon substrate 161. As described in Figures 42-44, the light generated by the light laser 180 is made from the bottom of the semiconductor structure i8l emission. According to another specific example, after the holes 217 are formed and advanced to the back surface 263 of the layer 26 ', a mirror stack for laser is formed from the stone surface 2 21 of the structure. As known, the present invention is fully applicable to obtain highly aligned channels on the back of the single crystal material layer 26. The back channel is used to provide and exist in the single NI-57- This paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) 541577 A7 B7 V. Description of the invention (55) Material layer Some of the microelectronic devices, optoelectronic devices, and / or electronic circuits in 26 are in electrical contact. The thin metal oxide etch stop layer is very important to avoid alignment problems that occur between the holes that begin on semiconductor substrates, such as wafers that process rhenium and the backsides of the active or contact areas in the single crystal material layer. Therefore, for example, the composite, integrated structure of dissimilar semiconductors or other materials can be successfully processed into a single, integrated structure with extremely high-quality thin films for structural use in high-performance microelectronic / optical devices. According to yet another specific example of the present invention, the hole can be formed in a semiconductor with various uses, including (but not limited to) a sign of electrical separation structure and arrangement formed in or contained in a semiconductor substrate of a composite semiconductor structure. And microstructure. Therefore, the active device can be formed in a semiconductor substrate of a composite semiconductor structure and a high-quality single crystal material film. For example, the etching process technology described herein can also be used to form separation trenches for active devices or microstructures (such as microinductors) formed in at least a portion of the silicon substrate 22. In this specific example, the time base material 22 is not excluded as an Ahandle® wafer. For example, the hole may form a separate trench in the silicon substrate 22 during the fabrication of a vertical laser. The invention forms a vertical thunderbolt in a composite semiconductor structure. Composite conductor lasers can be processed in accordance with the present invention, in which the semiconductor structure includes silicon (Si) or compound hard germanium (SiGe) to obtain a relatively low-cost, robust platform that provides mechanical strength to the structure, and is used for the assembly itself as appropriate Active devices (if required, high-quality single crystal semiconductor layers are also used as the main medium when forming activation devices and / or circuits, and include three or five group semiconductors such as GaAs, GaInAs, GaAlAs, InP, CdS, ZnSe, etc. 541577 V. Description of the invention (56) In the foregoing description, the present invention is described with reference to specific specific examples. However, those skilled in the art should understand that various improvements and changes can be made without departing from the scope of the invention listed in the scope of the following patent applications. Therefore, the description The drawings and drawings are only considered to be illustrative, but not limited, and all improvements are included in the scope of the present invention. Benefits, other advantages, and answers to problems are described above with specific examples. However, m, advantages, and answers to problems And any element that may cause any benefit, advantage or answer to a question is not subject to any or all of the essential characteristics or Limitations, requirements. As used herein, the word 'including 1' or any variation thereof encompasses non-excluded inclusions, including processes, methods, objects, or devices that include the listed elements, not just those elements. And the process, method, object or device may contain components not listed. • 59-

Claims (1)

541577 ------- VI. Application for patent scope 8 8 8 8 ABCD 1, A method for manufacturing semiconductor structures, including & substrate for early-crystal hair; Covering monocrystalline catalyzed oxide film on monocrystalline stone The thickness on the evening is lower than the thickness of the material that will cause stress defects;. The amorphous oxide interface layer containing at least silicon and oxygen is formed at the interface between the single crystal dance titanium oxide film and the single crystal substrate; Orienting epitaxially to form a single crystal compound semiconductor film covering a single crystal gangue oxide film, the single crystal compound semiconductor layer having a back side facing the single crystal gangue oxide film; covering the silicon substrate with a pattern to At least one exposed surface positioned on the boundary; forming a channel on the silicon substrate through the exposed surface area, which terminates at the single crystal perovskite oxide film before exposing the single crystal compound semiconductor; and advancing the channel to the single Back side of the crystalline compound semiconductor layer. 2. The method according to item 1 of the patent application scope, further comprising depositing a conductive material in the channel, which is in contact with a single crystal compound semiconductor material. 3. The method according to item 1 of the patent application scope, further comprising forming a heat drop on the exposed main surface of the silicon substrate, and forming a thermal communication between the single crystal compound semiconductor layer and the thermal deposition through the conductive material in the channel. 4. The method of claim 1 in which the orientation epitaxial formation of a single crystal compound semiconductor layer includes depositing a group of third to fifth compound semiconductor materials that are epitaxially oriented. 5. The method according to item 1 of the scope of patent application, wherein the channel formation includes exposing the Shi Xi substrate to the etching selection of the silicon substrate and the single crystal titanium oxide layer -60- Paper size Sin + S S Home Standard (CNS) A4 size (21GX 297 ^ 7 541577 A8 B8 C8 6. Optional at least 1G: 1 anisotropic etching agent. For example, if the Shi Xi substrate in the patent scope of item 1 is exposed, the channel formation in "top = two t" can be included in the last name. The H crystal orientation is concentrated. 7. 8. 9. 10. If applied The scope of the patent is item i, ancient and soil. ^ ^ ^ The channel formation includes silo soil "prepared to provide anisotropic crystalline directional etching thereon: ^ :: etching", and the wet etchant includes Alkaline hydroxide solution. For example, the method of the first patent and the second patent application in the scope of patent application, wherein the formation of the channel includes a reactive ion etching of the sill stone substrate. For example, the method of applying for the scope of patent 1: ¾ $ t, 、, ㈣, i, wherein the channel formation includes: making the substrate exposed to chromium in a plasma discharge to etch the channel through the silicon substrate; light detection When the channel reaches the single-crystal perovskite film, and the optical detection ends, the formation of the channel is terminated. For example, the method of claim 9 in the patent application, wherein the channel formation includes: reactive ion engraving; 5th base material; and by making part of electromagnetic radiation (equivalent to radiation and including plasma discharge to a radiation detector) The frequency of the output signal related to the radiating part is generated from the preselected excitation type of the silicon substrate or the perovskite oxide release material.) The light is used to detect the end point of the channel formation between the silicon substrate and the perovskite oxide film. ; And when the detected output signal reaches a predetermined threshold, the channel formation is terminated. 11. The method according to item 丨 of the scope of patent application, wherein the channel formation includes exposing the silicon substrate to a plasma discharge, etching the silicon substrate, and by using the quality -61-This paper standard is applicable to Chinese national standards (CNS ) A4 size (210 X 297 mm) Binding 541577 ABCD VI. Patent application scope Spectrometer analysis and detection of plasma discharge, detection of the end point of the formation step between the semiconductor substrate and the perovskite oxide film, until the preselected excitation type containing the perovskite oxide film is reduced So far, and the channel formation is terminated during the detection. 12. The method according to the scope of application for patent, wherein the channel advance includes contacting the perovskite oxide film with an anisotropic wet etchant including liquid at least one of hydrochloric acid and hydrofluoric acid, and valley liquid, The acidic solution is then exposed to electromagnetic radiation. 13. The method of claim 1 in which the channel advancement includes exposing each ore oxide film to an anisotropic dry etchant including a plasma generated in a gas source containing a voxel gas. 14_ The method of claim 1, wherein the monocrystalline perovskite oxide comprises a member selected from the group consisting of strontium titanate, lithium barium titanate, barium titanate, lithium zirconate, and barium zirconate , Gallium gallate, barium gallate, and perovskite oxides of barium stannate. 15. The method of claim w, wherein providing a silicon substrate includes selecting a silicon selected from the group consisting of (100) silicon, (110) silicon, and (111) silicon. 16. The method of claim ii, wherein providing a single crystal substrate includes selecting silicon having a thickness of about 12,000 to 25,000 nanometers, and depositing a perovskite oxide film, including forming a thickness of about 2 to about 10%. 〇 Nano-sized titanium ore oxide, and the shape of the single crystal compound cast substrate, including forming a compound semiconductor substrate with a thickness of about 500 to about 10,000 nanometers. 17. —A method for manufacturing a semiconductor structure, including providing a single crystal silicon substrate; depositing a single crystal titanite oxide film, and covering the single crystal substrate, the -62-This paper is suitable for financial countries S Domestic Standard (CNS) A4 Specification (21Gχ Tung Dong Qiao ----- 541577-BCD VI. Patent application scope The thickness of the film is lower than the thickness of the gallium which will cause stress defects; it is formed on the monocrystalline cathodic oxide film And an interface between a single crystal substrate and an amorphous oxide interface layer containing at least silicon and oxygen; oriented epitaxially forming a single crystal semiconductor plutonium covering a single crystal catalyzed oxide film; and oxidizing the single crystal jossite The film is heated to effectively convert the cathodic oxide film into an amorphous titanite film; the pattern covers the Shixi substrate, and at least one exposed surface positioned on the substrate is bounded; 18. formed on a silicon substrate The channel passes through the exposed surface area, which terminates at the single crystal nutrite oxide film before the single crystal compound semiconductor is exposed; and advances the channel to the back side of the single crystal compound semiconductor layer. A semiconductor structure includes: a single crystal Evening substrate; cover sheet An amorphous oxide material of a crystalline silicon substrate; a single crystal titanite oxide material coated with an amorphous oxide material; a single crystal compound semiconductor material covering a single crystal titanite oxide material; and at least one extending through silicon The channel through which the substrate and the perovskite oxide film reach the back of the single crystal compound semiconductor material layer. 19. ^ The semiconductor structure of the 18th scope of the patent application, wherein the channel contains a conductive material in contact with the single crystal compound semiconductor layer. 2 〇 If the semiconductor structure in the 18th scope of the patent application, the channel contains a conductive material in contact with the single crystal compound semiconductor layer, and it also includes the national paper standard (CNS) A4 specification 297 public love y -63-) 41577 A8 541577 8 8 8 8 A BCD, patent application scope includes vertical cavity surface type laser. 27. The light-emitting semiconductor device according to claim 25, wherein the device includes a light-emitting diode. -65- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)