TW540963U - Structure capable of verifying the layer stacking sequence of circuit board - Google Patents

Structure capable of verifying the layer stacking sequence of circuit board

Info

Publication number
TW540963U
TW540963U TW91216095U TW91216095U TW540963U TW 540963 U TW540963 U TW 540963U TW 91216095 U TW91216095 U TW 91216095U TW 91216095 U TW91216095 U TW 91216095U TW 540963 U TW540963 U TW 540963U
Authority
TW
Taiwan
Prior art keywords
verifying
circuit board
structure capable
layer stacking
stacking sequence
Prior art date
Application number
TW91216095U
Other languages
Chinese (zh)
Inventor
Shi-Chi Wu
Shih-Hsin Cheng
Original Assignee
Leadtek Information Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Leadtek Information Co Ltd filed Critical Leadtek Information Co Ltd
Priority to TW91216095U priority Critical patent/TW540963U/en
Publication of TW540963U publication Critical patent/TW540963U/en

Links

TW91216095U 2002-10-09 2002-10-09 Structure capable of verifying the layer stacking sequence of circuit board TW540963U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW91216095U TW540963U (en) 2002-10-09 2002-10-09 Structure capable of verifying the layer stacking sequence of circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW91216095U TW540963U (en) 2002-10-09 2002-10-09 Structure capable of verifying the layer stacking sequence of circuit board

Publications (1)

Publication Number Publication Date
TW540963U true TW540963U (en) 2003-07-01

Family

ID=29581479

Family Applications (1)

Application Number Title Priority Date Filing Date
TW91216095U TW540963U (en) 2002-10-09 2002-10-09 Structure capable of verifying the layer stacking sequence of circuit board

Country Status (1)

Country Link
TW (1) TW540963U (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100490603C (en) * 2005-09-30 2009-05-20 环隆电气股份有限公司 Circuit board with verified laminated layer sequence
US8448571B2 (en) 2010-09-06 2013-05-28 Fukui Precision Component (Shenzhen) Co., Ltd. Method for screen printing printed circuit board substrate
CN112033294A (en) * 2020-08-17 2020-12-04 胜宏科技（惠州）股份有限公司 Method for identifying whether PP (polypropylene) sheets are correctly stacked

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100490603C (en) * 2005-09-30 2009-05-20 环隆电气股份有限公司 Circuit board with verified laminated layer sequence
US8448571B2 (en) 2010-09-06 2013-05-28 Fukui Precision Component (Shenzhen) Co., Ltd. Method for screen printing printed circuit board substrate
CN112033294A (en) * 2020-08-17 2020-12-04 胜宏科技（惠州）股份有限公司 Method for identifying whether PP (polypropylene) sheets are correctly stacked

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Legal Events

Date Code Title Description
GD4K Issue of patent certificate for granted utility model filed before june 30, 2004
MM4K Annulment or lapse of a utility model due to non-payment of fees