TW540155B - Manufacturing method capacitor having tantalum pentoxide dielectric layer - Google Patents

Abstract

A kind of method for manufacturing capacitor having tantalum pentoxide dielectric layer is disclosed in the invention, in which the invention is suitable for use in dynamic random access memory (DRAM). In the invention, tantalum pentoxide (Ta2O5) dielectric layer is deposited on the substrate formed with storage electrodes. The dielectric layer is doped with titanium oxide (TiO2) and is treated by a nitridation process as well as an oxidation annealing process to change its composition as (Ta2O5)l-x(TiO2)x for satisfying the following condition: 0.15 < X < 0.25; and the atomic percentage ratio of Ti/Ta is in the range of 8.8 to 16.7%. After that, a corresponding electrode is formed on the dielectric layer to complete the manufacture of capacitor so as to effectively decrease generation of leakage current and maintain high storage capacity.

Description

540155

V. Description of the invention (1) Field of the invention: The present invention relates to a capacitor having a group of two pentoxide layers in a dynamic random access memory (dram hybrid titanium dioxide to reduce the leakage capacity of a capacitor. Manufacturing method of the device) In particular, related to the manufacturing method of the electric valley device, it is applicable.) 'It is doped with pentoxide and does not reduce the storage capacity of the capacitor. Relevant technical description: Circuit random access, (DRAM) is a widely used Most of the integrated cells are composed of a dynamic H-mechanical access memory cell (a capacitor that is used to remove wells). As known by% =, capacitors are used to store electric charges to provide electrons. It should have a sufficiently large capacitance, and the frequency of 'recharging is more refreshed' in order to avoid the loss of shell material and reduce the size of the stacked capacitors with the increasingly highly integrated dram structure. Space S: meta1 'MIM) or metal-insulator-half structure to form a capacitor. In the complex, the WC (Lnductor, MIS) material can be connected from: (ι) to increase the capacitance of the dagger electrical connection container for the storage electrode, theoretical The electric constant, and (3) decrease the dielectric and increase the dielectric layer in the direction of increasing the thickness of the storage electrode surface. The surface structure of the rugged surface structure, 彳, '', is justified to form creases' The related research results are that the three-dimensional electrode structure is much more complicated. In terms of reducing the thickness of the dielectric layer, the manufacturing steps are much larger than those of the traditional &quot; electric layer.

M0155 V. Description of the invention (2) Γ: Most capacitors f have used extremely thin dielectric layers. However, when the thickness is less than 50 Å, it is easy to produce two ions due to direct carrier tunneling (!) Flow! Affects the characteristics of the component. ® This, another research is dedicated to the dielectric constant of the dielectric material to replace the commonly used silicon oxide layer, to further enhance the capacitor's capacitance, of which the pentoxide: group (Ta2 05) is quite popular One of the most important dielectric layer materials. Unfortunately, this material: itself has the disadvantage of high leakage current, so it is known practice to dope impurities in the second group, such as Shi Xi. This can indeed reduce the leakage current. Doping Shi Xi will also reduce the dielectric constant of the second pentoxide group and reduce the capacitance of the valley device. In addition, Saito et al., U.S. Patent No. 4,734,340, disclose a dielectric thin film = doped titanium dioxide (Ti〇2) in an electrical layer, in which the original-to-blade ratio (at ·%) of the titanium pair: 〇; [to the range of 4. The person below explains the manufacturing method of a capacitor having tantalum pentoxide according to FIGS. 1A to 1B. First, as shown in the figure u, provide: Q0 * For example, a silicon wafer is formed thereon Transistor element to

Insulating protective layer on Li ii70 pieces. In order to simplify the figure here: only: a flat substrate 10 is shown. In addition, a pattern of the first conductive layer 12 is deposited on the substrate 10, for example, a polycrystalline silicon layer, as the storage electrode 12 of the capacitor ^. Then, a chemical vapor deposition method (*. 31 »v: pV =: tion 'CVD) is formed on the first conductive layer 12 and the substrate 10, for example, the second group of pentoxide-doped dielectric layers 14 To change two =. Next, please refer to Section 1_, forming a second conductive layer on the surface of the dielectric layer 14 as a capacitor.

540155 V. Description of the invention (3)-The counter electrode 16 is made of a metal, such as platinum (p t) or tungsten (w). This completes the manufacture of the memory element capacitor. However, the above-mentioned dielectric layer is doped with silicon to reduce leakage current, but at the same time due to the addition of silicon ^. The dielectric constant of the gasified second button is reduced, that is, the capacitance of the capacitor is reduced. In view of this, an object of the present invention is to provide an improved manufacturing method of a capacitor having a second pentoxide layer by doping the dielectric material. First, titanium oxide can reduce the occurrence of leakage current, improve the properties of components, and can support high dielectric constant, so that capacitors maintain high storage capacity. Summary of the invention:

The purpose of the invention is to provide a dielectric layer with a pentoxide button. The manufacturing method is suitable for dynamic random access memory. It can reduce the leakage current in the container and improve the properties of the device. . 1. Another object of the present invention is to provide a method for making an electric valley device with a two-button pentoxide dielectric, which is suitable for dynamic random access memory. At the same time, the dielectric constant of the capacitor is maintained: the high number of dielectrics allows the valley device to maintain a high storage capacity. According to the description, the method of the present invention having a tantalum pentoxide dielectric layer in a dynamic random access memory includes the following spring: a user provides a substrate to form a first conductive layer on the substrate as Capacitance layer becomes =% pole ;.介 A dielectric layer is formed on the first conductive layer, in which the dielectric / V of Ta; ~ 5 1 X (Tl02) χ and satisfying 0.15 &lt; χ &lt; 0.25 and Ti / Ta atoms The percentage ratio forms a second conductive layer on top of the dielectric layer of 8.8 to 16.7 at. , ^ The opposite electrode of the above capacitor in Denso

540155

And complete the capacitors described above. After the dielectric layer is formed in thunder and a at 700 ° C, the steps of applying and rapid heat treatment at 450 ° C and subsequent steps are included. A brief description of the dielectric layer implementation-electrolytic oxidation annealing scheme under conditions: Purpose, characteristics, and advantages can be more clearly understood, and in conjunction with the attached drawings, a detailed description is provided. In a preferred embodiment: The manufacturing method of a green container of a button dielectric layer 1A to 1B is shown;

Figures 2A to 2D are pictures of Mount Zishan 4 and the city center ^, f _, and a method for manufacturing a capacitor with a five-tantalum dielectric layer according to an embodiment of the present invention; A graph showing the relationship between the leakage current and the Ta 02 05-doped Moire percentage according to the embodiment of the present invention. "Figure 4", the relationship between the dielectric constant and the percentage of Ti02 moles of Ta02 05 according to the embodiment of the present invention cannot be drawn. [Symbol] 10, 20 ~ substrate; 12, 22 ~ first Conductive layer; 14,24 ~ dielectric layer;

2 4 a ~ dielectric layer subjected to rapid high temperature heat treatment; 24b ~ dielectric layer subjected to low temperature plasma oxidation annealing treatment; 26 ~ second conductive layer. Detailed description of the preferred embodiment:

0503-6284TW; TSMC2001-0108; Chen.ptd Page 7

540155 V. Description of the invention (5)

The following is a reference to the dielectric layer memory (if the DRAM is a region on a silicon crystal device. Here is a metal formed on the board 20, according to the capacitor of 2A). In the first circle, the insulation is simplified. A first known micro-insulator is a metal type. Here, the storage electrode 22 is also an insulator. The half leads to a 2D figure to explain the manufacturing method with a pentoxide in the embodiment of the present invention. Prior to dynamic random access, please refer to FIG. 2A, a substrate 20 is provided, for example, a semiconductor element is formed on it, and a semiconductor protective layer is covered. The contact pattern has a contact window to expose the element. Leveling substrate 20. Then, after the base conductive layer 22, for example, a platinum (pt), or (w) shadow etching process is used to define its pattern, a storage electrode 22 of a metal (MIM) valley device is formed. In addition, poly-Si can be used to form a storage electrode for a gold body (MIS) type capacitor.

Next, a low pressure chemical vapor deposition (10w pressure CVD, LPCVD) is performed using a chemical vapor deposition (CVD) device (not shown) having two liquid delivery systems (H (luid delivery system, LDS)). A dielectric layer 24 is deposited on the surface of the substrate 20 and the surface of the storage electrode 22, wherein Ti (C3H7〇) 2 ((: 111119〇2) 2 and 73 ((: 2115〇) 5, which are close to each other at decomposition temperatures) As the reaction precursor, for example, the former is about 270 / C and the latter is about 22 (TC. In addition, the vaporization temperature of Ti (C3H7〇) 2 (CiiHi9〇2) 2 is in the range of 130 to 240 ° C and Ta (C2H5. The vaporization temperature of) 5 is in the range of 50 to 80 ° C. Since the former is solid, a soluble organic solvent is added here, such as (: 4) to form a liquid. Then, the above precursors have a flow rate. Controlled separately in the range of o.ias o cc / min, and more nitrogen (Ar) and oxygen (〇2) as the carrier gas required for the reaction 'where the flow rate of argon is controlled to 20 to 7〇sccm range, and oxygen

540155 V. Description of the invention (6) '----- The rate of Qi is in the range of 30 to 200 seem. At the same time, these gases and precursors are heated using a heating tube, for example, in the range of 500 to 2000, and the deposition temperature of the substrate 20 is controlled in the range of 330 to 400 ° C. In the above-mentioned manufacturing process, 'the working pressure can be controlled within the range of &quot; ㈣ ^' s ^ Yilai 'can form a titanium dioxide doped pentoxide button dielectric layer 22, wherein the composition ratio of the dielectric layer 22 is (Ta205) ix (Ti〇2) x and satisfying ΐ5 &lt; χ = 0.25 and an atomic percentage ratio of Ti / Ta ranging from 88 to 167 at ·%. The dielectric layer 22 composed here can effectively reduce the leakage current without lowering the dielectric constant. Next, please refer to FIG. 3, which shows the relationship between the leakage current j and the percentage of ^ ~ mole doped in Ta205 under the applied electric field strength of 0.5 MV / cm. As shown in the figure, the present inventors found that when the molar percentage of Ti0 2 is in the range of 15 to 25 mol%, that is, the atomic percentage ratio of Ti / Ta is in the range of 8 · 8 to 16 · 7 at ·%. The leakage current is reduced by about two stages compared to when it is not doped. In the conventional method, for example, when the atomic percentage of Ti / Ta is in the range of 0. 1 to 4 at.%, The leakage current is compared to When there is no doping, only one step is reduced. Next, please refer to FIGS. 2B to 2C, which respectively illustrate the steps of performing a rapid thermal annealing treatment and a plasma oxidation annealing treatment on the dielectric layer 22 after the dielectric layer 24 is formed. As shown in FIG. 2B, under a condition of 700 ° C, nitrogen oxide (% 〇) or nitrogen (%) is passed in to perform rapid thermal annealing (RTA) on the dielectric layer 22 to form Dielectric layer 24a subjected to high-temperature rapid heat treatment. Next, as shown in FIG. 2C, under the condition of 450 ° C, oxygen (〇2) is introduced to perform 540155 on the dielectric layer 24a. 5. Description of the invention ⑺ '-——-Plasma oxidation annealing ( Plasma oxidation annealing (POA) treatment to form a dielectric layer 24b that is subjected to a low temperature plasma oxidation annealing treatment. In this way, the dielectric constant of the titanium dioxide doped pentoxide button can be maintained in a range close to that when tantalum pentoxide is not doped with titanium dioxide. ^ τ · η, referring to FIG. 4, which shows the relationship between the dielectric constant and the percentage of Ti 2 Molar doped in Ta205. Among them, at 700, = thermal annealing treatment and electropolymerization of T &amp; Λ at 45 (rc) ^ As shown in the figure, the inventors found that when the percentage of Ti02 Moore is 15 to 25 mol In the range of%, that is, the ratio of the atomic percentage of Ti / Ta is in the range of 88 to% ', the dielectric constant will be lower than that when it is not doped. On the surface,' Ϊ 参 f 第 2D 图 'is annealed. Processed dielectric layer 24b Table: ±: second conductive layer 26 ′ is a metal such as a surface, a crane, etc. to form a counter electrode 26 of electricity W and complete the manufacture of a MIM capacitor or a MIS capacitor. As can be seen from the above, according to the present invention The embodiment can not only effectively reduce the generation of leakage current and improve the component; maintain a high dielectric constant and reduce the second group of pentoxide = impurity impurities, that is, the capacitor can maintain a high storage. 2 However, the present invention has been implemented in a better way The example is disclosed as above, however, and to limit the present invention 'anyone skilled in this art', Shenhe _, can be changed and changed. Tian t departs from the essence of the present invention as defined by the scope of patents attached Foreword: Fork Worship 0503-6284TW; TSMC2001-0108; Chen.ptd Page 10

Claims (1)

540155 VI. Scope of patent application 1-I A capacitor manufacturing method with a tantalum pentoxide dielectric layer is suitable for a state random access memory (DRAM) and includes the following steps: A substrate is provided, and the first substrate is formed on the substrate. A conductive layer is used as a storage electrode of the capacitor; a dielectric layer is formed on the first conductive layer, wherein the composition of the dielectric layer is (Ta205) χ (η〇2) χ and satisfies 〇5 &lt; χ &lt; 〇25 &amp; η / Ta atomic percentage ratio in the range of 8 · 8 to 16.7 at ·%; and forming a second conductive layer on the dielectric layer as the opposite electrode of the capacitor and completing the capacitor Manufacturing. w The method described in item 1 of the scope of patent application, wherein the above-mentioned conductive layer is a metal layer selected from at least one of platinum and tungsten. 3. The method described in item 1 of the scope of patent application, the straight conductive layer is a polycrystalline silicon layer. Eight T on the fans one of them-species. Among them, the above-mentioned item 4 · The method described in item 1 of the scope of patent application The conductive layer is a metal layer, selected from at least 5 of platinum and tungsten · The method described in item 2 of the scope of Shenqing patent Capacitor is a metal-insulator-metal (M 丨 M) type capacitor 6. As described in the scope of the patent application No. 3 method, 苴: ^ capacitor is a metal-insulator-semiconductor (MIS) ^ second description 7. Such as the scope of patent application! In the method described in the above item, the dielectric layer is formed by a low chemical vapor deposition method (LPCVD). -Pressure 8. The method described in item 7 of the scope of the patent application. 7) The chemical vapor deposition method uses Ti (c H 〇) (CllHi9 0) &amp; 0 L as a reaction precursor. 2 夂 1 &amp; ((: 21150) 5 as 0503-6284TW; TSMC2001-0108; Chen.ptd 540155 6. The scope of patent application 9 · The method described in item 7 of the scope of patent application, wherein the above chemical vapor deposition method is more permeated with nitrogen and oxygen as the carrier gas and the flow rates are 20 to 70 seem and 30 to 200, respectively. Fan garden of seem. 10. The method according to item 7 of the scope of the patent application, wherein the working pressure of the above-mentioned low pressure chemical vapor deposition method is in the range of 0.1 to 10 t r r. 11. The method as described in item 8 of the scope of the patent application, wherein the flow rates of the reaction precursors are in the range of 0.1 to 5.0 cc / min. ~ 1 2 · The method as described in item 8 of the scope of patent application, wherein the vaporization temperature of the above Ti (C ^ O) 2 (CuU2) 2 is in the range of 1 30 to 240 ° C. 13. The method according to item 8 of the scope of patent application, wherein the vaporization temperature of the above Ta (C2H50) 5 is in the range of 50 to 80 ° C. 1 4. The method according to item 8 of the scope of patent application, wherein the temperature of the heating tube used to heat the precursor is in the range of 150 to 200 ° C. 15. The method according to item 8 of the scope of patent application, wherein the substrate deposition temperature is in the range of 330 to 400 ° C. &amp; 1 6 · The method as described in item 1 of the scope of patent application, wherein after the formation of the above-mentioned electrical layer, the method further includes introducing nitrogen oxide gas or nitrogen gas under the conditions of 700 t: Steps of rapid thermal annealing process. 17. The method as described in item 16 of the scope of the patent application, after the rapid thermal annealing treatment step in the basin, the method further comprises a step of 45 ° (rc ;; 2) = a plasma oxidation annealing treatment of the dielectric layer. step.