TW540041B - Decoding system for disk and the method thereof - Google Patents

Abstract

The present invention provides a decoding system for disk and the method thereof, which is used to receive the message data on the disk and execute the decoding operation. The present invention only needs to slightly change the structure of the decoding system to reduce the accessing number to the data buffer by each module in the decoding system without having to increase the clock of the decoding system and the width of the bus. Thus, the present invention can increase the parallel processing capability of the decoding system, so as to increase the speed of the decoding system, and further achieve the effect of high-speed compact disk.

Description

540041

FIELD OF THE INVENTION The present invention provides a decoding system and method for a disc, and more particularly, a system and method for improving disc decoding by reducing the number of data buffer accesses. Decoding of the background of the prior art Please refer to Fig. 1. Fig. 1 is a block diagram of the decoding system of a CD player. As shown in Figure 1, after the data is read from the disc 100, it is transmitted first.

Send it to EFM Plus demodulation device (Eight to Fourteen Modulation Plus demodulator) 102, demodulate 16 channel bit (C0Cie word) into 8-bit data symbol . Then, the EFM Plus demodulation and conversion device 102 will correct the error correction code data block (Eγγ〇γ) generated after the demodulation.

Correction Code data block (ECC data block for short) 107 is stored to the data buffer i06 via bus 104, where ECC data block 107 includes Main Data 108, external allocation code ( Parity of Outer-code (referred to as p0) 11 and Parity of Inner-code (referred to as PI) 112. Primary Information

The external matching code 110 is collectively called RS (Reed-Solomon) external code ', and the main information 1 0 8 plus the external matching code 11 〇 and the internal matching code 1 1 2 are collectively called RS internal code . Secondly, the error correction code decoding device (ECC decoder, referred to as ECC decoding device) 11 4 reads the ECC data block 1 07 from the data buffer 106, and sequentially decodes the X direction (that is, the pi direction) and the Y direction ( (P0 direction), and decode the ECC data block 1 07

540041 V. Description of the invention (2) The erroneous data is corrected, and then the ECC decoding device 114 rewrites the corrected part in the ECC data block 107 into the data buffer. Then, a de-scrambler and an error detection code confirmation device (Eπ〇Γ Detection Code check, referred to as EDC confirmation device) 116 reads the main data that has been corrected in the buffer area 106. Perform descrambling and EDC confirmation operations. When the host wants to read the main data 108 in the data buffer 106, it uses ATAPI (Advanceci Techn〇1〇gy)

Attachment Packet Interface (Interface Device) 118 The descrambled corrected main data 108 is transmitted to the host.

Please refer to Fig. 2. Fig. 2 is a flow chart of a conventional DVD disc player's decoding system accessing data = punching area. This process includes the following steps: First, step 201 is performed, and the EFM Plus demodulation and conversion device 102 writes the demodulated E ⑴ into the data buffer 1Q6e. Second, proceed to step 2Q2, and the material buffer 106 reads the PI direction. The ECC data block is decoded with the error rank correction, and then the corrected part of the E (χ data block 107 is written into the data buffer 106. In the following step, the ECC decoding device 114 starts from ECC data block i 2 in the data buffer i in two directions, 隹-New Zealand% hit T 1 丁 Denny 1U7 and perform error correction decoding, and then correct the ECC data block 1 07 Qiu f should be A times α 丨 〆 // 士 ... 丄, tf τ correction of the 4 wounds are written into the lean buffer 1 06: 9. After the completion of step 203, the system's requirements can be repeatedly performed step 202 and step 203 to Ancient 1? The time is 1%. 1. 7 is the completion step of the lamp holder, and enters the error correction rate of 107 on the block. 1 1 6 Lost times: π vibration, step scrambler, and EDC confirmation device.丄 & 5 take the buffer buffer to descramble and confirm the EDC action. Wait— ^ After the raw material 108 is used to wait for the Yuan to perform the above action, the master End

Page 5 540041

When the main data 108 in the data buffer 106 is taken, the steps are performed.

The Hi ^ ΑΤΑPI interface device 118 descrambles the corrected main data 108 and transmits it to the host. In the above-mentioned conventional technique, each module of the decoding system needs to perform the above steps in order to complete the decoding of the disc. Please refer to Fig. 3. Fig. 3 is a conventional ECC decoding device for RS code decoding process. First, the original coded characters in the data buffer 1 06 enter the "Syndrome generation" stage 301 and are decoded by ECC

The device 114 calculates signs in the Pi or p0 direction. Next, enter stage 302, calculate the "erasure location polynomial" according to the known erasure location, and then use the generated sign value and the erasure position polynomial to calculate rF. rney deformation polynomials (Forney, s modified syndrome polynomial), to obtain the initial value required to perform the next stage. Continuation stage 3 0 2 'Enter stage 3 03, using the initial value generated in the previous stage to distinguish "err-erasure erasure polynomial" and "err-erasure polynomial" and "error-erase Table-valued polynomials "(error-erasure evaluator polynomial). Then, enter

"Chi en search unit" stage 304, find the location of the error data, and find the value of the error data. Finally, enter the "correction" stage 3 0 5 and correct the wrong data in the original coded characters to get the correct coded characters, and write the correct coded characters into the data buffer 1 0 6 inner 0 As can be seen from Figure 1, when the conventional decoding system performs the decoding operation of the disc,

Page 6 540041 V. Description of the invention (4) Each module needs to know the speed of each module of the decoding system, the speed of the decoding system, the decoding system, the decoding system for data access, and the entire ECC decoding device 114. , All need to access data to fetch will make the whole solution speed. The current number of accesses to the clock for high decoding systems. The material buffer 106 performs an access operation. In theory, if the group can access the data buffer synchronously, it will be able to increase the effect of the DVD at a high speed; however, the actual data group needs to use the same data buffer 106; In addition, it can be known from Figures 2 and 3 that during the decoding process of the ECC data block 107, the calculus action of the error correction with the direction of P0 is the buffer 1006. Performing multiple save operations on the data buffer is very time-consuming, and it also limits the overall DVD system. There are several solutions to the above problems, including: increasing the width of the data buffer or reducing the data buffer. The purpose and method are to reduce the data delay for a decoding system of a disc

The number of access times of the ancient Xima series I + red area, so you can decode the parallel processing capabilities of the system, / $ This will achieve the effect of high-speed optical disc drive. Speed up the decoding system

In the first embodiment of the present invention, after the Efm operates, the generated Ecc data US demodulation and demodulation device is demodulated, and the ECC decoding device enters and exits to the ECC decoding device. The ECC data block is temporarily stored in the data buffer area = correction decoding, and after the error correction of the ECC data block on the network, the ^ ECC decoding device completes descrambling and EDC confirmation actions. After the $ 2 beard and the EDC confirming device are able to perform the above actions, they will become the main tip.

540041

V. Description of the invention (5) When the terminal wants to read the main data in the data buffer, it will descramble the main data through the device and send it to the host. 1 The second embodiment of the present invention is similar to the first embodiment. The difference lies in that when the EM code device performs error correction decoding in the PI direction, the main data and the error value after p solution are also input to the first descrambler and EDC. The confirmation device uses the descrambling frequency and the EDC confirmation action. When subsequent decoding operations in the directions ⑼ and ^ are performed, the part of the main data that has completed the EDC confirmation action can be skipped without decoding, and when the subsequent P 〇With? After the decoding operation in the 1 direction, the second descrambler and the EDC confirmation device will perform the EDC confirmation operation again for the main data in the data buffer that has not yet completed the EDC confirmation operation. ^ The difference between the third embodiment and the first embodiment of the present invention lies in that the third embodiment has two ECC decoding devices, namely a first Ecc decoding device and a second ECC decoding device. The two decoding methods are divided into two types. Design: (1) The first ECC decoding device is performed only for the first time? Decoding in the 1 direction, and subsequent decoding operations are handled by the second ECC decoding device. (2) Only the first ECC decoding device processes? Decoding in the 1 direction, while the second ECc decoding device only processes decoding in the P0 direction. The fourth embodiment of the present invention is another aspect of the third embodiment. If the ECC decoding device is in the situation (1) of the third embodiment, the first Ecc decoding device performs the first error correction decoding in the PI direction. The first descrambler and the EDC confirming device will perform descrambling and EDC confirming operations on the main data simultaneously, and the second ECC decoding device will perform the second error correction decoding in the direction of the direction 'the second descrambler And EDC confirm that the equipment will carry out

540041 V. Description of the invention (6) Expected descrambling and EDC confirmation actions; after repeated decoding, the third descrambler and EDC confirmation device will re-attempt the main data in the data buffer that has not yet completed the EDC confirmation action. Perform descrambling and EDC confirmation operations. The fifth embodiment of the present invention is when the Ecc decoding device is in the (.2) situation of the third embodiment; whether it is the first or second decoding in the p 丨 direction, the first descrambler and EDC are shared. The confirmation device is installed, so the second descrambler and the EDC confirmation device in the fourth embodiment are not needed. Brief Description of the Drawings Figure 1 is a block diagram of the decoding system of a conventional DVD player. Figure 2 is a flowchart of the process of accessing the data buffer of the decoding system of a conventional DVD player. Fig. 3 shows the decoding process of the RS code performed by the conventional ECC decoding device. Figure 4 (a) is a block diagram of the first embodiment of the decoding system of the present invention. FIG. 4 (b) is an internal block diagram of the ECC decoding device in FIG. 4 (a). FIG. 4 (c) is another embodiment of FIG. 4 (b). FIG. 5 is a block diagram of a second embodiment of the decoding system of the present invention. FIG. 6 is a block diagram of the third embodiment of the decoding system of the present invention. FIG. 7 (a) is a block diagram of a fourth embodiment of the decoding system of the present invention. FIG. 7 (b) is a block diagram of a fifth embodiment of the decoding system of the present invention. Fig. 7 (c) is an internal block diagram of the first descrambler and the EDC confirmation device in Fig. 7 (b). '' Symbols of Schematic Elements

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540041 V. Description of the invention (7) 100-disc 102EFM Plus demodulation device I 0 4 bus 1 0 data buffer 107 ECC data block 108 main data II 0 external distribution code 11 2 internal distribution code 114ECC decoding device 11 6 descrambler and EDC confirming device 118ATAPI interface device 4202 first sign value generator 40 3 sign value generator 404 second sign value generator 406Fourney deformation sign value polynomial generator 408 Error-Erase table-valued polynomial generator table 410 Chien search unit 412 first syndrome value register 414 second syndrome value register 502 first descrambler and E]) c confirmation device 504 second descrambling Frequency converter and EDC confirmation device 60 2 first ECC decoding device, 604 second ECC decoding device 702 third descrambler and Edc confirmation device 704 first EDC register 706 second EDC register 708 EDC confirmation The detailed description of the device invention = =, the features and advantages can be more obvious and easy to understand. The following is a detailed description of the drawings in the conventional knowledge, as follows: Codes, plus resources: The decoding device 114 can be repeated. Unstable decoding time = set mutation, which makes ECC decoding device 114 solve EF M Plus ^ t ^ m ^ ^ ^ ^ ^ Save the ECC data area. Plus the demodulation device 102 needs to temporarily store the ghost 107 in the data buffer 106, and then, the ECC solution

Page 10 540041 V. Description of the invention (8) y Ma 2 sets 1 1 4 and then reads the ECC data block 1 0 7 from the lean buffer 1 06 = = action. However, because the data of the EFM Plus demodulation and conversion device 102 is the same, the EFM Plus demodulation 11 / (shell material can be directly output to the ECC decoding device 114, and then decoded by the ECC solution ^ ^ @ direction, At the same time, the ECC data block 107 is temporarily stored: within the second red area 106 'to save the time for the next ECC data block 107 to read the data buffer 1 06. I Sit 24: Figure 4 (a) This is the first embodiment of the decoding system of the present invention: Ghost image. The decoding system in Figure 4 (a) is slightly similar to Figure 1. The difference is that the EFM Plus demodulation device 10/2 and the ECC data area The block 107 is output to the Ecc solution station. The gate is connected to the decoding device 114. After that, the ECC decoding unit 114 uses the RS internal code to calculate the value m of the data-like block. The error correction decoding in the secondary direction, then, the Ecj code I is set to 1, 14 and the ECC data block 1Q7 is temporarily stored in the f buffer \\. The ECC decoding device 114 will use the EFM pius demodulation to produce the ecc data. At the time of the empty mark between blocks m, the subsequent correction of the p0 fish material group is performed for the ECC material block 10 that has previously been allocated to the second material punching area 106. When the ECC decoding device 114 completes the correction of the Ecc data, the descrambler and the EDC confirming device 116 read the main data 1 08 'in the data delay error and perform descrambling and E]) c Exactly, after the actions described in the description are completed, when the host wants to read the data area ^ main data 108, it sends the master = the scrambled data to the host through the ATAPI interface device 118. Therefore, the knowledge with Figure 1 ^ The receiver / village 1 decoding system can reduce the first-time PI-direction decoding pair :: car delivery 'Figure 4 of the TR 枓 buffer 1 0 6 of 540041 5. Description of the invention (9) " One read count. Figure 4 (b) is an internal block diagram of the ECC decoding device 114 in Figure 4 (a). When the first sign value generator 402 calculates the jECC data block 107 from the EFM P1US demodulation device 102, the second sign value generator 400 also calculates that it has been stored in the data buffer first. The PI or ㈧ of the ECC data block 107 of 1 06 = the direction sign value. Next, the Forney deformation syndrome polynomial generator, the error-erased epitope and the table-valued polynomial generator 408 and the Chien search unit 41. It will alternately process the sign values from the first sign value generator 4202 and the second sign value generator 404, so that errors can be made without losing the data from the EFM pius demodulation device 102. Corrected decoding action. Figure 4 (c) is another aspect of Figure 4 (b). The difference between the two lies in the part of the signboard. Figure 4 (c) integrates the calculation of the sign values in the ^ and ⑼ directions into a single sign. The value generator 403 performs it, but the generated syndrome value ^ is temporarily stored in the first syndrome value register 412 and the second syndrome value register 414. Assume that the data before the PI direction is updated, the updated data is ⑼, and the error value is rl (x) = r (x) + eW. Therefore, the new E after the error is corrected can be expressed as: EDC {x) r, = EDC (x) r + EDC (x) e

From the above formula, it can be known that when the EDC confirmation operation is performed, a new edc confirmation result can be obtained by adding the edc confirmation result before the update to the EDC confirmation result of the wrong value. Since the descrambler and the EDC confirmation device 116 read the main data 108, what is the direction? 1 direction, so will? The edc confirmation result before the 1 direction update, plus the E D C confirmation result of the error value when decoding in the P I direction, can obtain p I

540041 5. Description of invention (ίο) New EDC confirmation result after direction decoding. Therefore, the descrambler and the EDC confirming device 116 can also perform the descrambling and EDC confirming operations of the main data 108 synchronously when the ECC decoding device 114 performs the PI direction decoding. In this regard, please refer to FIG. 5, which is a block diagram of the second embodiment of the decoding system of the present invention. When the ECC decoding device 114 performs error correction decoding in the PI direction, the main data 108 and the PI decoded error value are also input to the first descrambler and the EDC confirmation device 502 to perform descrambling and EDC confirmation operations, and then perform When performing the decoding action in the directions of p0 and pi, the part of the main data 108 that has completed the edc confirmation action can be skipped and no longer decoded. This can avoid corrections and errors. And when completing the subsequent p0 and? Decoding action in the 1 direction 'brother descrambling device and EDC confirmation device 5 04 will focus on the main data of the EDC confirmation operation part 108 in the data buffer area, and then enter the homepage = descrambling and EDC confirmation operation . Therefore, compared with the structure of Figure 4, Figure ^, Department: you do n’t need to perform EDC recognition again.

= Two ^. Time ′ and ™ confirm the action ST ^ i =, or even an exponential relationship, so the ECC solution ^ area is reachable not less than 14 and has the big block 1 07 are both binary / Λ \ 新 白,. However, not every ECC code speed can be set to be decoded by two people. Therefore, in order to reduce the cost and improve the decoding method, a decoding system is designed. Figure 6 is a block diagram of the first 'κ' example of this ',' 4. Figure 6 Decoding System and

Page 13 540041

Figure 4 is similar, the difference lies in the part of the ECC decoding device; the decoding system of Figure 6 has two ECC decoding devices, namely the first Ecc decoding device 602 and the second ECC decoding device 604. The two designs are described as follows: (3) The first ECC decoding device 602 only processes the ECC data block 107 transmitted by the EFM pius demodulation device 102, that is, the first Ecc decoding device 602 The first PI direction decoding is performed, and the subsequent decoding operations are processed by the second ECC decoding device 604. For the first time? The decoding speed in the 1 direction can be reduced to the same time as the EFM Plus demodulation device 102 inputting the Ecc data block 107, and the first area ECC decoding device 602 with a smaller area can be used to process the first PI. Decoding of directions. (4) The first ECC decoding device 602 only processes the decoding in the pm direction, and the second ecc decoding device 604 only processes the decoding in the p0 direction. Therefore, this design can also reduce the decoding speed and use a smaller area ECC decoding device. Compared with FIG. 4, the area of the first ECC decoding device 602 in FIG. 6 plus the second EK decoding I set 604 is smaller than the area of the Ecc decoding device in FIG. In the same way as in Figure 5, the descrambler and the EDC confirmation device can synchronize the main data and the edc ^ confirmation operation when the Ecc decoding I is set to the decoding of the PI direction. Please refer to Figure 7 "), Figure 7 (a) is another type of cancer owed to Figure 6, if the ECC decoding device is the situation of Figure 1 (1), the first ECc code device 6 0 2 is performing the first p 丨When the direction is corrected for error correction, the first descrambler and the EDC confirming device 502 will perform descrambling and EDC confirming operations on the main data 108 simultaneously. The second ECC decoding device 604 is performing p. Square 540041

When decoding to it, the part that has been confirmed by EDC is not corrected to avoid the situation of correction error. When performing the second error correction decoding in the PI direction, the part of the main data 108 that has completed the EDC confirmation operation can be skipped and no longer decoded. This can speed up the decoding and avoid the situation of correcting errors. Similarly, the second The descrambler and the EDC confirmation device 504 will perform the descrambling and EDC confirmation operations of the main data 108 simultaneously when performing error correction decoding in the PI direction. After repeated decoding, the third descrambling device and the E1) confirmation device 702 will perform descrambling and EDC confirmation operations again on the main data 108 in the data buffer 106 that has not yet completed the EDC confirmation operation. If the ECC decoding device is in the situation of Fig. 6 (2), please refer to Fig. 7 (b). Whether it is the first or second decoding direction, the first descrambler and EDC confirmation device 502 are shared. Therefore, the second descrambling frequency is not necessary for the EDC confirmation device 504. , W For the internal structure of the first descrambler and the EDC confirmation device 502 in Fig. 7 (b), please refer to Fig. 7 (c). As shown in FIG. 7 (c), after the EDC confirmation device 708 completes the EDC confirmation operation, it only needs to store the EDC confirmation result in the first EDC register 704 or the second EDC register 706. As can be seen from Figures 4 (a) to 7 (c), when the ECC decoding device performs error correction decoding in the PI and ⑼ directions, it reduces the number of times the data is repeatedly read from the data buffer, which will greatly reduce the number of data buffers. Number of accesses. In addition, the ECC decoding device described in the decoding system of the present invention may be a decoding calculation architecture of RSPC (Reed Solomon Product Code). The data buffer can be EDO-RAMUxtended Data (out RAM), static random access memory (Static Random Access Memory, SRAM), and dynamic random access.

540041 V. Description of the Invention (13) Access to Dynamic Random Access Memory (DRAM), Synchronous Link DRAM (SL-DRAM), DR-DRAM (Direct Rambus DRAM), EDO-DRAM (Extended Data Out DRAM), synchronous dynamic random access memory (Synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (Double Data Rate SDRAM, ddisdram), virtual channel synchronous dynamic random access memory ( Virtual

Channel SDRAM, VC-SDRAM). Therefore, compared with the conventional decoding system, the decoding system of the present invention does not need to improve the timing of the system, nor does it need to increase the bus width, which can effectively reduce the number of accesses to the data area and shorten the system response. Time, improve the DVD processing capacity of the decoding system, and then speed up the decoding system to achieve a high speed effect. However, it is clear that: "Any person skilled in the art" of the present invention is not restricted from the enthusiasm and intrigue of the present invention, so this daze will be regarded as defined by the scope of the attached patent . As mentioned above, although the present invention has been disclosed in five preferred embodiments as described above

Claims (1)

540041 7. 12 --- Case No. 9010224_2 ____ year one, ... said amendment_ six, patent application scope1. A disc decoding system for receiving information and performing decoding actions on the disc, the decoding system includes : A demodulation device for receiving the message data of the disc and performing a demodulation operation to generate an Error Correction Code data block 'The error correction code data block contains A parity 〇f inner-code (PI) and a parity of outer-code (P〇) in a main data; ^ Decision correction code decoding device for decoding operations for error correction Data buffer for temporarily storing the main data, the internal matching code and the external matching code; descrambler and error detection check) device data, and into an advanced technology Attachment zone has been output to the host The demodulation block directly outputs the device to complete the internal block temporary storage device, and then performs subsequent completion error correction to read and descramble the packet to connect to the end of the packet; To the erroneous department, the code is confirmed in the data access to the data, and the error correction of the code is confirmed (E rr 〇 r D etecti ο n C 〇de) to take the main and error detection that has been corrected in the data buffer. Code confirmation action; and an interface (Advanced Technology Interface) device for reading the data to slow down the main data and descrambling the main data after demodulating the error correction code data area correction code decoding device, After the error correction code is decoded in the decoding direction, the error correction code is decoded in the data buffer; after that, the error correction code is decoded; the error correction code data block in the buffer is being decoded; and when the error correction code is decoded, After the device operates, the descrambling and error detection codes are correct. 540041 --- The year of the cliff is q. 6. The scope of patent application ^ The device will perform Γ scrambling and error detection code confirmation for the main data that has been corrected in the data buffer area; when the main terminal needs the main data :: Ϊ ΐ Ϊ The advanced technology packet connection interface device sends the corrected main frame angle to the host after scrambling. The decoding system described in the first item of the present invention, wherein the demodulating device is a demodulating code character having μ channel bits into n (m> n) bits of data symbols. 3. The decoding system as described in item 1 of the scope of patent application, wherein the error correction code decoding device may be a decoding algorithm structure of a Reed-Solomon Product Code. 4. The decoding system as described in item 1 of the scope of patent application, wherein the error correction code decoding device includes a syndrome generator to calculate the error correction code data block from the demodulation device or the data buffer. Symptom value. 5. The decoding system as described in item 4 of the scope of patent application, wherein the error correction code decoding device further includes a sign value register to store the sign value calculated by the sign value generator. 6. The decoding system as described in item 1 of the scope of patent application, wherein the data buffer can be a static random access memory (SRAM) and a dynamic random access memory (SRAM) Random Access Memory (DRAM), Synchronous Link Dynamic Random Access Memory (SL-DRAM), DR-DRAM (Direct Rambus DRAM), EDO-DRAM (Extended Data Out DRAM), Synchronous Dynamic Random Access Memory Memory (Synchronous DRAM, SDRAM), dual data rate synchronous dynamic random access memory (D oub 1 e D ata R ate 540041 Case No. 90102242 Modification 6. Patent application scope SDR AM (DDR-SDRAM), virtual channel synchronous dynamic random access memory (Virtual Channel SDRAM, VC-SDRAM) and other memories. 7 · A disc decoding method for receiving the message data of a disc and performing a decoding operation, the decoding method includes: (1) t buy the message data of the disc to a demodulation conversion device, the demodulation conversion The device performs demodulation on the message data to generate an Error Correction Code data block. The Error Correction Code data block includes a main data and an internal parity code. -code (PI) and an external parity of code (PO); (2) transmitting the error correction code data block to an error correction code decoding device 'and correcting errors in the direction of the internal verification code Decoding; (3) writing the error correction code data block to a data buffer; (4) accessing the error correction code data block in the data buffer for subsequent error correction decoding; (5) Reading the corrected main data in the data buffer to perform descrambling and error detection code confirmation (counting r 0 r Detecti ο n C 〇decheck); and (6) reading the data buffer Internal The positive through the primary data packet to an advanced technology attachment interface (Advanced Technology Attachment Packet Interface) device, the output terminal to the host after descrambling key information. 8. The decoding method as described in item 7 of the scope of patent application, wherein the demodulation device is to demodulate a coded word having M channel bits into N (M > N) bits Page 2002 2002. 07. 04. 020 540041 Information symbol of Yuan. 9. The decoding method described in Item 7 of the patent scope of the patent claim, wherein the error correction code decoding setting can be a decoding algorithm structure of a Reed solo product code. 1 0 · The decoding method as described in item 7 of the scope of the patent application, wherein the error correction code includes a sign generator to calculate the error correction code from the demodulation device or the lean buffer The sign value of the data block. 11. The decoding method as described in item No. 0 of the patent application scope, wherein the error correction code decoding device further includes a sign value register to store the sign value calculated by the sign value generator. 1/2 · Decoding method as described in item 7 of Shen Qing's patent scope, wherein the data buffer can be SRAM, DRAM, SL-DRAM, DR-DRAM, EDO-DRAM, SDRAM, DDR-SDRAM, VC-SDRAM And other memory. 1 3 · — A decoding system for a disc, which is used to receive the message data of the disc and perform a decoding action. The decoding system includes: a demodulation device for receiving the message data of the disc and demodulating it The station operates to generate an error correction code data block (Err〇r C〇rrectin code data block). The error correction code data block includes a main data, an internal parity code (Parity 〇f Inner-code, PI) and an external parity code (Parity of Outer-code, P0); an error correction code decoding device for performing error correction decoding operations; a data buffer for temporarily storing the main data, the internal matching Code and the external matching code; a first descrambler and error detection code confirmation (Error Detect ion m Sllll i Page 21, 2002.07. 04.021, 540041 Amendment No. 90102242 VI. Patent application scope (Code check) device, used to read the main data in the data buffer to perform descrambling and error detection code confirmation actions; A second descrambler and error detection code confirmation device for reading the main data in the data buffer that has not yet completed the error detection code confirmation operation, and performing descrambling and error detection code confirmation again Action; and an advanced technology packet connection interface (Advanced Teehnology Attachment Packet Interface) device for reading the main data that has been corrected in the data buffer and descrambling the main data and outputting it to the host; 'The demodulation device outputs the error correction code data block generated after the demodulation directly to the error correction code decoding device. When the error correction code decoding device performs error correction decoding of the internal matching code direction, the main The error value after decoding the direction of the internal matching code in data f is also input to the first descrambling frequency and error detection code confirmation device for Scrambled and error detection code confirmation action; then the error correction code data block is temporarily stored in the data buffer, and after the subsequent decoding actions of the external matching code and the internal matching code direction are completed , The first descrambling and error detection code confirmation device will perform descrambling and error detection code confirmation again for the main data in the portion of the tribute buffer that has not completed the operation of error detection code confirmation. Action: When the host side needs the main data, the corrected main data is descrambled and transmitted to the host side through the advanced technology packet connection interface device. 14. The decoding system according to item 13 of the scope of the patent application, wherein the demodulation device demodulates a coded word having M channel bits into a data symbol of n (m > n) bits. Page 22, 2002. 07. 04. 022 540041 __ Case No. 90102242_- VI. Patent application scope 1 5 · If the patent application scope No. 13 is a decoding system described in the above description, the error correction code decoding device may be a Li Deed solomon product code (Reed Solomon Product Code) decoding algorithm architecture. 16 · The decoding system as described in item 3 of the scope of patent application, wherein the data buffer can be SRAM, DRAM, SL-DRAM, DR-DRAM, EDO-DRAM, SDRAM, DDR-SDRAM, VC-SDRAM, etc. Memory. 1 7. —A method of decoding a disc, which is used to receive the message data of a disc and perform a decoding action. The decoding method includes: (1) item taking the message data of a 5 Hai disc to a demodulation device, the The demodulation device performs demodulation on the message data to generate an error correction code data block. The error correction code data block (Err〇r C〇rrecti data block) contains a main data, an internal configuration Parity code (PI) and an external parity code (Parity 〇f Outer-code, P〇); (2) transmitting the error correction code data set; block to an error correction code decoding device ( 3) The 5 Hai error correction code solves the problem of Ma Ma Li's confirmation device, and performs internal synchronization simultaneously.-A first descrambling and error detection code scrambling and error detection code confirmation action. 4) Write the error correction code data (5) Read the ^ block in the data buffer to a data buffer; code device to perform subsequent main data to the error correction code error correction correction decoding; D Misalignment between the verification code and the internal verification code 2002. 07. 04. 023 540041 ---_ Case No. 90102? 4 years ^! Month Day Amendment VI. Patent Application Range / Descrambler and Error Detection Code Confirmation (E rr 0 r D etecti 〇n C 0 de deck) device ', for the main data in the data buffer that has not yet completed the error detection code confirmation action part, perform descrambling and error detection code again; and (7) take the data The main data that has been corrected in the buffer area is sent to an Advanced Technology Attachment Packet Interface device, and the main data is descrambled and output to the host. 1 8. The decoding method as described in item 17 of the scope of the patent application, wherein the demodulation means is to demodulate a coded character with M channel bits into N (M > N) bits Information symbol. 19. The decoding method according to item 7 in the scope of the patent application, wherein the error correction code decoding device may be a decoding algorithm structure of a Reed Solomon Product Code. 20β The decoding method described in item 17 of the scope of patent application, wherein the data buffer can be SRAM, DRAM, SL_DRAM, DR-DRAM, EDO-DRAM, SDRAM, DDR-SDRAM, VC-SDRAM and other memories. 2 1 · — A decoding system for a disc, which is used to receive the message data of the disc and perform a decoding operation. The decoding system includes: a demodulation device for receiving the message data of the disc and demodulating it Anxious action to generate an error correction code data block (Err〇r Correction code data block), the error correction code data block contains a main data, an internal check code (Parity of Inner-code (PI) and An external verification code (Parity of Outer-code, P0); Page 24 2002. 07. 04. 024 540041 __Case No. QfU〇2242 Car month date correction __ VI. Patent application scope 1 data buffer area for temporarily storing the main data, the internal distribution code and the External verification code; a first error correction code decoding device for performing the first error correction decoding of the internal correction code direction of the error correction code data block; a second error correction code decoding device for performing the first correction Error correction code data block subsequent correction of errors in the direction of the external matching code and the internal matching code;-descrambler and Error Detect Code Check device to read the data buffer The main data that has been corrected in the red zone is used to perform descrambling and error detection code confirmation actions; and an Advanced Technology Attachment Packet Interface device is used to read the corrected data buffer. Pass the main data, and descramble the main data and output it to the host; where the deblocking is directly input the error correction code and decode it; The decoding of the data error detection code is adjusted by the advanced technology to produce the error correction code line. The first time the positive code data is decoded, the second error is changed. The scrambler and the host-side device need to be adjusted to install the modified data. The decoding device installs the subsequent King Lane; and after the action, the buffer confirms that the moving packet consecutively will solve the first misplacement and enter the error. The error is more correct, the solution has been changed; when the interface decoding device is installed internally, The allocation block is temporarily submitted by the positive code solution for error detection. The main correction is required for the main correction and error correction, and the receiving code is stored in the second error code device for coding and confirmation of the main positive code data area. The first wrong direction error correction data buffer error correction code solution completion error correction device will descramble and wrong time, descrambling through the required data Page 25 2002. 07. 01 〇25 540041 _Case No. 9010? State _ year month day _ amendment __ VI. The scope of patent application will be transmitted to the host. 2 2 · The decoding system as described in item 21 of the scope of patent application, wherein the demodulation device is to demodulate a code character with M channel bits into a data symbol of N (M > N) bits . 2 3 · The decoding system as described in item 21 of the scope of patent application, wherein the first error correction code decoding device and the second error correction code decoding device may be a Reed-Solomon product code (R eed S ο 1 〇m ο η P r duct Co). 2 4 · The decoding system described in item 21 of the scope of patent application, wherein the data buffer can be SRAM, DRAM, SL-DRAM, DR-DRAM, EDO-DRAM, SDRAM, DDR-SDRAM, VC-SDRAM, etc. Memory. 2 5 · —A method of decoding a disc, which is used to receive the message data of a disc and perform a decoding action, the decoding method includes: (1) reading the message data of the disc to a demodulation device, the The demodulation device performs the demodulation operation on the message data to generate an error correction code data block. The error correction code data block includes a main data and an internal parity code. of Inner-code (PI) and an Parity of Outer-code (P0); (2) transmitting the error correction code data block to a first error correction code decoding device, and performing the first internal Error correction decoding in the code direction; (3) Write the data block of the error correction code to a data buffer; (4) Read the data block of the error correction code in the data buffer to a second error Correct code decoding device for subsequent external matching code and internal Page 26: 2002.07.04.026 540041 Case No. 90102242: Amendment VI. Correction and decoding of errors in the direction of the patent application distribution code; (5) Read the main data that has been corrected in the data buffer to a descrambler and The Error Detection Code check device 'performs descrambling and error detection code confirmation actions; and (6) reads the main data corrected in the data buffer to an advanced technology packet An interface (Advanced Technology Attachment Packet Interface) device is connected, and the main data is descrambled and output to the host. 2 6 · The decoding method as described in item 25 of the scope of patent application, wherein the demodulation and conversion device demodulates the coded characters with M channel bits into data symbols of n (M > N) bits . 2 7 · The decoding method described in item 25 of the scope of the patent application, wherein the first error correction code decoding device and the second error correction code decoding device may be Reeds-Solomon product codes (reeds ο 1 〇 m 〇n Pr duct 〇de) decoding decoding architecture. 2 8 · The decoding method described in item 25 of the scope of patent application, wherein the data buffer can be SRAM, DRAM, SL-DRAM, DR-DRAM, EDO-DRAM, SDRAM, DDR-SDRAM, VC-SDRAM, etc. Memory. 2 9 · — A decoding system for a disc, which is used to receive the message data of the disc and perform a decoding action. The decoding system includes: a demodulation device for receiving the message data of the disc and demodulating Change the action to generate a grr〇r Correction Code data block, which contains a main data, an internal parity code (PI) and An external Page 27. 2002. 07. 04. 027 ^ 4004j Amendment m〇? .9A9 said patent application scope code (Parity Of Outer_c〇de, p〇);: material buffer 'is used to temporarily store the main information, the internal allocation Nuclear code allocation code: First error correction code decoding device for correcting and decoding the error correction code data misalignment code direction; JT f two error correction code decoding device for performing the correction Error correction code data = block outside = core code direction error correction decoding; σ and error detection code confirmation (E rr 〇rdetecti 0 n C 〇det = air set 'is used to read the corrected main ^ ^ / in the data buffer for descrambling and error detection code confirmation Actions; and an advanced technology packet connection interface (Advanced Technology Facility PaCket InterfaCe) device, which is used to read the data and slowly output the main data to ^ $, and descramble the main data to: == The error correction code data area error correction generated after = ^ ΐ code decoding device, and then the first wrong stone horse, eve: the decoding device will only perform internal correction code direction error correction in the solution area. The error is corrected, and the data block is temporarily stored in the data buffer. The error correction decoding of the correction code / partial allocation code direction is passed to the second error: Hai interference: Ϊ: device management; and decoding of the error correction is completed. After the action, the corrected product detection error detection code confirmation device will work on the data buffer; when the main data is descrambled and the error detection code is confirmed to connect the main data, it is connected through the advanced technology packet. , Will be corrected The main data descramble transmitted to the host after frequency 540041 fix -—— Case No. 901099/19 6. Declaring patent scope end 0 3 0 · The decoding system described in item 29 of the scope of patent application, wherein the demodulation device will have M channel bit code words The element demodulation becomes a data symbol of N (μ > n) bits. 3 1 β The decoding system as described in item 29 of the scope of patent application, wherein the first error correction code decoding device and the second error correction code decoding device may be a Reed-Solomon product code (Ree (1 Solomon Product Code) decoding algorithm architecture. * 3 2 · The decoding system described in item 29 of the patent application scope, wherein the data buffer can be SRAM, DRAM, SL-DRAM, DR-DRAM, EDO-DRAM , SDRAM, DDR-SDRAM, VC-SDRAM, etc. 33 · —A method of decoding a disc, used to receive the information of a disc and perform a decoding operation. The decoding method includes: (1) reading the The message data of the disc is transmitted to a demodulation device, and the demodulation device performs a demodulation operation on the message data to generate an error correction tlT ^ n ^ TeCt [〇n Co〇de data M〇ck) 5 The correction code negative material block contains a main respect upset. +, τ Wang Yibei, an internal parity of code (Parity of Inner-code P) ^ m ^ nil,, Dn, ⑽6, PI) and-an external parity code (Parity of Outer-code, P〇); (2) Send the error correction code data area dream stop, 隹 —Ka Rudi a wrong correction code decoding 1 set, Ajin's internal distribution code direction error (3) Write the error correction code data block to— At noon, (4) read the second error area in the data buffer, and the second error correction code decoding device to perform the ... block to the first h.更 The error of the distribution code direction is more Page 29, 2002. 07. 04. 029 540041 -— Case No. 卯 102242g Amendment VI. Patent Application Scope / Positive Decoding; (5) 卖 Sell the main data that has been corrected in the data buffer area. Descrambler and Error Detection Code check device 'to perform descrambling and error detection code confirmation actions; and (6) read the main data that has been corrected in the data buffer to An Advanced Technology Attachment Packet Interface device, which descrambles the main data and outputs it to the host. 3 4 · The decoding method as described in item 33 of the scope of the patent application, wherein the demodulation device demodulates a coded character with M channel bits into a data symbol of N (M > N) bits . 3 5. The decoding method as described in item 33 of the scope of the patent application, wherein the first error correction code decoding device and the second error correction code decoding device may be Reed Solmon product codes Code) decoding algorithm architecture. 3 6 · The decoding method described in item 33 of the scope of patent application, wherein the data buffer can be SRAM, DRAM, SL-DRAM, DR-DRAM, EDO-DRAM, SDRAM, DDR-SDRAM, VC-SDRAM And other memory. 3 7 e — A decoding system for a disc for receiving the message data of the disc and performing a decoding action. The decoding system includes a demodulation device for receiving the message data of the disc and performing demodulation. Change action to generate an Error Correct i on Code data block, which contains a main data, an internal parity of inner-code (PI), and an external Page 30 2002 · 07. 04 · 030 ^ 4〇〇4i Case No. 9010224? $ 'Application for patent scope allocation code (Parity 〇f 0ute bu c〇de, p〇); ~ data buffer for temporary Depositor & a η '^ ^ Recognize the main material of Liuzi, the internal distribution code and the distribution code; ff #ls decision correction code decoding device, used to perform the error correction code data two , The first time the internal correction code direction error correction decoding;-a descrambler and error detection code confirmation (Error Detecti0n = e check) device, used to read the data buffer The main resource j is to perform the first descrambling and error detection code confirmation actions; the second and second error correction code decoding device is used to perform the error correction code data ^, and the subsequent external code and internal code Correction decoding of direction errors; a first descrambling frequency and error detection code confirmation device for reading the main data in the data buffer to perform the second descrambling and error detection code confirmation operation; / Second descrambler and error detection code confirmation device for reading the data The main data of the error detection code confirmation action in the buffer has not been completed, and the descrambling and error detection code confirmation actions are performed again; and the Advancedcj Technology Attachment Packet Interface device is used to read the data The main data that has been corrected in the buffer area is descrambled and output to the host; the demodulation device outputs the error correction code data block generated after the demodulation directly to the first An error correction code decoding device, the first error correction code decoding device performs the first error correction decoding of the internal matching code direction, and the first descrambler and the error detection code confirmation device will Page 31, 2002. 07. 04. 031 540041 Case Dai 90102M9 6. The patent application scope requires the data to be descrambled for the first time, and the error correction code information will be obtained after the external allocation code and the internal brother correct the correction code. The code device performs the descrambling and error detection of the second descrambler and error data within the second time. The decoding device completes the error device and error detection code confirmation, and installs the detection code confirmation of the error detection code confirmation action. Action; when the main technology packet connection interface is installed, it is transmitted to the host. Frequency and wrong block temporary allocation of the core code device, all parts of the core detection code detection code correction is correct, the main machine needs to set the wrong detection code stored in the direction of the asset, when the code direction The confirmation device recognizes the action; the decoding action re-checks the main data once again. The error correction in the data buffer is decoded. The second error is corrected. The error correction solution will be performed simultaneously. When the descrambling data is still in the area, after the main data is penetrated, then when it is handed over to the positive code for decoding, the main error is more descrambling is not completed and the error is descrambling first. The decoding system described in item 37 of the scope, wherein the demodulation I is configured to demodulate a coded word having M channel bits into a data symbol of NM> N) bits. 399 The decoding system as described in item 37 of the scope of patent application, wherein the first error correction code decoding device and the second error correction code decoding device may be Reed-Solomon product codes (Reed s〇 丨〇m〇n Product Code) decoding algorithm architecture. 40 · The decoding system as described in item 37 of the scope of patent application, wherein the data buffer can be SRAM, DRAM, SL-DRAM, DR-DRAM, EDO-DRAM, SDRAM, DDR-SDRAM, VC-SDRAM, etc. Memory. 4 — A method of decoding a disc, used to receive the message data of a disc and Page 32 2002. 07. 04 · 032 540041 Case No. 90T 02242 Amendment VI. Patent application scope to perform a decoding operation. The decoding method includes: (1) reading the message data of the disc to a demodulation device, The demodulation device performs demodulation on the message data to generate an Error Correction Code data block, where the error correction code data block includes a main data, an internal allocation code ( Parity oi Inner-code (PI) and an external matching code (Parity of Outer-code, P0); (2) transmitting the error correction code data block to a first error correction code decoding device; (3) — The first error correction code decoding device, a first descrambler and an error detection code check device synchronize the error correction decoding, descrambling, and error detection of the first internal verification code direction simultaneously. Code verification action; (4) Write the error correction code data block to a data buffer; (5) Take the error correction code data block in the direction of the external distribution code in the data buffer to a first buffer Two mistakes Positive code decoding device to perform error correction decoding in the direction of the external matching code; (6) reading the data block of the error correction code in the direction of the internal matching code in the data buffer to a second error correction code decoding device and A second descrambling writes the errors to the code #recognition device to synchronize the second internal_matching code direction error # to correct the decoding, decoding, and error detection code 4 recognition actions; read the data buffer The main data that has been corrected in the area to a third == error detection code confirmation device will be performed again for the main data in the data buffer-which has not yet been converted into an error detection code. Page 33 2002. 07. 04. 033 540041 -_______ Case No. 90102242 __ — year, month, and day of amendment 6. Patent application frequency and error detection code confirmation actions; and (8) reading the data buffer has been corrected The main data is passed to an Advanced Technology Attachment Packet Interface device, and the main data is descrambled and output to the host. 4 2 The decoding method according to item 41 of the scope of patent application, wherein the demodulation device demodulates a coded word having M channel bits into a data symbol of n (M > N) bits. 4 3 · The decoding method as described in item 41 of the scope of patent application, wherein the first error correction code decoding device and the second error correction code decoding device may be a Reed-Solomon product code (R eed S ο 1 〇m ο η P r duct Co). 44. The decoding method described in item 41 of the scope of patent application, wherein the data buffer can be SRAM, DRAM, SL-DRAM, DR-DRAM, EDO-DRAM, SDRAM, DDR-SDRAM, VC-SDRAM, etc. body. 4 5 · — A decoding system for a disc for receiving the message data of the disc and performing a decoding action, the decoding system includes: a demodulation device for receiving the message data of the disc and performing decoding Modulate the action to generate an Error Correction Code data block. The Error Correction Code data block contains a main data and an internal matching code (Parity of lnner — code, PI). ) And an external matching code (Parity of Outer-code (P0); data buffer, used to temporarily store the main data, the internal matching code and the external matching code; Page 34 2002.07.04.034 540041 Amendment No. 90102242 6. Scope of patent application-a first error correction code decoding device for correcting and correcting the error correction decoding direction of the code in the data block of the error correction code; a first solution A scrambler and an Error Detect Code Check device for reading the main data in the data buffer to perform descrambling and error detection code confirmation actions; a second error correction A code decoding device for performing error correction decoding on the direction of the external code of the error correction code data block; two and third descramblers and error detection code confirmation devices for reading the uncompleted data buffer The main data of the error detection code confirmation action is to perform descrambling and error detection code confirmation action again; and an advanced technology packet connection interface (Advanced TeehnQi Attachment Packet Interfarp ") ^ ^ m Main data, read: The data is slowly output to the host; After the main data is descrambled, the demodulation device will demodulate After the change, the generated block is directly output to the first error correction code data area. The error correction code decoding device performs internal matching only after ^ =, the first decoding, and the first descrambler and error value measurement = towards it. Error correction; if the data is to be decoded for the first time and the error is set, the signal will be descrambled and error detected. Page 35, 2002. 07. 04. 〇35 code processing; and complete the solution of error correction == two error correction Ma solution: state and error detection code confirmation device will pinch the third descrambling The main action of confirming the wrong debt measurement is not yet completed in the buffer zone 540041 __Mjt Q0] 0 ?? A9 _------------------------ 6. Scope of Patent Application The code confirms the action; when the host side needs the main data, the corrected main data is descrambled and transmitted to the host side through the advanced technology packet connection interface device. 4 6 · According to the decoding system described in Item 45 of the scope of patent application, the demodulation device is to demodulate the encoding characters with M channel bits into N (M > N) bits. Information symbol. 4 7 The decoding system as described in item 45 of the scope of patent application, wherein the first error correction code decoding device and the second error correction code decoding device may be Reed Sollo product codes (Reed Sol. m〇n Product Code) decoding algorithm architecture. 4 8. The decoding system as described in item 45 of the scope of patent application, wherein the data buffer area can be SRAM, DRAM, SL-DRAM, DR-DRAM, EDO-DRAM, SDRAM, DDR-SDRAM, VOSDRAM and other memories. 49. The decoding system as described in item 45 of the patent application scope, wherein the first descrambler and the error detection code confirmation device include an error detection code register to store the first and second errors The detection code confirms the result of the action. 5 0 · —A method for decoding a disc, which is used to receive the message data of a disc and perform a decoding action. The decoding method includes: (1) reading the message data of the disc to a demodulation device, the The demodulation device performs the demodulation operation on the message data to generate an Error Correction Code data block, where the error correction code data block includes a main data, an internal parity code (Parity 〇f inner —code (pi) and a parity 〇f Outer-code (P0); Page 36. 2002. 07. 04. 036 540041 Case No. 90102242 6. Scope of patent application (2) Device for transmitting the error correction code data; 卄 £ Block to-First error correction code decoding (3)-First error correction Code decoding-code verification confirmation (Err〇r Detectión CQd, \ Brother-descramble and error detection internal correction Ma direction error correction C02 Che: k) action to synchronize the confirmation action; De-mapping, descrambling and error detection code (4) Write the data block of the error correction code to a data buffer. (5) Read the neighbors inside and outside the data buffer " ^ ^ ^ ny The error correction code in the code direction ", Pingui to Yidi Er error correction code decoding device, to perform external correction code direction error correction decoding; (6) Read the data buffer has not completed the error test The main contribution of the code confirmation operation is to a third descrambler and error detection code confirmation device, and the descrambling and error detection code confirmation operations are performed again; and (7) the data buffer has been corrected to read the data. Pass the main information to an advanced technology packet connection Surface (Advanced Techn〇i〇gy Attachment Packet Interface) device 'and outputs to the host after the descrambling key information. -5 1 · The decoding method as described in item 50 of the scope of patent application, wherein the demodulation and conversion device demodulates the coded characters with M channel bits into N (M > N) bits of data symbol. 5 2 · The decoding method described in item 50 of the scope of patent application, wherein the first error correction code decoding device and the second error correction code decoding device may be Reeds-Solomon product codes (reeds ο 1 〇 m ο η P r duct Co)). Page 37 2002.07.04.037 540041 53. The decoding method described in item 50 of the scope of patent application, wherein the data buffer can be SRAM, DRAM, SL-DRAM, DR-DRAM, EDO-DRAM, SDRAM, DDR -SDRAM, VC-SDRAM and other memory. 5 = The decoding method as described in item 50 of the scope of the patent application, wherein the Xidi player device and the error front horse confirmation device include an error second brother-. . Μ stores the first and second error detection codes:: Stores the results.