JPS58111539A - Error correcting method - Google Patents

Abstract

PURPOSE:To process efficiently signals, by providing pointers which correct and represent errors if a block has errors of a prescribed word and bit after classifying the error in response to the error bit number and discriminating the pointers at the next stage. CONSTITUTION:Two-word error correction is executed at the decoder of the prestage, and a plurality (P1, P2, P3) of error pointers to bits constituting the word are provided, an error discriminating code is given to the error pointers, and error correction is done at the decoder of the next stage by using the error pointers. First, the decoder of the next stage discriminates error bits by using a parity syndrome Sp and the number of error pointers P1, P2 and P3 included in bits of one word unit are counted. The error correction is classified through the number of errors, and based on the range of error correction represented with the parity syndrome Sp, the error correction is executed by using the error pointers P1-P3.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an error correction method 1 which has a high error correction ability even for irregular burst errors and random errors, and reduces the risk of missing error detection or performing erroneous correction. /CaI, in particular, relates to an error correction method that may be a word-by-word or bit-by-bit correction method.

The applicant of the present application has previously proposed a method called cross interleave as a data transmission method effective against burst errors. This generates a first check word sequence as a data bit sequence by supplying one word and one bit included in each of the PCM data sequences of a plurality of channels in a first array IIK to a first error correction encoder. Then, the first check word series, check bit series, PCM data series of multiple channels, and data bit series are put into a second arrangement state, and one word and one bit contained in each are subjected to second process 2-correction. A second check word sequence and a check bit sequence are generated by supplying the second check word sequence and check bit sequence to the encoder, and double interleaving (sequence change) is performed on a word-by-word and bit-by-bit basis.

Interleaving, when the check words, check bits and PCM data included in a common error correction block are distributed and transmitted, and returned to the original arrangement on the receiving side, the count word included in the common error correction block, This is intended to reduce the number of error words and error bits among multiple bits. In other words, when a burst error occurs during transmission, this burst error can be dispersed. If such interleaving is performed twice, the first and second check words and check bits each constitute a separate error correction block, so it is not possible to correct an error in either the check word or the check bit. Even when the error is corrected using the other one, the error correction ability can be further improved. By the way, especially in the case of the word-based correction method, if even one bit in the σ1 word is incorrect, the whole word is treated as being incorrect, so when dealing with received data that has a relatively large number of random errors, It cannot be said that the error correction ability is necessarily sufficient.

Therefore, it is possible to correct words, K bits, for example 2 words, 2-12 bit errors, in one block, and when the error location is known, M words, M bits, for example 3 word errors, 3 bit errors or 4 word errors. , 4-bit errors can also be corrected (of course, if the error location is truly known using the bit-by-bit correction method, it can be corrected by simply inverting the bit).
=r-do-S) in combination with the multiple interleaving described above. Also, this error correction code has 1 word error, 1
When only bit errors are to be corrected, there is an S characteristic that can be easily obtained depending on the configuration of the encoder.

Also, when performing the first stage code for the second error correction block, then returning to the first arrangement state, and then performing the next stage numbering for the first error correction block a, the first stage code is used for the first stage code. 〉 - When one missed detection or one correction occurs, this oversight or incorrect correction becomes a factor for new oversights or incorrect corrections in the next stage. The risk of this occurring increases.

In the present invention, in the first stage number, for example, up to two word errors and two pit errors are corrected, and in the case of a bit-by-bit correction method, for example, in the case of a bit-by-bit correction method, the first stage number indicates that 2 or more bits in each word are 1. When an error is detected, a pointer indicating that there is an error is added to each word and each bit included in the block, and the state of this pointer is determined in the next stage of decoding. This prevents the risk of overlooking errors in column numbers and making incorrect corrections. In this way, the possibility of missed errors and incorrect corrections during error detection and correction is reduced, and problems such as abnormal noises caused by incorrect corrections are avoided when transmitting audio PCM signals, for example. It's resolved.

First, an example of a word-by-word correction method for the error correction code used in the present invention will be explained between stations.

When describing the vA correction code, an vector representation or a cyclic group representation is used. First, consider an irreducible m-th degree polynomial F on G P (2). @02 and “
In the body GF (2) which is harmful and only harmful to the origin of 1",
The irreducible polynomial F k) has no roots, so (F(
Consider a tentative root α that satisfies x)=0).

At this time, 2m different elements 0. α, α2. α3・・・・・・α2
m-1 constitutes an extended field GF (2m). GF (2
m) u, G F (to m-th order irreducible polynomial iF over (2))
It is a polynomial with modulus . The origin of GF (2°) is 1.
α=(X).

α2 = (x2), ......, α! n-1
= n-1 = (can be created by a linear combination of
+a1α+a2-+ ”=-・+ ant-1α%'
r go (ILm-1j am-v *・・・・・・
...*&2*lLl*aQ) Here, a6. al
* ・・・・・・-* am-I CGF (2).

- As an example, considering GF(2), (modF(X)
: x8+x'+x3+x"+1) All A8 pit data is a7x7 +a15x6+a5xl+a4x4+a3x
3+a2x2+al x-1-a.

or (&7-&6s&5*&4**3.a1m&1-&
6), so for example, move a7 to MOB@,
Assign IQ to LSB @, jLyl, G F (
Since it belongs to 21K, it is 0 minus 1.

Further, a T1 matrix T of (m x m ) is derived from the polynomial F (x).

Another way to express it is to use a cyclic group.

This utilizes the fact that the remaining elements, excluding the 0 element from GF(2m), form a multiplicative group of order 2rn-1.

If we express the element of GF(2m) using a cyclic group, we get
・ □ 0 * 1 (= α2m-”), α, α2.a
3. Fist @ @ (12m-2.

Now, in one example of the present invention, m pits are one word, and n
When one block is composed of words, 4m check words are generated based on the 9-ity check matrix H shown below.

Additionally, the ``Tee check matrix H'' can be similarly expressed using the matrix TK.

However, 1 is a unit matrix of (m x m).

) As mentioned above, both the expression using the % root α and the expression using the generator matrix T are essentially the same.

Furthermore, if we take as an example the case where four (k=4) check words are used, the no-ity check matrix H is as follows. One block of received data is converted into a vector ■=(W, W
@@*@−, W□, W. ) (However, W1=W1+e
i.

n-1n-2' el: error amount turn), then 4 occurring on the receiving side
Syndom a - 8 (1, Sl, 82 +831d
This error correction code can correct up to two word errors in one error correction block, and can correct three or four word errors when the error location is known. be.

4111 check words (p'=w3
.

q = W2, r = W1, s = WO). This check word is obtained by K as shown below. However, Σke? It means Σ1.

1”4 If we omit the calculation process and only show the results, becomes. In this way, check word p=q.

The role of the encoder provided on the transmitting side is to form r and s.

Next, we will explain the basic algorithm for error correction when data containing check words formed as described above is transmitted and received.

[1] When there is no error: So = St == 8
2=83 =0(2) 1 word error (error turn el and f; Er) ノAle: 5o=ei
St=α'el 52=a"elSs=cE"e
It is possible to determine whether a one-word error has occurred by checking whether the above relationship holds when changing l and n and l sequentially. Alternatively, 5lBx 8s -=-=x ++-y=αl ao St 8g , and the error location 1 can be found by comparing the turn of α1 with that stored in ROMKt' in advance. Syndrome S1 at that time is error mother turn e! Become that.

[3] In the case of 2-word Neller (ei, ej) If the above formula holds true, it is determined that there is a 2-word error, and the work 2-pattern at that time is (4) 3 '7- Yx Shiller ei , ej, ek
) cD If we transform the above equation, we get aj (8o+8t for α)+(aksx+sz)=(
aL+aj) (cc'+czk) eiaj (81+ for α
82 )+(aks*-+-5s)=ai(a1+aj
)(a=k)et From the above formula, αl(aj(αkS o+81 )+(81+8g for α)
))-aj(αkS1+82)+(αkS2+83) If the following holds true, it can be determined that there is a 3-word error. however,(
The condition is that 8o (0, Sx? 0.8x? 0). At that time, 6 k 2 -/ri 1 is calculated as follows. In reality, if the rounding configuration for correcting a 3-word error is 1/2 rough, the time contributing to the correction operation will also be longer.

So i, j, k by pointer.

In combination with the case where the error location in 2 is known,
It is practical to use the above equation for checking at that time and perform an error correction operation.

(5) 417-P! Rah (ei, ej, ek, e
j) Case O: If the above formula is expressed as desired, the error location (i, j*ksf
fi) is known, error correction can be performed by the above-mentioned calculation.

The basic error correction algorithm described above uses syndrome 8o-8s to check whether there is an error in the first step, check whether there is a one-word error in the second step, and check whether there is a two-word error in the third step. When trying to correct even 2-word errors, it takes a long time to complete all steps, and when determining the location of 2-word errors in %, An intermission occurs. Therefore, an embodiment of a modified algorithm that does not cause such problems and is effective when applying the correction of two words A2- will be discussed.

When considering 2-word correction, the time required for correction must be sufficiently small compared to the data transfer time. For example, 30 bits constitute one word of data, and one
One data block consists of 4 words, and is transmitted serially in units of 1 word, not in units of 1 book.
If the code is to be coded in units of one word and corrections are to be made, it must be done as described above.

Now, in order to shorten the time required for correction, corrections of 2-bit errors or more are not considered, and although errors of 2-bit errors or more are determined, they are not corrected, and the error correction function of the next stage does not consider corrections of 2-bit errors or more. The role of correction is given.

Here, one word consists of 30 bits of data, 12 bits of check bits (nority pit), and 2 bits of error correction. The check matrix is
−, where α is the root of G(2)=0 of the generator polynomial G←)=x+x+1.

Further, an encoder (not shown) provided at the transmitter @ generates 912 check bits (14 retibits) from the parity check matrix H and 30 bits of data.

Assuming that the data bit is 9% and the parity is P, H・(D+
Since P)''=0, the upper 11F12 bits are added to the data bits.

1 word r containing the parity bits generated as above
The basic algorithm for error correction when a is transmitted and received will be explained.

One word of the received data is expressed as a column vector V = (W41°. However, if the error pattern is ei, then Wi = Wi
It is 10e1.

If there is no cr]xp-: 80=81=0[z]1 word e2- (error pattern is el):
8o+'ei, 81=c! Although the mother turn of eiα1 is stored in advance in a ROM (not shown), the error location -1 can also be determined by comparing it with the mother turn.

[a] 2 bits Z 9- (ei, ej) 0jJ
6th: 5o=a'et+(Ejej, 8x=
a3'ei +c! 3jej So now, 81 Yosh 2 - Find location 1 (ei - ej - 1), S1 = α31 + α3j - α31 + (8o + α1) 3 = S
oα"+88α'+8♂ Soα2 l+34?α'+(8J+8x)=00 billion yo p 8o, Substitute Sl, pattern of α1 (1"1
1-12), the error location 11.12 is found (using ROM).

Therefore, αj (j=hh) is found, and the error location j□, j2 is found.

Alternatively, the error location i1.12 may be determined by storing the pattern formed by ROMK80.81.

(4) 3 vias) or more O: E-9- (ei, ej, ek)
In the case of O, if the error location is determined by using the syndrome 8o and 81, it will be determined that there is no solution (the same is true if the ROM is used to find the pattern formed by the syndromes So and 81, I#), so 3 Errors of bits or more are determined.

As described above, in 2-word error correction, it is possible to correct errors of 3 bits or more, but the processing capacity for error correction is increased.

The following is an example in which one word consisting of 30 bits of data and 12 bits of parity bits is added, and one word of 42 bits constituting simple parity bits is added to this 147-word to perform the next stage of error correction. Busy and suspicious.

(The words that make up the simple parity bits are added on the transmitting side.) The pre-stage coder (not shown) performs the above-mentioned two-word error correction and adds at least two bits to the bits that make up the word. Error pointers of type = (PI, PIP3) are provided, error discrimination codes are given to these error pointers, and the next stage coder (
(not shown), error correction is performed using these error pointers.First, in the next stage decoder, error discrimination is performed using a simple tabit, and each error I ink is detected using this. The corrections used are made as shown in chart 70 of the accompanying drawings.

At the beginning of the flowchart shown in the figure, a blank error pit is determined using the mother stay check syndrome 8p, and along with this, the bits in units of one word '!'! 1
The number of determination signals indicated by each error pointer (the number of determination signals indicated by each error pointer) is counted.

Check out Syndrome 8p of Nomentari Tei, 5p=
In the case of Q, further /intertar P3 is checked, and pointer P
When the number of 3 is O, it is determined that there is no error, and the linter (PI, P2) in that error correction block is cleared (@O
'), if 5p=o and the number of pointers P3 is not 0, then the sum of each l pointer, that is, Pi +P2+P
Check a, and if the sum is 1, Ps =
Since there is an error of 1 or 3 bits or more, the l
Step 2 - Mark all bits in the correction block as errors and interpolate or mute them. On the other hand, if the sum of each of the four inks is not 1, it is possible that the I-interfaces Pg and Px are also set, but the pointer PI - Ps is properly expressed as 8p=O. For example, pointer P3. After making 4 intercopies of the part where P2 stands and leaving it as it is, pre-interpolation or interpolation using average value interpolation % or muting is performed.

This operation may be performed by interpolating or muting even the location where the pointer PI stands, if necessary.

Also check out Nonoritei's Syndrome 8p.
When p#O, the sum of pointers P2 and Pa (P2+P3
), and if the sum is 2 or more, further check pointer P3 and Pa (if 1, pointer P2, copy the point where Pa is standing and enter interpolation or muting. On the other hand, P2 When the sum of and Pa is 2 or more and the pointer P3 is 1, it is checked whether 8p has 3 or more bits set to ``1'', and if it is set, the bit set in pointer P3 is inverted and the pointer Correction is performed using an eraser, and if it is not set, all bits are set to 2-, and interpolation or muting begins.The above steps of checking Pa!ql and correcting Pa using a pointer eraser may be performed as necessary. You can omit it, but it is better to include it when you want to improve your correction ability.

Also, if P2+Ps〉2, then KP20P3=
Check whether it is 1 or not, and if it is 1, P2=1 and S
Fipa determines whether p is 5 bits or more and 11" is set.
= x checks whether 8p is 3 or more bits or not 112 is set, and if it is set, inverts the set bit of pointer P2゜Pa, performs correction using the pointer register, and if not set, all Marks the bit as an error and enters interpolation or muting. On the other hand, when P2+P3''Wl, the following three types of processing are performed depending on the number #i of pointer Pi.In other words, when P1=0, it is determined that the detection by syndrome a is incorrect, and the error occurs. Interpolation or muting is performed by marking all bits in the correction block as errors, and checking whether Pl-1 and *aSp are 5 or more pits @11 is standing, and if so, the pointer is The bit on which P1 is set is inverted and corrected by the pointer register, and if it is not set, all bits are treated as errors, and the circuit enters interpolation or muting.Furthermore, when Pl≧2, pointer P1 is set. Perform interpolation or muting by performing 4 intercopies of the location.

As described above, according to the present invention, the system 2, such as a cross-interleaso type code code, which is based on a counting stage code, can be used.
- When detecting and correcting errors of a predetermined number of words or bits or more in the stage comprising the correction circuit, if there is an error of a predetermined number of words or a predetermined number of bits in each block, it will be corrected and then repaired at Kuue. Since the L-interference indicating 2- is classified and added according to the number of error bits, and the signal processing is performed by determining the number of pointers indicating an error and the error location by the pointer at the next stage, Technique 2 - It is possible to prevent the possibility of one missed detection or erroneous correction, and it is extremely useful especially for systems such as digital audio systems where abnormal noises (click noises) must never be emitted.

[Brief explanation of the drawing]

The attached drawings are diagrams for explaining one embodiment of the present invention. Sp Hanoglyte Check Syndrome, Pl# P2
-P3 is the error main link.

Claims (1)

[Claims] 1. A first information constituent unit consisting of an information unit included in each of the PCM information series in the first column 11 and a first error correction unit therefor; By delaying the information unit of the information constituent unit and the first correction unit by different times, the second information constituent unit in the second array shape K and this the second for
form an information structure from the error correction units of the first and twentieth arrays I! Each information unit in the 13th! and a second error correction unit, in which an initial stage 0 is performed for the second information constituent unit and the second error correction unit to obtain a second arrangement state;
This #2 arrayed static information unit is error-corrected by a second error correction unit, and an error correction instruction unit indicating the presence or absence of error correction and error correction OIi is added, and then the second information configuration unit is Let K be the first information constituent unit of time, and the first information constituent unit of this $1
The number of shellers is detected for a certain information unit by the first correction unit, and the number of shells is calculated using this number of corrections.
An error correction method in which cases of correction are divided, and correction is performed using the Scherer correction instruction unit within the error correction range indicated by the correction instruction unit. 2. The correction method according to claim 1, wherein the correction instruction unit is a bit unit. 3. The error correction method according to claim 1, wherein the correction at the end of # is a bit-by-bit inversion based on the error correction instruction unit or a discard of one information unit. 4. The number of errors in error correction cases was set to 0! The error correction method according to claim 1, wherein #f is small.