TW535291B - Semiconductor device and pattern layout method thereof - Google Patents

Abstract

A semiconductor device and a pattern layout method thereof for promoting a semiconductor device used for driving a driver into a single-chip disposition. Within a driver for driving display device, wherein the driver has anode driver, cathode driver, and memory, the semiconductor device of the present invention uniformly divides anode driver areas 10, 12, 13, 16, which are connected to the memory, within a chip, and uniformly disposes SRAM 18, 19 adjacent to the uniformly divided anode driver areas 10, 12, 13, 16, respectively. As a result, a distribution of circuit becomes easier, and a chip size can be reduced.

Description

535291 V. Description of the Invention (l) —--Technical Field of the Invention] The present invention relates to a semiconductor device and a pattern layout method thereof; more specifically, 'for example, an anode driver and a cathode driver are provided, and the drivers are Figure ^ of a driver for a wafer-shaped display driver, etc., and its pattern layout method. &gt; Sentences [Knowledge] The following description will be made with reference to the drawings on the semiconductor devices constituting the display driver and the like. -The above display includes various flat displays such as an LCD display, an LED display, an organic EL (electrically excited light) display, an inorganic EL display, a pDp (plasma display), a FED (field emission display), and the like. ^ Hereinafter, an organic display device, for example, which has an anode driver and a cathode driver and supplies a plutonium current to the organic element to cause the organic EL element to emit light will be described as an example. In addition, since the EL element is self-luminous, it has many advantages such as no background light required for a liquid crystal display device, and unlimited field angles, so it is expected to be applied to a new-generation liquid crystal display device. In particular, the organic EL element is known to be superior to the inorganic EL element in terms of high efficiency, high response characteristics, and polychromaticity. _ <The driver for organic EL display driving 'is composed of logic N-channel transistor and P-channel MMOS transistor, high-voltage-resistant N-channel transistor and p-channel transistor. Resistive Micro Motion @ = Channel type MGS transistor and 1 &quot; channel type_transistor, and N-channel MMOS transistor for bit shifting. Here, access can be achieved

535291 V. Description of the invention (2) The MOS transistor system with low resistance and high withstand voltage can use D (Double diffused) MOS transistor. The above-mentioned DMOS transistor structure refers to a difference between a diffusion layer formed on a surface end of a semiconductor substrate and diffusion of impurities having different conductivity types to form a new diffusion layer and diffusion of the diffusion layers in a lateral direction. It is constructed by using it as an actual effective channel length, and since it can form a short channel, it is an element suitable for reducing the resistance of the channel. Further, the pattern layout of the semiconductor device when constituting various drivers such as the above-mentioned organic EL display driver is a structure in which a one-bit output layout is repeatedly arranged only with a desired number of outputs. [Problems to be Solved by the Invention] Here, when the driver for driving the organic EL display described above is configured, the anode driver, the cathode driver, and the memory are configured separately. Therefore, when these devices are mounted on a single printed circuit board, they are not satisfactory in terms of cost or size. Therefore, it is expected to reduce the size and cost of the wafer by singulating the anode driver, the cathode driver, and the memory into a single chip. [Means for Solving the Problem] 3 Therefore, the semiconductor device and the pattern layout method of the present invention are those in which the anode driver, the cathode driver, and the memory are formed into a single chip, and are characterized by a desired connection to the memory. The drives are divided equally in the chip, and each memory is evenly arranged at a position near the drives that have been divided equally. Furthermore ', the desired drives connected to the memory are distinguished into

535291 V. Description of the invention (3) Multiple array groups' and arrange each memory in each group. Furthermore, the desired drive connected to the above memory is arranged relatively to the left and right or up and down of the crystal. , And each memory is arranged at the center of the chip. [Embodiments of the Invention] Hereinafter, one embodiment of the semiconductor device and the pattern layout method of the present invention will be described with reference to the drawings. In this embodiment, an example of the display is an organic EL display, and a semiconductor device incorporating various Mos transistors constituting a driver for driving the organic EL display will be described. The driver for the organic EL display is an N-channel type M0S transistor and a p-channel type M0s transistor of a logic system (for example, 3V) from the left side of FIG. 10 (8). N-channel MOS transistor (for example, 30V), N-channel MOS transistor with high withstand voltage type C (for example, 30V), and low resistance can be achieved from the left side of Figure 10 (1)) ^ N-channel MOS transistor with high withstand voltage system (for example, 30v), p-channel type jjos transistor with high withstand voltage system (for example, 30v), and high withstand voltage system that can reduce the resistance of the channel (For example, 30v) is a p-channel MOS transistor. In addition, for convenience of explanation, a distinction is made between the high-withstand-voltage MOS transistor and the high-withstand-voltage MOS transistor that can reduce the resistance of the via. In the following description, the resistance of the via can be reduced. The high-voltage MOS transistor is called SLED (SI it channel by counter doping with extended shallow drain) M0S transistor. Various types of drivers for driving such organic EL displays are incorporated

535291 V. Description of the invention (4) A semiconductor device formed by a MOS transistor, as shown in FIG. 10, makes the P-channel type MOS transistor constituting the above-mentioned high withstand voltage system and the above-mentioned high-resistance path low-resistance high. The N-type well (we 11) 23 of the p-channel type SLEDMOS transistor of the withstand voltage system becomes the high step difference portion, and the p-type well 22 constituting other various jjqs transistors is a low step difference portion. In other words, an N-channel MOS transistor and a p-channel MOS transistor of a micro-logic system (for example, 3 v) are arranged at the lower part of the step. Hereinafter, a method for manufacturing the semiconductor device will be described. First, in the first figure, in order to delineate regions for forming various transistors, for example, in a P-type semiconductor substrate (p-sub) 2l, p-type wells (pf) 22 and N are formed by the LOCOS method. Type well (NW) 23. That is, although illustration is omitted, a bottom pad oxide film and a silicon nitride film are formed on the N-type well formation region of the substrate 21, and the bottom oxide film and the silicon nitride film are used as a mask. An acceleration voltage of about 80 KeV is implanted, for example, with boron ions under an implantation condition of 8 × 10 12 / cm 2 to form an ion implantation layer. Then, using the nitride nitride layer as a mask, field surface oxidation is performed on the substrate surface by the LOCOS method to form a LOCOS film. At this time, boron ions that have been ion-implanted in the LOCOS film formation area will diffuse inside the substrate to form a p-type layer. Secondly, after removing the underlying oxide film and silicon nitride film, using the above-mentioned L0C0S film as a mask, an acceleration voltage of about 80KeV is applied to the substrate surface at an implantation condition of 9x l (F / cm2), for example, phosphorus ion is implanted Implanted on the surface of the substrate 'to form an ion implantation layer. Then, after removing the above-mentioned L0C0S film, each impurity ion implanted in the substrate is thermally diffused to form a P-type well and an N-type well. As shown in Figure 1, it will be formed on the base

535291 The P-type well 22 in the plate 21 is arranged at the low section and the N-type well 23 is arranged at the high section. In FIG. 2, in order to separate the elements in each Mos transistor, an element separation film 24 of about 500 nm is formed by the LOCOS method, and the active region other than the element separation film 24 is used. The thermal oxidation forms a thick gate oxide film 25 for Nancai pressure of about 80 °. Next, using the resist film as a mask, the first low-concentration N-type and P-type source and drain layers (hereinafter referred to as the rLN layer 26 ″ and the rLP layer 27 ″) are formed. That is, first, in a state in which a region other than the LN layer formation region is covered with a resist film (not shown), an acceleration voltage of about 120 KeV is used to implant, for example, phosphorus ions at a implantation condition of 9 x 10 V cm 2. Implanted on the surface of the substrate to form "Layer-26." Then, in a state in which the area outside the Lp layer formation area was covered with a resist film (pR), an acceleration voltage of about 120 KeV was used at 8. 5 χ The implantation conditions of 1012 / cm2, for example, implant boron ions into the surface layer of the substrate to form a "layer." In addition, the annealing step in the subsequent steps is actually performed (for example, under a nitrogen environment of 100,000 ° C for 2 hours). ), And each of the above ion-implanted ion species is thermally diffused to form an LN layer 26 and an LP layer 27. Next, in FIG. 3, in the P-channel type and N-channel type SWLDM0S transistor crystal body formation region Between the formed LN layer 26 and the LP layer 27, a second low-concentration N-type and p-type source and drain layer (hereinafter referred to as "SLN layer 28", "SLP layer 29"). That is, first, in a state in which a region other than the SLN layer formation region is covered with an antimoney film not shown, an acceleration voltage of about 120KeV is used to implant, for example, an ion implanter under an implantation condition of 1 · 5 × 1012 / cm2. Into the surface layer of the substrate to form a

313373.ptd Page 9 535291 V. Description of the invention (6) SLN layer 28. Then, in a state where a region outside the SLp layer formation region is covered with a resist film (pr), a boron difluoride ion (for example, boron difluoride ions ( 49 胂 2+) is implanted on the surface layer of the substrate to form an SLP layer 29 connected to the LP layer 27. In addition, the impurity concentrations of the LN layer 26 and the SLN layer 28, or the LP layer 27 and the SLP layer 29 may be set to be substantially equal, or the concentration of either of them may be set to be south. Furthermore, in FIG. 4, the N-type and P-type source and drain layers (hereinafter referred to as “r layer 3 0” and “ρ + layer 3 1”) are formed with a high concentration using the resist film as a mask. ) ° That is, first, in a state in which a region other than the N + layer formation region is covered with a resist film (not shown), an acceleration voltage of about 80 KeV is used to implant, for example, phosphorus ions at an implantation condition of 2 X 1015 / cm2. It is implanted on the surface layer of the substrate to form an N + layer 30. Then, in a state in which a region outside the P + layer formation region is covered with a resist film (PR), a boron difluoride ion is implanted under an implantation condition of 2 X 1 015 / cm2 using an acceleration voltage of about 14 KeV. It is implanted on the surface layer of the substrate to form a P + layer 31. Next, in FIG. 5, a resist film having an opening diameter smaller than the opening diameter of the mask for forming the SLN layer 28 and the SLP layer 29 (see FIG. 3) is used as a mask. A central portion of the SLN layer 28 of the LN layer 26 and a central portion of the SLP layer 29 connected to the LP layer 27 are ion implanted with a reverse conductivity type impurity, thereby forming a barrier between the SLN layer 28 and the SLP layer 29. The P-type body layer 32 and the N-type body layer 33. That is, first, in a state in which a region other than the p-type layer formation region is covered with a resist film (not shown), an acceleration voltage of about 120 KeV is used, and an example of implantation conditions of 5 × 1 (F / cm2) is used.

313373, ptd page 10 535291 V. Description of the invention (7) The factory boron ions are implanted on the surface of the substrate to form a p-type body layer 32. However, 'in a state in which a region other than the N-type layer forming region is covered with a money-resistant film (PR)', an acceleration voltage of about 190 KeV is used to implant, for example, phosphorus ions at an implantation condition of 5 × 10 2 / cm 2. An N-type body layer is formed on the surface of the substrate. In addition, the “operating procedure regarding the ion implantation steps shown in FIG. 3 to FIG. 5 above” can be appropriately changed, and the P-type body layer 32 and the N-type body layer can be appropriately changed. The surface layer portion of the body layer 33 may constitute a channel. Furthermore, as shown in FIG. 6, a second P-type well (SPff) is formed in the substrate (p-type well 22) of the above-mentioned miniaturized n-channel and P-channel MOS transistor formation region for normal withstand voltage. 34 and second N-well (SNW) 35. That is, first, a resist film (not shown) having an opening in the N-channel type MOS transistor formation region for the above-mentioned withstand voltage is used as a mask, and an acceleration voltage of about 190KeV is used at 1.5x 1 ( First implantation condition of p / cm2 After, for example, boron ions are implanted in the P-type well 22, the second implantation is performed at a rate of about 2 · 6 X 1 〇12 / cm2 using an acceleration voltage of about 50 KeV. Under conditions, boron ions are implanted to form a second P-type well 34. Then, using an anti-surname agent film (pR) having an opening in the above-mentioned p-channel MOS transistor formation region for general withstand voltage as a mask, With an acceleration voltage of 380KeV, for example, phosphorus ions are implanted in the P-type well 22 above under the implantation condition of ux 10i3 / cm2 to form a second n-type well 35. In addition, there is no high acceleration M0S of about 380KeV In the case of a transistor voltage generating device, a double charging method that uses an acceleration voltage of about 190KeV and implants divalent phosphorus ions at an implantation condition of 1 · 5 X 1013 / cm2 can be used. Then, about 140KeV is used. Phosphorus ions were implanted at an accelerating voltage of 4.00 × 1012 / cm2.

313373.ptd

^ 5291 Five 'Invention Note (8)' '1 -------Formation of ϊ ^ The 1-channel type commonly used for withstand voltage is attached to the p-channel surface s transistor, and the N-channel for level shifting After the gate oxide film 25 of the type MOS transistor is formed and the gate oxide film 25 is removed, as shown in FIG. 7, a gate oxide film of a desired film thickness is additionally formed on the w region. Also, P first uses thermal oxidation to form an N-channel type MOS transistor for use at a level of about 14 nm (at this stage, although it is about 7 nm, ', but the gate for general heat resistance described later When the oxide film is formed, the thickness of the gate oxide film is 5). Next, the gate oxide film 36 of the N-channel-type MOS transistor and the channel-type MOS transistor formed on the ν channel-type and channel-type MOS transistor formation region for normal withstand voltage are removed, and then thermally oxidized there. A thin gate oxide film 37 (approximately 7 nm or so) which is usually used for withstand voltage is formed in the region. Then, in FIG. 8, a polycrystalline stone film of about 100 nm is completely formed, and POC 13 is used as a thermal diffusion source, and then the polycrystalline silicon layer is thermally diffused and electrically conductive. On the ε film, approximately 1 q qηιη of the Shixi Chemical Crane film and about 150 nm silicon dioxide film are laminated, and then an anti-emuth agent film (not shown) is patterned to form a gate for each MOS transistor. Pole 38A, 38B, 38C, 38D, 38E, 38F, 38G. In addition, the above silica dioxide film can be used as a hard mask during patterning. 'Next, in FIG. 9, the low-concentration source and drain layers for the above-mentioned 1 ^ channel type and P channel type MOS transistor for general withstand voltage are formed. ^

That is, first, a non-residual agent film covering a low-concentration source and a region other than the drain layer formation region for an N-channel type MOS transistor for general withstand voltage is used as a mask. K e V acceleration voltage to 6.2 X

535291 V. Description of the invention (9) _ 1 013 / cm2 Implantation conditions For example, after implantation of phosphorus ions, a low-concentration N-type source and drain layer 39 is formed. Then, a money-repellent film (PR) covering a region other than the low-concentration source and drain layer formation region for the p-channel MOS transistor for general withstand voltage is used as a mask, using about 205 ^ ¥ For example, a boron difluoride ion is implanted under an implantation condition of 2 × 10 3 / cm 2 at an accelerating voltage to form a low-concentration P-type source and source layer 40. Furthermore, in FIG. 10, the above-mentioned gates 38A, 38B, 38C, 38D, 38E, 38F, and 38G are covered by the LPCVD method to form a film 41 with a thickness of about 250 nm. The n-channel and p-channel MOS transistor formation regions for the above-mentioned withstand voltages have an opening resist film (PR) as a mask, and anisotropic etching is performed on the 71:08 film 41. Thereby, as shown in FIG. 10, a sidewall diaphragm 41A is formed on the two sidewall portions of the gate electrodes 38A and 38B, and a TEOS film 41 remains in a region covered by the resist film (pR). . Then, using the above-mentioned gate electrode 38A and sidewall diaphragm 41A, and the above-mentioned gate electrode 38B and sidewall diaphragm 41 A as a mask, the above-mentioned high-concentration N-channel and P-channel MOS transistors are used to form a high concentration. Source and drain layers. That is, to cover the non-illustrated impedances in the areas other than the areas for forming the source layer and the electrode layer of the N-channel type MOS transistor for general withstand voltage: the film is a mask, With an acceleration voltage of about 100 KeV, for example, arsenic ions are implanted under an implantation condition of 5 × 10 U / cm 2 to form a high-concentration source-type and drain-layer. Then, a non-illustrated resist film covering a region other than the p-channel-type μ-channel source for general withstand voltage and the drain layer formation region is used as a mask, and approximately 40KeV is used. Acceleration voltage to 2χ

313373.ptd Page 13 535291 V. Description of the invention The implantation conditions of 1 015 / cm2 are implanted with boron difluoride ions, for example, to form a high-concentration P + -type source and source layer 43. The illustration below is omitted, and the interlayer insulation of about 60 nm, which is composed of a TE0S film and a bpsg film, is fully formed, and then the high-concentration source and drain layers 30, 31, and 42 described above are formed. The gold layer connected with 43 contacts can complete the N-channel MOS transistor and P-channel Mos transistor used for constituting the above-mentioned driver for the display drive, and the N-channel MOS transistor for level movement. Crystal, N-channel type Gu transistor for high withstand voltage _ Tong Xiao MOS transistor, and N-channel SLEDMOS transistor and P-channel SLEDM0s transistor for high withstand voltage that can achieve low resistance of the channel. The present invention is characterized in that a constant current is supplied to a display driving driver such as an organic EL element (organic electroluminescent element), and in a display driving driver or the like that emits an organic EL element, an anode driver is used in winter. , Cathode driver, storage display: and the controller and a single chip to transform it into a single chip Γ e body U Ri Nai is a highly efficient pattern layout method. In the following, a brief description of the present invention is provided. The simplified layout of the pattern layout structure is shown in Figure 11 (a). The anode driver body and the controller are listed separately—say u ^ ^ w ^ ^ From the upper left, 32-bit From the cathode of 128-bit U (a) drawing (* use: C0M) ^ driver area 10, device area 13, and Ηbit image are positive: 32-bit anode drive Polar driver area 14, 10-bit 535291

Anode driver area for image 丨 5, 32-bit anode γ goes to 1 70 for the driver area 16: 'Each driver area is required to repeatedly distribute the output area of 1 bit 70 copies only with the required output amount Turn out of the field; turn out the bits. Then, the desired round is formed. Then, through the other logic (LOG 1C) section 17, at the position of the toilet section B: (in this embodiment, although it is a left and right pair; piece: can be equipped with a chip It is arranged vertically and symmetrically inside), with SRAM (static RAM) 18, 19 of the memory, and from the ^^^ output wiring 20, which are connected to the anode driver areas i0, i2, U '", 1 6 〇

In the present invention, the anode driver connected to the SRAM is arranged with four corners in the chip, and the anode driver regions 10, 12, 2, and '16 are combined, and the SRAM is divided into &amp; The anode driver area 1 (groups of 3 and 13) on the left end of the wafer and the anode driver areas 12 and 16 arranged on the right end of the wafer correspond to each other, thereby making the pull wire of the wiring 20 more flexible. easily.

^ That is, a comparison between the structure of the conventional knowledge (Fig. 12) and the structure of Fig. 11 (a) is described above. As shown in Fig. 12, when the output pads corresponding to all the drivers are When arranged in a row in the chip, because the wiring 3 is pulled from the memory 2 arranged at a position to each output seat 1, the drawing space of the wiring 3 (the area surrounded by the circle on the way) is needed. The circle size will increase the size of this section. In contrast, in the present invention, as shown in FIG. 11 (a), a driver (anode driver in this embodiment) connected to the SRAM is arranged in

313373, ptd Page 15 535291 V. Description of the invention (12) The four corners in the wafer are combined with each anode driver area 10, 1, 2, 13, 16, and the SRAM is divided into two because each anode driver area 10 , 12, 13, 16 and the SRAM 18, 19 form the wiring 20, so that the space for drawing wires can be reduced. Furthermore, the structure shown in Fig. 11 (b) is compared with the structure shown in Fig. Ii (a), and the structure shown in Fig. 11 (b) is similar to the structure shown in Fig. 11 (a). Generally, the drivers connected to the SRAM (anode drivers in this embodiment) are arranged at four corners in the wafer, because the SRAMs (18, 18, 12, 13 and 16) connected to the anode driving regions 10, 12, 13, and 16 are connected. 19) with

It is placed in one position '. Therefore, although the wiring space of the wiring 20 is smaller than the structure shown in FIG. 2 and FIG. 2, it is larger than the structure shown in FIG. 1 i (b). Furthermore, because the wiring length of the structure shown in Fig. 11 (a) is also left-right symmetrical, compared with the structures shown in Fig. 11 (1)) and Fig. 12, the influence of impedance can be reduced, and Can suppress uneven display. As described above, when a driver for a hungry display driver having, for example, an anode driver, a cathode driver, a memory M, or a controller is formed into a chip earlier, the body is divided into two because The length of the pull wire when connecting the driver to the driver will be shorter, so the size of the chip is reduced and the cost can be reduced.

"Lear cry" "In this embodiment, although the anodes connected to the memory are moved in the time zone, 10, 12, 13, and 16 are evenly arranged at the four corners of the wafer and the anode driver areas 10, 12, and 1 η ^ ν. And in a manner corresponding to each group: two two are divided into two groups' ”⑴, but can be further subdivided. The hidden body is divided into two (Guan 18,

535291 V. Description of the invention (13) Furthermore, in this embodiment, the display system is described with reference to its driving driver, for example, LCD display, LED display, PDP-free (plasma display), FED (Field emission display) can be used for driving. [Effects of the Invention] According to the present invention, when a display driving driver having an anode driver memory is connected to a driver region of a single crystal and a memory body, the driver regions are uniformly divided in the chip to separate the memory and the driver. The wiring between the drivers becomes easier. The wiring length will be shorter, so the wafer scale can be exemplified as an organic EL display. However, the present invention is not limited to organic EL displays, special flat displays, cathode drivers, and wafers. By dividing evenly and correspondingly dividing the configuration, the memory can be reduced and the size of the memory can be reduced. I side

313373.ptd Page 17 535291 Brief description of drawings [Simplified description of drawings] Figures 1 (a) and (b) are cross-sectional views of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figures 2 (a) and (b) are cross-sectional views of a method of manufacturing a semiconductor device according to an embodiment of the present invention. Figures 3 (a) and (b) are cross-sectional views of a method of manufacturing a semiconductor device according to an embodiment of the present invention. 4 (a) and (b) are cross-sectional views of a method of manufacturing a semiconductor device according to an embodiment of the present invention. Figures 5 (a) and (b) are cross-sectional views of a method of manufacturing a semiconductor device according to an embodiment of the present invention. Figures 6 (a) and (b) are cross-sectional views of a method of manufacturing a semiconductor device according to an embodiment of the present invention. Figures 7 (a) and (b) are cross-sectional views of a method of manufacturing a semiconductor device according to an embodiment of the present invention. 8 (a) and (b) are cross-sectional views of a method of manufacturing a semiconductor device according to an embodiment of the present invention. Figures 9 (a) and (b) are cross-sectional views of a method of manufacturing a semiconductor device according to an embodiment of the present invention. Figures 10 (a) and (b) are cross-sectional views of a method of manufacturing a semiconductor device according to an embodiment of the present invention. Figures 11 (a) and (b) are top views of the pattern layout of a semiconductor device according to an embodiment of the present invention. FIG. 12 is a plan view of a pattern layout of a conventional semiconductor device.

313373, ptd Page 18 535291 Simple explanation of components [Description of component symbols] 1 Output socket 2 Memory 3 Wiring 10, 12, 13, 13 6 Anode driver area 11 Cathode driver area 14, 15 Image anode driver area 17 Logic Part 18 &gt; 19 SRAM 20 Output wiring 21 Substrate 22 P-well 23 N-well 24 Element separation film 25 &gt; 36 &gt; 37 Gate oxide film 26 LN layer 27 LP layer 28 SLN layer 29 SLP layer 30 N + layer 31 P + layer 32 P-type body layer 33 N-type body layer 34 Second P-type well 35 Second N-type well 39, 42 N-type source, drain layer 40, 43 P-type source, source layer 41 TEOS Membrane 41A sidewall diaphragm 38A, 38B, 38C, 38D, 38E, 38F, 38G gate

❿ 313373.ptd Page 19

Claims (1)

535291 6. Scope of patent application h A semiconductor device and memory shall be equally divided from the above, and each configuration shall be equally distributed. 2 · As configured in the group connected to the patent application memory. 3 · As the patent application application and the above Memorize the center of left and right or upper and lower films. 4. The pattern layout of a semiconductor-mounted cathode driver will be divided equally from the above, and each of them will be equally arranged. 5 If the patent application is applied, it will be the same as the above complex array, and 6 'Built in the wafer, the anode driver, the cathode driver, and the semiconductor wafer in a single wafer are set. It is characterized by the desired driver connected to the body, attached to the driver and equally divided on the wafer. Memory. The semiconductor device according to item 1, wherein the driver differing from the memory is divided into a complex array group and each memory. In the semiconductor device surrounding item 1 or item 2, the desired driver connected to the body is arranged in the chip "inside facing" and the memory is arranged in a pattern. "The layout method" refers to the anode The driver and the memory are strictly μ, and the semiconductor mounting method based on an early Japanese chip is characterized as follows: The desired driver is connected in the vicinity of the chip and each driver that has been specifically divided. Memory. The pattern layout method of the semiconductor device and the device of the fourth item, 1 The desired driver is divided into the memory arranged in the parent group. The fourth and fifth items of the ^^^ u The upper and lower positions of the pattern cloth of the cow's conductor device ^ and the desired drive connected by the redundant memory are arranged opposite to each other, and each 313373, ptd 535291 6. Scope of patent application The memory is arranged in the central part of the chip. 313373.ptd Page 21