533572 A7 B7533572 A7 B7
五、發明説明（） 發明領域： (請先閲讀背面之注意事項再填寫本頁) 本發明係有關於一種重新分佈層（re-distribution layer ; RDL)之結構及其製程，特別是有關於一種在重新分 佈層之介層洞中具有平滑的間隙壁（spacer)結構之重新分 佈層之結構及其製程。 發明背景： 覆晶（flip-chip)技術是可使整體封裝尺寸更加緊密之 先進半導體製造技術。覆晶技術不同於傳統的封裝技術， 特別是在於覆晶技術係將晶片以上表面向下的方式覆蓋在 晶片載具上，且藉著晶片表面上的銲料凸塊電性連接至晶 片載具。由於並不需要會佔據大量空間的銲線，因此覆晶 封裝的整體尺寸與傳統的半導體元件之封裝比較之下，顯 得緊密許多。 在覆晶技術之晶片上形成銲料凸塊前，需先形成凸塊 下金屬層（under bump metallization ; UBM)於半導體晶片的 經濟部智慧財產局員工消費合作社印製 表面上。此凸塊下金屬層在形成輝料凸塊的過程中可炫成 液體，藉以使銲料凸塊可牢固地黏合至晶片上。 上述覆晶技術中的凸塊下金屬層之習知範例之一係為 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 533572 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（） 二層式結構。此二層式結構中的底層之材質例如可為鋁， 中間層之材質例如可為鎳—釩合金，以及頂層之材質例如 可為銅。然而，此材質例如可為鋁/鎳一釩合金/銅之三層式 金屬結構會導致製造上的問題。此問題係產生於當具有1 述三層式凸塊下金屬層的晶片被用來在晶片上的周圍之眾 多間距約小於70μιη(通常為約6〇μιη或約5〇μιη)之介層洞上 形成電路探測接觸點（circuit pr〇bing c〇ntact p〇int)時:此 製造上的問題可參考第1圖。 第1圖係繪不習知重新分佈層之上視圖。在每兩個介 層洞11間的間距約小於70μιη的情況下，這些間距約小介 7〇μιη之介層洞U即不適合用於後續銲料凸塊之黏2於 程，因為銲料凸塊的尺寸遠大於上述間距，導致相鄰的， 料凸塊間會彼此互相接觸。因此，為了解決此一問題、 層洞1 1可藉由重新分佈層12重新分佈至凸塊下金屬層= 請參考第2圖所繪示之習知重新分佈層之 結播 圖。在此第2圖中，重新分佈層丨2進一步包括重 之介電層14與重新分佈層之金屬層16。此外，曰 ^此第2圖 中更包括上金屬層20、蝕刻中止層30、護層4〇、 a ' 凸塊下 金屬層50、以及銲料凸塊60等。護層40係覆甚认 ’、產於部分的 重新分佈層之金屬層16上。凸塊下金屬層5〇則灣_ 、復盍於部 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) ...........«^.......、|叮 f請先閱讀背面之注意事Js再填寫本頁j « ^3572 趣裨部智慧財產局員工消費合作社印製 A7 B7 i'發明説明（） 分的重新分佈層之金屬層16上與部分的護層40上，藉以 使銲·料凸塊6 0可牢固地黏合至晶片上。此重新分佈層1 2 之結構使半導體基材10的内部電路可經由上金屬層20、 重新分佈層之金屬層16、凸塊下金屬層50、以及銲料凸塊 60等之導電路徑電性連接至外部之印刷電路板（未繪示）。 對於南速的類比應用而言，重新分佈層之介電層1 4必 須具有例如約為3 μ m之較大的高度，且介層洞1 1必須具 有例如約為1之高寬比（aspect ratio)，方能降低訊號干擾之 現象。然而，若重新分佈層之介電層1 4具有較大的高度， 則會在如此高的介層洞1 1中導致如第2圖中所示之較差的 階梯覆蓋（step coverage)效果。階梯覆蓋的定義為寬度8〇 除以南度90。方南度90保持不變，則當寬度8〇愈大時 階梯覆蓋的數值隨之愈大’即代表階梯覆蓋的效果較好。 反之，若高度90保持不變，則當寬度80愈小時，即代表 階梯覆蓋的效果較差。此外，若寬度80小至在介層洞^ i 中幾乎形成斷路，則代表此處具有很大的接觸電阻，進— 步會導致元件的可信賴度大幅降低。因此，有必要尋求解 決之道。 發明目的及概述： 鑒於上述發明背景中，習知重新分佈層結構之缺點。 4 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐） •-----------·裝--------訂 (請先閲讀背面之注意事項再填寫本頁) _ 533572 A7 B7 五、發明説明（） 因此本發a月之一目的為提供一種重新分佈層之結構及其製 程，可用以改善重新分佈層之介層中階梯覆蓋之效果。 (請先閲讀背面之注意事項再填寫本頁) 本發明之另一目的為提供一種重新分佈層之結構及其 製程，可用以降低重新分佈層中介層之接觸電阻。 本發明之又一目的為提供一種重新分佈層之結構及其 製程，可用以提高元件之可信賴度。 依據本發明之上述目的，因此本發明提供一種重新分 佈層之結構，至少包括：半導體基材，具有上金屬層；重 新分佈層之介電層，覆蓋半導體基材，且重新分佈層之介 電層中具有介層洞，其中此介層洞貫穿重新分佈層之介電 層，且此介層洞與上金屬層相連接；間隙壁，位於介層洞 之側壁；以及重新分佈層之金屬層，覆蓋部分之上金屬層、 間隙壁、以及重新分佈層之介電層。 經濟部智慧財產局員工消費合作社印製 依據本發明之上述目的，因此本發明另提供一種重新 分佈層之製程，至少包括下列步驟：首先，提供具有上金 屬層之半導體基材，其中上金屬層之上表面係為半導體基 材之部分上表面；接著，形成蝕刻中止層，覆蓋半導體基 材；接著，形成重新分佈層之介電層，覆蓋蝕刻中止層； 接著，去除部分之重新分佈層之介電層與部分之蝕刻中止 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐) 533572 A7 B7 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 層，藉以形成介層洞，且約暴露出部分之上金屬層；接著， 形成間隙壁薄膜，覆蓋重新分佈層之介電層以及約暴露出 之部分上金屬層，其中位於介層洞之側壁上之間隙壁薄膜 係為弧形，且具有第一高度；接著，去除部分之間隙壁薄 膜，藉以約暴露出重新分佈層之介電層之上表面與部分之 上金屬層，且位於介層洞之側壁上之間隙壁薄膜形成間隙 壁，但此間隙壁具有第二高度，其中第二高度約小於第一 高度；然後，形成重新分佈層之金屬層，覆蓋部分之上金 屬層、間隙壁、以及重新分佈層之介電層。 圖式簡單說明： 本發明的較佳實施例將於往後之說明文字中辅以下列 圖示做更詳細的闡述，其中： 第1圖係繪示習知重新分佈層結構之上視圖； 第2圖係繪示習知重新分佈層之剖面結構圖； 第3圖係繪示本發明之一較佳實施例之重新分佈層之 剖面結構圖；以及 經濟部智慧財產局員工消費合作社印製 第4A圖至第4E圖係繪示本發明之一較佳實施例之重 新分佈層之製程之結構剖面圖。 圖號對照說明： 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐) 533572 A7 B7 五、發明説明（） 經濟部智慧財產局員工消費合作社印製 10 半 導 體 基材 11 介層洞 12 重 新 分 佈層 14 重新分佈層之介電層 16 重 新 分 佈層 之金屬層 20 上金屬層 30 蝕 刻 中 止層 40 護層 50 凸 塊 下 金屬 層 60 桿料凸塊 80 寬 度 90 南度 1 10 半 導 體 基材 111 介層洞 1 14 重 新 分 佈層 之介電層 1 16 重新分佈層之金屬層 120 上 金 屬 層 130 蝕刻中止層 140 護 層 150 凸塊下金屬層 160 辉 料 凸 塊 165 間隙壁薄膜 170 間 隙 壁 180 第一高度 190 第 二 南 度 1 12 重新分佈層 發明 詳 細 說 明： 本 發 明 係揭 露一種重新 分佈 層之結構及其製程。 請 參 考第 3 圖 所 繪示 之本發明之 一較 佳實施例之重新分佈 層 之 剖面 結 構 圖 ，其 中更包括於 後續 製程形成之護層140 > 凸 塊下 金 屬 層 150 、以及銲料凸塊 160等。本發明之重 新 分 佈層 1 12 除 包括 重新分佈層 之介 電層1 1 4與重新分佈 層 之 金屬 層 1 16 外， 更包括其它 如半 導體基材1 1 〇、蝕刻 中 止 7 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐) 533572 A7 B7 五、發明說明（） 層1 3 0、以及間隙壁1 7 0等。以下說明與重新分佈層n 2 之結構相關之各元件間的連接關係。 .............·裝： (請先閲讀背面之注意事項再填寫本頁) 半導體基材11 〇主要例如可為石夕底材，但也包括已於 先前製程形成之其它元件。此外，半導體基材i 10更具有 上金屬層120，其中上金屬層120之上表面係為半導體基 材110之部分上表面。上金屬層120係為半導體基材110 内數層金屬層中的最上層，故稱之為上金屬層丨2〇。 敍刻中止層130係覆蓋半導體基材no與部分之上金 屬層120。蝕刻中止層130的材質例如可為氮化物，其用 途為可避免後續進行形成介層洞1 1 1之蝕刻製程時，亦將 不該钱刻的上金屬層1 2 0 —併餘刻。 經滴部智慧財產局員Η涓黄合竹初邙榮 重新分佈層之介電層1 14係覆蓋上述麵刻中止層 1 3 0。介層洞1 1 1則由上至下垂直貫穿重新分佈層之介電層 1 1 4以及姓刻中止層1 3 〇。因此，介層洞1 1 1可與上金屬層 1 2 0相連接。此外，重新分佈層之介電層1 1 4例如可為氧 化物。再者，運用本發明之具有間隙壁丨7〇之重新分佈層 1 1 2之結構可使重新分佈層之介電層1 1 4的高度達約 3 μπι ’而仍能使後續先後在介層洞i丨丨中所沉積的重新分 佈層之金屬層1 1 6與遵層1 4 0獲得較佳的階梯覆蓋之效 果。 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 經濟部智慧財產局員工消費合作社印製 533572 A7 -----Μ -----—------ 五、發明説明（） 本發明之最主要特色為具有間隙壁丨7〇之結構。間，、 壁1 7 0係位於上述介層洞i丨丨之側壁。此間隙壁丨7 〇的夕' 觀係為平滑之弧形，可藉以使後續的薄膜沉積之猫 k佳的階梯覆蓋之效果，或稱此間隙壁丨7 〇具有共^ (conformal)之功能。此外，重新分佈層之金屬層116進2 步覆蓋部分之上金屬層120、間隙壁ι7〇、以及重新分佈層 之介電層114,其中重新分佈層之金屬層116之材質例2 可為鋁、銅、或鋁鋼合金。由於間隙壁丨7〇具有弧形之外 觀，因此重新分佈層之金屬層116與後續的護層14〇，皆 如第3圖中所示，具有較佳的階梯覆蓋之效果，而不至於 有前述習知在介層洞1 1 (請參考第2圖）中幾乎形成斷路， 且造成此處具有很大的接觸電阻，進一步導致元件的可化 賴度大幅降低之缺點產生。 除上述本發明之重新分佈層之結構外，本發明更包括 重新分佈層之製程。請參考第4A圖至第4E圖所繪示之本 發明之一較佳實施例之重新分佈層之製程之結構剖面圖。 本發明之製程係包括下述步驟。首先，如第4A圖所示，提 供具有上金屬層120之半導體基材11〇，其中上金屬層120 之上表面係為半導體基材1 1 〇之部分上表面。接著，形成 蝕刻中止層130，覆蓋半導體基材11〇,其中此蝕刻中止層 1 3 0的材質例如可為氮化物，其用途為町避免後續進行形 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) -------------·裝---------訂--------- (請先閱讀背面之注意事項再填寫本頁} 五、發明説明（） 成"層洞1 1 1(請參考第 , 圖）之蝕刻製程時，亦將不該赛 刻的上金屬層12〇 — ^ °接者，形成重新分佈層之介 (請先閲讀背面之注意事項再填寫本頁) 電層114，覆蓋蝕刻中止 禮130其中此重新分佈層之介電 層1 1 4的材質例如可· i $ 了為乳化物。運用本發明之具有間隙壁 170(請參考第4E圖| ^ a 間）之重新勿佈層U 2之製程可使重新分 佈層之介電層114的古疮、去^ ， 八 的同度達約3 ，而仍能使後續先後在 ^ 5 1 1中所’冗積的重新分佈層之金屬層1 1 6與其它薄 膜之沉積獲得較佳的階梯覆蓋之效果。 接著，如第4B圖所示，去除部分之重新分佈層之介^ 層H4與部分之蝕刻中止^ 13〇。此步驟可藉以形成介j /同111’且約暴露出部分之上金屬層ι2〇。 接著，如第4C圖所示，形成間隙壁薄獏165，覆蓋重 新分佈層之介電層114以及約暴露出之部分上金屬層12〇 中。另外，位於介層洞之側壁上之間隙壁薄獏丨65係為弧 形，且具有第一高度18〇。 經濟部智慧財產局員工消費合作社印製 接著，去除部分之間隙壁薄膜1 65，藉以約暴露出重 新分佈層之介電層114之上表面與部分之上金屬層12〇。 此時，位於介層洞111之側壁上的間隙壁薄膜可形成如第 4D圖所示之間隙壁17〇。此間隙壁ι7〇具有第二高度， 且第一南度1 9 0約小於第一高度1 8 0。此步驟中係包括例 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 533572 A7 _B7 五、發明説明（） 如蝕刻步驟，且此蝕刻步驟需以例如為乾蝕刻之方法才能 形成間隙壁1 70之弧形外觀。 (請先閲讀背面之注意事項再填寫本頁) 然後，如第4E圖所示，形成重新分佈層之金屬層1 1 6， 覆蓋部分之上金屬層1 20、間隙壁1 70、以及重新分佈層之 介電層Π 4，其中重新分佈層之金屬層1 1 6之材質例如可 為鋁、銅、或鋁銅合金。由於間隙壁1 7 0具有弧形之外觀， 因此重新分佈層之金屬層1 1 6可如此第4E圖中所示，具有 較佳的階梯覆蓋之效果。此外，若再進行習知之後續製程， 則最後可獲得如第3圖中所繪示的護層1 40、凸塊下金屬 層150、以及銲料凸塊160等元件。 綜合上述，本發明之一優點為提供一種重新分佈層之 結構及其製程，可用以改善重新分佈層之介層中階梯覆蓋 之效果。 本發明之另一優點為提供一種重新分佈層之結構及其 製程，可用以降低重新分佈層中介層之接觸電阻。 經濟部智慧財產局員工消費合作社印製 本發明之又一優點為提供一種重新分佈層之結構及其 製程，可用以提高元件之可信賴度。 如熟悉此技術之人員所瞭解的，以上所述僅為本發明 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 533572 A7 B7 五、發明説明（） 之較佳實施例而已，並非用以限定本發明之申請專利範 圍；凡其它未脫離本發明所揭示之精神下所完成之等效改 變或修飾，均應包含在下述之申請專利範圍内。 .............·裝：：:訂.........修 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 12 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐)V. Description of the invention () Field of invention: (Please read the notes on the back before filling this page) The present invention relates to the structure and process of a re-distribution layer (RDL), especially to a Structure and process of a redistribution layer having a smooth spacer structure in a mesial hole of the redistribution layer. BACKGROUND OF THE INVENTION: Flip-chip technology is an advanced semiconductor manufacturing technology that can make the overall package size closer. The flip-chip technology is different from the traditional packaging technology, especially in that the flip-chip technology covers the wafer carrier with the upper surface of the wafer downward, and is electrically connected to the wafer carrier by solder bumps on the wafer surface. Since no bonding wires are required that take up a lot of space, the overall size of a flip-chip package is much tighter than that of a conventional semiconductor device package. Before forming a solder bump on a flip-chip technology wafer, an under bump metallization (UBM) must be formed on the printed surface of the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs of the semiconductor wafer. The metal layer under the bump can be turned into a liquid during the process of forming the bumps of the bumps, so that the solder bumps can be firmly adhered to the wafer. One of the known examples of the under-bump metal layer in the above-mentioned flip-chip technology is the application of the Chinese National Standard (CNS) A4 specification (210X297 mm) for this paper standard. 533572 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 5 2. Description of the invention () Two-layer structure. The material of the bottom layer in the two-layer structure may be aluminum, the material of the middle layer may be nickel-vanadium alloy, and the material of the top layer may be copper, for example. However, this material can be, for example, a three-layer metal structure of aluminum / nickel-vanadium alloy / copper, which can cause manufacturing problems. This problem arises when a wafer with a metal layer under the three-layer bump is used to pass through a number of via holes on the wafer with a spacing of less than about 70 μm (usually about 60 μm or about 50 μm). When a circuit detection contact is formed on the circuit (circuit prObing cntact point): Refer to Figure 1 for this manufacturing problem. Figure 1 is a top view of the unfamiliar redistribution layer. In the case where the distance between each two interlayer holes 11 is less than 70 μm, these interlayer holes U with a distance of about 70 μm are not suitable for the subsequent adhesion of solder bumps, because the solder bumps The size is much larger than the above-mentioned distance, resulting in adjacent, material bumps will contact each other. Therefore, in order to solve this problem, the layer holes 11 can be redistributed to the metal layer under the bump by the redistribution layer 12 = please refer to the conventional redistribution layer drawing shown in FIG. 2. In this second figure, the redistribution layer 2 further includes a heavy dielectric layer 14 and a metal layer 16 of the redistribution layer. In addition, the second figure further includes an upper metal layer 20, an etching stop layer 30, a protective layer 40, a metal layer 50 under the bump, and a solder bump 60. The protective layer 40 covers the metal layer 16 which is recognized as a part of the redistribution layer. 50 metal layers under the bump _, the size of the paper is adapted to the Chinese national standard (CNS) A4 specification (210X297 mm) ........... ^^ ..... .. 、 | ding f Please read the note on the back Js before filling in this page j «^ 3572 Printed by A7 B7 i 'Invention Note () of the Intellectual Property Bureau of the Intellectual Property Bureau of the Ministry of Interest () Metal layer of redistribution layer 16 On the upper and part of the protective layer 40, the solder bump 60 can be firmly adhered to the wafer. The structure of the redistribution layer 12 enables the internal circuits of the semiconductor substrate 10 to be electrically connected via conductive paths such as the upper metal layer 20, the redistribution metal layer 16, the under bump metal layer 50, and the solder bump 60. To an external printed circuit board (not shown). For the South Speed analog application, the dielectric layer 14 of the redistribution layer must have a large height of, for example, about 3 μm, and the dielectric hole 11 must have an aspect ratio of, for example, about 1. ratio) in order to reduce signal interference. However, if the redistribution layer's dielectric layer 14 has a large height, it will result in a poor step coverage effect as shown in FIG. 2 in such a high via hole 11. Step coverage is defined as the width of 80 divided by 90 degrees south. The square degree 90 remains unchanged, and the larger the width of the step 80 is, the larger the value of the step coverage is, which means that the effect of the step coverage is better. Conversely, if the height 90 remains the same, when the width 80 is smaller, it means that the effect of step coverage is poor. In addition, if the width 80 is so small that an open circuit is almost formed in the via hole ^ i, it means that there is a large contact resistance here, and further progress will lead to a significant reduction in the reliability of the device. It is therefore necessary to find a solution. Object and Summary of the Invention: In view of the above background of the invention, the disadvantages of the redistribution layer structure are known. 4 This paper size applies to China National Standard (CNS) A4 specification (210X 297mm) • ----------- · Installation -------- Order (Please read the notes on the back first (Fill in this page again) _ 533572 A7 B7 V. Description of Invention () Therefore, one of the objectives of this report is to provide a redistribution layer structure and its process, which can be used to improve the effect of step coverage in the interlayer of the redistribution layer. (Please read the precautions on the back before filling this page.) Another object of the present invention is to provide a redistribution layer structure and its process, which can be used to reduce the contact resistance of the redistribution layer interposer. Another object of the present invention is to provide a structure of a redistribution layer and a process for improving the reliability of the device. According to the above object of the present invention, the present invention provides a structure of a redistribution layer, which at least includes: a semiconductor substrate having an upper metal layer; a dielectric layer of the redistribution layer covering the semiconductor substrate, and the dielectric of the redistribution layer There is a via hole in the layer, wherein the via hole penetrates the dielectric layer of the redistribution layer, and the via hole is connected to the upper metal layer; the spacer wall is located on the sidewall of the via hole; and the metal layer of the redistribution layer And a dielectric layer overlying the metal layer, the barrier ribs, and the redistribution layer. The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the above-mentioned object according to the present invention. Therefore, the present invention further provides a process for redistributing a layer, including at least the following steps: First, a semiconductor substrate having an upper metal layer is provided, wherein the upper metal layer is provided. The upper surface is a part of the upper surface of the semiconductor substrate; then, an etching stop layer is formed to cover the semiconductor substrate; then, a dielectric layer of a redistribution layer is formed to cover the etching stop layer; then, a portion of the redistribution layer is removed Dielectric layer and part of the etching stop This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) 533572 A7 B7 V. Description of the invention () (Please read the precautions on the back before filling this page) Thereby, a via hole is formed, and a metal layer above the exposed portion is formed. Then, a spacer film is formed to cover the dielectric layer of the redistribution layer and a partially exposed upper metal layer, which is located on the sidewall of the via hole. The partition wall film is arc-shaped and has a first height. Then, a part of the partition wall film is removed to expose the redistribution. The upper surface of the dielectric layer of the cloth layer and a part of the upper metal layer, and the spacer film on the sidewall of the dielectric hole forms the spacer wall, but the spacer wall has a second height, wherein the second height is less than the first height Then, a metal layer of the redistribution layer is formed, covering a portion of the metal layer, the partition wall, and the dielectric layer of the redistribution layer. Brief description of the drawings: The preferred embodiment of the present invention will be described in more detail in the following explanatory text with the following diagrams, in which: FIG. 1 is a top view of a conventional redistribution layer structure; Figure 2 is a cross-sectional structure diagram of a conventional redistribution layer; Figure 3 is a cross-sectional structure diagram of a redistribution layer according to a preferred embodiment of the present invention; 4A to 4E are cross-sectional views showing the structure of a redistribution layer manufacturing process according to a preferred embodiment of the present invention. Description of drawing number comparison: This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X 297 mm) 533572 A7 B7 V. Description of the invention () Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by a consumer cooperative 10 Semiconductor substrate 11 Interlayer hole 12 Redistribution layer 14 Redistribution layer dielectric layer 16 Redistribution layer metal layer 20 Upper metal layer 30 Etching stop layer 40 Protective layer 50 Under bump metal layer 60 Rod bump 80 Width 90 South degree 1 10 Material 111 Interlayer hole 1 14 Redistribution layer dielectric layer 1 16 Redistribution layer metal layer 120 Upper metal layer 130 Etching stop layer 140 Protective layer 150 Bottom metal layer 160 Brilliant bump 165 Gap wall film 170 Gap Wall 180, first height 190, second south 1 12 Redistribution layer invention detailed description: The present invention discloses a structure and process of a redistribution layer. Please refer to FIG. 3 for a cross-sectional structure diagram of a redistribution layer according to a preferred embodiment of the present invention, which further includes a protective layer 140 formed in a subsequent process > a metal layer under the bump 150 and a solder bump 160 and so on. The redistribution layer 1 12 of the present invention includes, in addition to the redistribution layer dielectric layer 1 1 4 and the redistribution layer metal layer 1 16, other materials such as a semiconductor substrate 1 1 0 and an etching stop 7 (please read the back first) Please note this page before filling in this page) This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X 297 mm) 533572 A7 B7 V. Description of the invention () Layer 1 3 0, and partition wall 1 7 0, etc. The connection relationship between the elements related to the structure of the redistribution layer n 2 will be described below. ............. Packing: (Please read the precautions on the back before filling out this page) Semiconductor substrate 11 〇 Mainly, for example, it can be Shixi substrate, but it also includes the previous process Other elements formed. In addition, the semiconductor substrate i 10 further has an upper metal layer 120, wherein the upper surface of the upper metal layer 120 is a part of the upper surface of the semiconductor substrate 110. The upper metal layer 120 is the uppermost layer among several metal layers in the semiconductor substrate 110, and is therefore referred to as an upper metal layer. The etch stop layer 130 covers the semiconductor substrate no and a part of the metal layer 120 thereon. The material of the etching stop layer 130 may be, for example, nitride, and its purpose is to avoid the subsequent etching process of forming the via hole 1 1 1, and the upper metal layer 1 2 0 which should not be engraved should be etched and left for a while. The dielectric layer 1 14 of the redistribution layer is covered by the above-mentioned stop layer 1 30, which is a redistribution layer by the member of Dibu Intellectual Property Bureau. The dielectric hole 1 1 1 penetrates the dielectric layer 1 1 4 of the redistribution layer vertically from top to bottom, and the engraved stop layer 1 3 0. Therefore, the via hole 1 1 1 can be connected to the upper metal layer 120. In addition, the dielectric layer 1 1 4 of the redistribution layer may be, for example, an oxide. In addition, by using the structure of the redistribution layer 1 12 having a partition wall of the present invention, the height of the dielectric layer 1 1 4 of the redistribution layer can reach about 3 μm ′, while still enabling subsequent follow-up in the dielectric layer. The redistribution layer metal layer 1 16 and the compliance layer 1 40 deposited in the holes i 丨 丨 obtain better step coverage effects. This paper size applies to China National Standard (CNS) A4 (210X297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 533572 A7 ----- M --------------- V. Invention Explanation () The main feature of the present invention is a structure with a partition wall 700. In the meantime, the wall 170 is located on the side wall of the above-mentioned via hole i 丨 丨. The view of the wall 丨 7 〇 is a smooth arc, which can be used to make the subsequent film deposition of the cat step coverage effect better, or the wall 丨 7 〇 has a function of conformal (conformal) . In addition, the metal layer 116 of the redistribution layer further covers the metal layer 120, the partition wall 70, and the dielectric layer 114 of the redistribution layer. The material example 2 of the metal layer 116 of the redistribution layer may be aluminum. , Copper, or aluminum-steel alloy. Because the barrier wall 丨 70 has an arc-shaped appearance, the redistribution layer of the metal layer 116 and the subsequent protective layer 14 are both shown in Figure 3, which has a better step coverage effect, without The foregoing knowledge almost forms an open circuit in the interlayer hole 11 (refer to FIG. 2), and causes a large contact resistance here, which further results in the disadvantage of greatly reducing the reliability of the device. In addition to the structure of the redistribution layer of the present invention, the present invention further includes a process of redistribution layer. Please refer to FIG. 4A to FIG. 4E for a structural cross-sectional view of a redistribution layer manufacturing process according to a preferred embodiment of the present invention. The process of the present invention includes the following steps. First, as shown in FIG. 4A, a semiconductor substrate 110 having an upper metal layer 120 is provided. The upper surface of the upper metal layer 120 is a part of the upper surface of the semiconductor substrate 110. Next, an etch stop layer 130 is formed to cover the semiconductor substrate 110. The material of the etch stop layer 130 may be, for example, nitride, and its purpose is to avoid subsequent shaping. The paper size is applicable to the Chinese National Standard (CNS) A4. Specifications (210X297 mm) ------------- · Packing --------- Order --------- (Please read the precautions on the back before filling This page} 5. Description of the invention () In the etching process of "layer hole 1 1 1 (please refer to the figure)", the upper metal layer 120 which should not be engraved will also be connected, forming a redistribution The layer of the dielectric (please read the precautions on the back before filling this page) The electrical layer 114 covers the etching stop ceremony 130. The material of the dielectric layer 1 1 4 of this redistribution layer can be i. The process of redistribution layer U 2 with a spacer 170 (please refer to FIG. 4E | ^ a) of the present invention can make the redistribution of the dielectric layer 114 of the redistribution layer, and remove the ulcers. 3, and still can make the subsequent redundancies of the redistribution layer of the metal layer 1 1 6 and other thin film deposition to obtain a better step coverage effect. As shown in FIG. 4B, the part of the redistribution layer of the interlayer ^ layer H4 and the part of the etching stop ^ 13. This step can be used to form the interlayer j / same 111 'and approximately expose the part of the metal layer ι2 Next, as shown in FIG. 4C, a thin spacer 165 is formed to cover the redistribution layer of the dielectric layer 114 and the exposed part of the upper metal layer 120. In addition, the layer on the sidewall of the dielectric hole The gap wall thin 貘 65 is curved and has a first height of 18. It is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Then, a part of the gap wall film 1 65 is removed to expose the dielectric of the redistribution layer. The upper surface of the layer 114 and a portion of the metal layer 12 above. At this time, the spacer film on the sidewall of the via 111 can form a spacer 17 as shown in FIG. 4D. This spacer ι70 has a first Two heights, and the first south degree of 190 is less than the first height of 180. This step includes an example. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 533572 A7 _B7 V. Description of the invention () Such as the etching step, and this etching step requires an example If it is a dry etching method, the curved appearance of the partition wall 1 70 can be formed. (Please read the precautions on the back before filling this page.) Then, as shown in Figure 4E, form the redistribution layer metal layer 1 1 6 The metal layer 120 on the covering part, the partition wall 1 70, and the dielectric layer Π 4 of the redistribution layer, wherein the material of the metal layer 1 1 6 of the redistribution layer may be, for example, aluminum, copper, or an aluminum-copper alloy. Because The partition wall 170 has an arc-shaped appearance, so the metal layer 1 16 of the redistribution layer can be as shown in FIG. 4E, which has a better step coverage effect. In addition, if a conventional subsequent process is performed, components such as a protective layer 140, a metal layer under the bump 150, and a solder bump 160 as shown in FIG. 3 can be finally obtained. To sum up, one advantage of the present invention is to provide a structure and a process of a redistribution layer, which can be used to improve the effect of step coverage in the interlayer of the redistribution layer. Another advantage of the present invention is to provide a structure of a redistribution layer and a process for reducing the contact resistance of the redistribution layer interposer. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Another advantage of the present invention is to provide a redistribution layer structure and its process, which can be used to increase the reliability of components. As will be understood by those familiar with this technology, the above is only the paper size of the present invention applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 533572 A7 B7 V. The preferred embodiment of the invention description () It is not intended to limit the scope of patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the scope of patent application described below. ............. Packing ::: Order ......... Repair (Please read the notes on the back before filling this page) Employee Cooperatives of Intellectual Property Bureau, Ministry of Economic Affairs Printed on 12 paper sizes for China National Standard (CNS) A4 (210X297 mm)