TW533550B - A memory device structure and the method of fabricating the same - Google Patents

Abstract

A method of fabricating a memory device structure, where the method includes the steps of forming a tunnel oxide layer, a silicon nitride layer and a silicon oxide layer. A conductive layer is then formed on top of the silicon oxide. The conductive layer is then patterned to form a conductive gate layer. The silicon oxide layer is patterned during the same step of patterning the conductive layer, exposing the silicon nitride layer. Following that, a blanket dielectric layer is then formed on the substrate. This blanket dielectric layer is patterned with one etch step to form a spacer wall at the sides of the conductive gate layer.

Description

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533550 The present invention relates to a structure of a semiconductor device and a method for manufacturing the same, and more particularly to a structure of a memory device and a method for manufacturing the same. 0 A typical flash memory system uses a doped polycrystalline stone to make a floating gate. With control brake. When programming, the electrons incident on the floating gate are evenly distributed throughout the polycrystalline silicon floating gate layer. However, if there is a defect in the tunneling oxide layer under the denier floating gate layer of polycrystalline silicon, it will easily cause leakage current of 7L parts and affect the reliability of the device. Muli has developed a structure of silicon-oxide-nitride_oxide_semiconductor (S0N0S) memory elements. When this device applies a voltage to the word line and the embedded drain to program the inferiority, the electrons in the pass-through region close to the embedded drain region will be injected into the atmosphere when the voltage is 800 million. Bu Shi 々 丄 丄 耵 孓 said in the silicon layer. Also, because the silicon nitride material: has the characteristics of capturing electrons', therefore, the electrons injected into the silicon nitride layer are not evenly distributed throughout the entire silicon nitride layer. In the silicon nitride layer, @ is a Gaussian distribution: it is concentrated on a local area of the silicon nitride layer. Since the electrons incident on the siliconized silicon: are concentrated only in the local area $, The defect is less sensitive, and the phenomenon of element leakage current is less likely to occur. As shown in Figures 1A to 1C, it is shown as a schematic cross-sectional schematic diagram of the manufacturing process of a sonos memory element. Right please Referring to FIG. 1A, a substrate 100 is first provided, wherein the substrate 100 has a memory cell region 12 and a peripheral circuit region 13. Then, an oxide layer 102 is formed on the substrate 100. Then y--^ ^ 1 η 0 L ^ silicon layer 1 04 and a silicon oxide barrier silicon dioxide layer, a nitrogen L silicon layer 1 〇 6 .Receive the peripheral circuit area

533550 V. Description of the invention (2) In addition, the A oxygen ^^ layer 1 G2, the nitrided second layer 1 G 4 and the oxidation-resistant hard layer 106 are moved. ^-Wet oxidation method on the substrate 1 of the peripheral circuit area 130 〇〇surfaced layer 103. Next, a single π 08 is formed on the oxygen-blocking layer 106 of the memory cell region 120 and the gate silicon oxide layer of the peripheral circuit region 3 0 3. In addition, a patterned photoresist is formed on the polycrystalline stone layer 108 every 110, and the gate structure is planned to be formed. Then, please refer to FIG. 1B. With the photoresist layer 110 as an etching mask, the polycrystalline silicon layer 108 and the silicon oxide blocking layer 120 of the memory cell region 120 are patterned. 〇6—The silicon nitride layer 104-The silicon oxide layer 1 〇2, and the polycrystalline silicon layer 108 and the gate silicon oxide layer 〇3 in the peripheral circuit area 130, to form a gate structure in the memory cell area 208 and the peripheral circuit area, respectively. Among them, the gate structure formed in the memory cell area is formed by a penetrating oxide layer 02b, a silicon nitride charge trap layer 104b, a blocking oxide layer 106b, and a polycrystalline silicon layer 110. Make up. The gate structure of the peripheral circuit area 130 is formed by a gate oxide layer 102 and a silicon layer 108a. Then, the gate structure is used as an ion implantation mask to form a lightly doped drain region 112b and n2a in the substrate 100 on both sides of the gate structure of the memory cell region 120 and the peripheral circuit region 130. After that, please ask Mai according to Fig. 1C to form a spacer 丨 4b, i 丨 4a on both sides of the gate structure of the memory cell area 丨 2 0 and the peripheral circuit area 130. Next, the spacers 11 4b and 1 1 4a are used as an ion implantation mask to form a source / drain region 11 6 b and 11 6 a in the substrate 丨 00 on both sides of the spacers 114b and 114a, respectively. . Then, post-processes such as metal interconnections are performed to complete the production of a memory device. In the above step of fabricating a memory device, patterning the polycrystalline silicon layer

Page 6 533550 5. In the description of the invention (3), the polycrystalline silicon layer of the memory cell area and the peripheral circuit area is patterned at the same time. And after patterning the polycrystalline silicon, the resist silicon oxide-silicon nitride-silicon oxide layer of the memory cell region and the gate oxide layer of the peripheral circuit region are patterned immediately. However, the thickness and structure of the gate oxide layer and the gate oxide layer in the peripheral circuit area are greatly different due to the barrier oxide oxide layer-the nitride oxide layer-the oxide layer layer in the memory cell area, plus 0.2 5 microns below During the manufacturing process, the thickness of the gate oxide layer is getting thinner and thinner. Therefore, it is quite difficult to completely pattern the barrier silicon oxide-silicon nitride-silicon oxide layer of the memory cell region, and to prevent the substrate surface of the peripheral circuit region from being subjected to depressions due to over-etching. In order to solve the above problem, another conventional method is to divide the polysilicon layer etching step of the peripheral circuit area and the memory cell area into two steps to ensure the integrity of the device. However, this method requires an additional mask, which increases the complexity of the process. Therefore, an object of the present invention is to provide a method for manufacturing a structure of a SONOS memory element, so as to solve the problem that the conventional surface damages the substrate surface of the peripheral circuit region when the polycrystalline silicon layer is patterned. Another object of the present invention is to provide a structure extremely manufacturing method of a memory element so that the complexity of the manufacturing process can be reduced. The invention provides a method for manufacturing a memory device. This method is to first form a tunneling oxide layer, a silicon nitride layer and a silicon oxide blocking layer on a substrate in order. A conductive layer is then formed on the silicon oxide blocking layer. Thereafter, the conductive layer is patterned to form a gate conductive layer, and at the same time, the silicon oxide blocking layer is patterned to expose the silicon nitride layer. Next, a conformal dielectric layer is formed on the substrate, covering the gate conductive layer and the silicon nitride layer. After conformal introduction

9168twf.ptd Page 7 533550 V. Description of the invention (4) The electrical layer is subjected to an etching process to form a gap wall on the side wall of the gate conductive layer. The etch-back process simultaneously removes the silicon nitride layer that is not covered by the spacer, and forms a silicon nitride charge trapping layer. The width of the formed silicon nitride charge trapping layer is larger than that of the gate conductive layer. The invention further includes forming a source / drain region in the substrate on both sides of the gap wall, and forming a metal silicide layer on top of the gate conductive layer and on the source / drain region to reduce the resistance of the device. value. The invention provides a method for manufacturing a memory element. This method firstly provides a substrate, wherein the substrate has a memory cell region and a peripheral circuit region. An oxide layer, a nitride layer, and a dielectric layer are sequentially formed on the surface of the substrate, and then the oxide layer, the nitride layer, and the dielectric layer in the peripheral circuit area are removed, and then a wet method is used. A gate oxide layer is formed on the substrate surface of the peripheral circuit region in the oxidation method. Then, a conductive layer is formed on the dielectric layer in the memory cell region and the gate oxide layer in the peripheral circuit region. Next, the conductive layer is patterned to form a first gate conductive layer in the memory cell area and a second gate conductive layer in the peripheral circuit area, and at the same time, the dielectric layer of the memory cell area and the peripheral circuit area are patterned. The gate oxide layer, and the silicon nitride layer of the memory cell region is exposed. Next, a conformal dielectric layer is formed on the substrate to cover the first gate conductive layer, the second gate conductive layer, and the silicon nitride layer. Then, an etching process is performed on the conformal dielectric layer to form a first gap wall on the side wall of the first gate conductive layer and a second gap wall on the side wall of the second gate conductive layer. The etch-back process simultaneously removes the silicon nitride layer in the memory cell region that is not covered by the first spacer, and forms a silicon nitride charge trapping layer. The width of the formed silicon nitride charge trapping layer is larger than that of the first silicon nitride charge trapping layer.

9168twf.ptd Page 8 533550 V. Description of the invention (5) Gate conductive layer Two gap walls Two gate conductive layers form a metal The present invention includes a substrate, an oxide layer, and an oxide layer on the tunneling oxide, in other words degree. Between the oxygen barrier layer and the outer layer, the silicon nitride conductive layer is on top of the electrical layers on both sides of the gap to reduce the layer of oxygen on the layer of the polycrystalline stone layer of the present invention to avoid the surrounding electricity. Requires additional i: ί bottom::: in the first-spacer and M ^-η ^ ^ source / drain regions, and in the first silicon servant μ ra, σ 员 and source / drain A silicide layer on the region is used to reduce the element. A memory element is proposed to pass through the oxide layer and the nitride structure. The memory element includes the gate conductive layer and-^: charge trap layer,-block "C" on the surface of the substrate. Which ’then penetrates the layer. The inter-electrode conductive layer ::; the charge-trapping layer is configured to be disposed on a part of the charge-trapping layer, and the width of the electric% trapping layer is larger than that of the gate conductive layer; Gate conductive layer and silicon nitride charge trap layer. In addition, the partition wall is arranged on the nitride stone charge trap layer and the oxide stone layer: the side wall. The present invention further includes a source / a region arranged in the nitride nitride substrate, and a metal silicide layer disposed on the gate conducting and source / drain regions to use a resistance value. Because of the patterning step, the manufacturing method of the S0N0S memory element only patterned the Shixiu layer and the oxidized stone—nitride stone_oxidized stone fossil layer, and stayed in the nitrided layer. For this reason, the base of the road area was damaged during this button-engraving process. The manufacturing method of the S0N0S memory element can be performed simultaneously because the remaining steps of the polycrystalline layer in the memory circuit area can be performed simultaneously, and the photomask and etching steps can simplify the manufacturing process.

533550 V. Description of the invention (6) ---- In the embedded process. The structure of the SON0S memory element of the present invention can provide more charge trapping areas due to the larger area of the silicon nitride charge trapping layer, which can increase the prediction of the starting voltage when programming (Wind0w). ). In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows: Symbols of the drawings: 100, 20 0: substrates 102, 102a, 102b, 103, 106, 106a, 106b, 202, 202a, 202b, 203, 206, 206a, 206b: oxide layers 104, 104b, 204, 204b: silicon nitride layers 108, 108a , 108b, 208, 208a, 208b: polycrystalline silicon layer 11 0, 2 1 0: photoresist layer 11 2a, 1 1 2b, 21 2a, 21 2b: lightly doped drain regions (LDD) 114a, 114b, 218a, 218b: spacers 116a, 116b, 216a, 216b: source / drain 1 2 0, 2 2 0: memory cell area 130, 23 0: peripheral circuit area 2 1 8: conformal dielectric layer 2 1 9: metal FIG. 2A to FIG. 2E of the embodiment of the Shixihua compound are schematic cross-sectional views illustrating a manufacturing process of a SONOS memory device according to a preferred embodiment of the present invention.

9168twf.ptd Page 10 533550 V. Description of the invention (7) One: Figure 2A 'first provides a substrate 200, in which the substrate 200 has an upper region and a peripheral circuit region 230. Next, an isolation region (not shown) is formed on the substrate y to define an active region. A well area (not shown) is formed in the active area at the bottom of 200. Immediately after that, a silicon oxide layer 202 is formed on the substrate 200. A nitride stone layer 204 and a barrier stone oxide layer 2 ram are formed on 2 ^ 2. Its g property, ΐΓ = 4, can also be replaced by other ones with stored charge or charge trapping == 2. The same 'blocking stone oxide layer 206 can also be replaced by the second "electric material shell." Then the' blocking stone oxide layer, peripheral silicon layer 204 and the blocking silicon oxide layer 206 in the peripheral circuit area 23 Remove. Then, on the surface of the substrate 2000 in the peripheral circuit area 230, thirst-type gas and an oxide layer 20 3 are formed. After the silicon oxide method forms a gate, the silicon oxide is blocked in the memory cell area 220 at the same time. Lu 206: A polycrystalline stone layer is formed on the oxidized stone layer 203 of electricity = 230. : In the evening, the silicon layer 20 8 can also be replaced with other conductive materials. The materials that can be used as the gate conductive layer are suitable for the patterned photoresist layer 21 on the polycrystalline silicon layer 208 of the present invention. (^ Determine the gate structure. Pre-shape the compound. Then, please refer to Figure 28, using the photoresist layer 210 as a mask to mask the polycrystalline silicon layer 208 and the silicon oxide barrier layer 222 of the memory cell area. — ,: The polycrystalline silicon layer 208 and the gate silicon oxide layer 203 in the peripheral circuit area 230 are different from the memory cell area 22G and the peripheral circuit area 23G. Here, the silicon oxide layer 206 and nitrogen are blocked. The siliconized layer has

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High etch selectivity, therefore, this etch step can be controlled to stay on the silicon nitride layer 204. This makes it easier to control this etching step, thereby preventing problems such as depressions on the surface of the substrate 200 of the peripheral circuit region 230 due to over-etching. Next, the gate conductive layers 20 8b and 20 8a are used as ion implantation masks to form a lightly doped drain electrode in the substrate 2 0 on both sides of the gate conductive layers 2 8 b and 2 0 8 a. Zone 2 1 2 b, 2 1 2 a. Then, a “constructed 2C picture” forms a conformal dielectric layer 218 on the substrate 200, covering the gate conductive layers 208b, 208a, and the nitride nitride layer 206. Among them, the material of the conformal dielectric layer 2 1 8 is preferably silicon nitride. After that, please refer to FIG. 2D, and carry out a money engraving process on the conformal dielectric layer 2 1 8 to form gap walls 218b and 218a on the side walls of the gate conductive layers 208b and 208a, respectively. Among them, since the material of the conformal dielectric layer 218 is silicon nitride, during the process of etching back the conformal dielectric layer 218, it can be covered by the non-gate conductive layer 208b and the spacer 218b at the same time. The silicon nitride layer 201 is removed to form a nitride nitride charge trapping layer 204b. The width of the vaporized silicon charge trap layer 204b formed therein is larger than the width of the gate conductive layer 208b. In other words, the width of the silicon nitride charge trap layer 204b of the present invention is larger than the width of the silicon nitride charge trap layer of a conventional memory device. Therefore, the memory device of the present invention can increase more charge trapping regions. In this way, in the process of thinking about the body element, the initial voltage can be predicted. Next, the spacers 218b and 218a are used as ion implantation masks, and a source / middle is formed in the substrate 200 on both sides of the spacers 218b and 21 8a. Then, refer to FIG. 2E. The memory element of the present invention further includes

9168twf.ptd Page 12 533550 V. Description of the invention (9) =: =, the top of 2088 and the source area 2i6b, the substrate 200 above the ziba form a metal dream layer 219: = two "stone oxide layer 219. Among them, a metal layer, and then a rod is provided to form a cover on top of the substrate 200, so that it is not covered by the partition 2 1 8b, 2 1 8a For example, cobalt silicide. Afterwards, the metal interconnects are made. ^ ^ The production of components. ^ Silly slave I ί King, the yuan into a memory cell two copies issued: month of: f memory elements formed include With-memory moon dagger [220 and one of the peripheral circuit areas 230, Meiya cell area 220 includes a pair of right-hand syllables Tu's 200. ,, and the middle 'is equipped with a gate electrode at 9n9K armored dagger. The conductive layer 208b'-then penetrates the oxide layer 2b, the charge trapping layer of the nitride oxide layer, the barrier layer of the oxide oxide layer at Z 218b, and the source / non-polar area mb. In another example, the region 230 includes an inter-oxidation layer 202a, an osmium layer, a nitrogen-cutting spacer 2118a, and a source / inverter in the memory cell area 22 0, which penetrates the oxide layer 20 Torr system. Placed on the surface of the base of the memory cell 2 0 0. The silicon nitride charge trapping layer 204 is disposed on the chemical layer 202b, and the gate conductive layer 2 is matched on ^ = = 2Q4b. In other words, the nitrogen_charge trapping layer 2 is larger than the gate conductive layer 2 08b width. An oxygen blocking core is arranged between the gate conducting layer and the fossil evening charge trapping layer 204b, which is used to isolate the idler conducting layer 208b and the nitrogen cutoff 204b. ^ Outer 'nitrogen-cutting spacer 2118b is disposed on the side wall of nitride nitride 533550 V. Description of the Invention (2) layer 2 041) and the gate conductive layer 2081 :) and the silicon oxide blocking layer 2061). The source / drain region 21 6b is disposed in the substrate 200 on both sides of the silicon nitride spacer 2 18b. In addition, in the peripheral circuit region 230, the gate oxide layer 202a is disposed on the surface of the substrate 200, and the gate conductive layer 2 08a is disposed on the gate oxide layer 202a, and the silicon nitride spacer 21 8a is disposed on the side wall of the gate conductive layer 20 08a and the gate oxide layer 2 02 a. The source / drain electrode 2 1 6 a is arranged in the substrate 2 0 on both sides of the nitride spacer wall 2 1 8 a. The memory device of the present invention further includes a metal silicide layer 2 丨 9 on the surface of the substrate 2 0 0 on top of the gate conductive layers 208a and 208b and above the source / drain 2 16a to reduce the gate. The resistance values of the electrode conductive layers 2 0 a, 20 8b and the source / drain 2 i6a. According to the manufacturing method of the SONOS memory element of the present invention, because of the step of patterning polycrystalline silicon to form a gate conductive layer, only the polycrystalline silicon '' final gas fossil oxidized-oxidized oxidized oxidized oxidized oxidized layer is patterned;:, And the evening = lice silicon layer. Therefore, it is possible to prevent the surface of the substrate in the peripheral circuit area from being depressed due to over-etching. In addition, in the method for manufacturing the SONOS memory element & part of the present invention, the worm-etching step of the polycrystalline silicon 'electrical layer in the memory cell region and the peripheral circuit region can be performed simultaneously without the need for etching. Steps, thus simplifying the process and suitable for embedded processes. Furthermore, the structure of the S0N0S memory element of the present invention, since the width of the silicon nitride charge trap layer is larger than the width of the charge trap layer of the conventional memory element, this can provide more charge trapping regions, so that the memory element The stylized yushi can increase the prediction of its starting voltage. tIn summary of the above, the present invention has the following advantages:

533550 V. Description of the invention (11) 1 · The manufacturing method of the memory element of the present invention can prevent the substrate of the peripheral circuit area from being damaged during this etching process. 2. The manufacturing method of the memory device of the present invention, which can simplify the manufacturing process and is applicable to the embedded manufacturing process. 3. The structure of the memory device of the present invention can improve the initial voltage prediction of the device during programming. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.

9168twf.ptd Page 15 533550 Figures briefly explain Figures 1A to 1C are cross-sectional schematic diagrams of the manufacturing process of a conventional SON0S memory element; and Figures 2A to 2E are diagrams according to a preferred embodiment of the present invention Schematic diagram of the manufacturing process of SON 0S memory components.

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Claims (1)

533550 6. Application scope 1. A method for manufacturing a memory device, comprising: forming a tunneling oxide layer, a charge-trapping material layer, and a dielectric layer on a substrate; and forming a conductive layer on the dielectric layer Patterning the conductive layer to form a gate conductive layer, and simultaneously patterning the dielectric layer to expose the charge trapping material layer; forming a conformal dielectric layer on the substrate to cover the gate conductive layer and the A charge-trapping material layer; and performing an etch-back process on the conformal dielectric layer to form a gap wall on a side wall of the gate conductive layer. 2. The method of manufacturing a memory device according to item 1 of the scope of patent application, wherein the charge trapping material layer includes a silicon nitride layer. 3. The method of manufacturing a memory device according to item 1 of the scope of the patent application, wherein the material of the conformal dielectric layer includes silicon nitride, and the formed spacer silicon is a silicon nitride spacer. 4. The method of manufacturing a memory device according to item 1 of the scope of the patent application, wherein the etch-back process simultaneously removes the charge-trapping material layer that is not covered by the spacer to form a charge-trapping layer. 5. The method for manufacturing a memory device according to item 1 of the scope of patent application, wherein the material of the dielectric layer includes silicon oxide. 6. The method for manufacturing a memory device according to item 1 of the scope of patent application, wherein the material of the conductive layer includes polycrystalline silicon. 7. The method for manufacturing a memory device according to item 1 of the scope of patent application, wherein the substrate on both sides of the gap wall further includes forming a source / 9168twf.ptd Page 17 533550 6. Scope of patent application > and polar regions. 8. The method for manufacturing a memory device according to item 1 of the scope of the patent application, wherein a metal silicide layer is further formed on top of the gate conductive layer. 9. A method for manufacturing a memory device, comprising: providing a substrate having a memory cell region and a peripheral circuit region; forming an oxide layer, a charge trapping material layer, and a dielectric layer on a surface of the substrate; Removing the oxide layer, the charge-trapping material layer, and the dielectric layer of the peripheral circuit area; forming a gate oxide layer on the substrate surface of the peripheral circuit area; the dielectric layer in the memory cell area; and Forming a conductive layer on the gate oxide layer in the peripheral circuit area; patterning the conductive layer to form a first gate conductive layer in the memory cell area and forming a second gate conductive layer in the peripheral circuit area, Simultaneously pattern the dielectric layer of the memory cell region and the gate oxide layer of the peripheral circuit region to expose the charge-trapping material layer of the memory cell region; forming a conformal dielectric layer on the substrate to cover The first gate conductive layer, the second gate conductive layer, and the charge trapping material layer; and performing a worm-etching process on the conformal dielectric layer so that the first gate conductive layer The side wall forms a first gap wall and a second gap wall is formed on the side wall where the second gate is conductive. 10. The manufacturer of the memory element as described in item 9 of the scope of patent application 9168twf.ptd Page 18 533550 6. Patent application method, wherein the charge trapping material layer includes a silicon nitride layer. 1 1. The method for manufacturing a memory device according to item 9 of the scope of the patent application, wherein the material of the conformal dielectric layer includes silicon nitride, and the first and second spacers are formed. They are a silicon nitride spacer. 1 2. The method for manufacturing a memory device according to item 9 of the scope of the patent application, wherein the etch-back process simultaneously removes the charge trapping material layer that is not shielded by the first gap wall to form a charge trap. Floor. 1 3. The method for manufacturing a memory device according to item 9 of the scope of the patent application, wherein the material of the dielectric layer includes silicon oxide. 1 4. The method for manufacturing a memory device according to item 9 of the scope of the patent application, wherein the material of the conductive layer includes polycrystalline silicon. 1 5. The method for manufacturing a memory device according to item 9 of the scope of patent application, wherein the substrate on both sides of the first spacer and the second spacer further includes forming a source / drain region. 16. The method for manufacturing a memory device according to item 9 of the scope of patent application, further comprising forming a metal oxide layer on top of the first gate conductive layer and the second gate conductive layer. 1 7. A structure of a memory element, including: a substrate; a tunneling oxide layer disposed on the substrate; a charge trapping layer disposed on the tunneling oxide layer; a gate conductive layer disposed on On part of the charge trapping layer, the width of the charge trapping layer is greater than the width of the gate conductive layer; a dielectric layer is disposed on the gate conductive layer and the charge trapping layer. 9168twf.ptd Page 19 533550 6. Between the scope of patent application; and a gap wall, which is arranged on the charge trapping layer and the gate conductive layer and the sidewall of the dielectric layer. 1 8. The structure of the memory device according to item 17 of the scope of the patent application, wherein the material of the charge trapping layer includes silicon nitride. 19. The structure of the memory device according to item 17 of the scope of the patent application, wherein the spacer is a silicon nitride spacer. 20. The structure of the memory device as described in item 17 of the scope of the patent application, wherein the material of the dielectric includes silicon oxide. 2 1. The structure of the memory device according to item 17 of the scope of patent application, wherein the material of the conductive layer includes polycrystalline silicon. 2 2. The structure of the memory element according to item 17 of the scope of patent application, wherein the substrate on both sides of the gap wall further includes a source electrode and a polar region. 2 3. The structure of the memory device according to item 17 of the scope of the patent application, wherein a metal silicide layer is further disposed on top of the gate conductive layer. 9168twf.ptd Page 20