TW531816B - Semiconductor package substrate - Google Patents
Semiconductor package substrate Download PDFInfo
- Publication number
- TW531816B TW531816B TW91106113A TW91106113A TW531816B TW 531816 B TW531816 B TW 531816B TW 91106113 A TW91106113 A TW 91106113A TW 91106113 A TW91106113 A TW 91106113A TW 531816 B TW531816 B TW 531816B
- Authority
- TW
- Taiwan
- Prior art keywords
- substrate
- package structure
- semiconductor package
- main body
- patent application
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
531816531816
【發明領域】 本發明係有關於一種半導體封裝構造之基板,更特別有 關一種用於球格陣列(BGA)封裝之基板,使得封膠塑料之 杈造過耘中不致於產生氣孔或溢膠之缺點,並同 好的散熱效果。 丁捉1/、艮 【先前技術】 在工業界裡,半導體的封裝加工程序,一般可約略分為 晶圓切割、黏晶、銲線、封膠、印字、包裝。其中,封膠 (mo 1 d 1 ng )的主要目的為防止濕氣由外部侵入、以機械 方式支持導線、有效地將内部產生之熱排出於外部、及提 供能夠手持之形體。以球格陣列(BGA)封裝為例,其過程 大體上為將模具置於一基板上,將固態的封膠塑料(Ερ〇π Molding Compound; EMC)加熱溶融成液態,經由柱塞 (Plunger)施予壓力進入該模具之模穴裡,使得封膠^塑料 密封住該基板上之晶片或電子元件以形成一完全氣密之^ 膠體,待封膠體硬化之後,再進行脫模完成封膠製^。 舉例而言,習用之球格陣列(BGA)封裝構造之基板10, 如第1圖所示,典型上具有一主體15、複數個導線30位於 該主體15上、以及一銅質之平面金屬片2〇係配置於該主體 15之角落處,且可用以接地(Ground)或供電(power),並 且可用以散發熱量。再如第2圖所示,一層防焊綠漆 (solder mask)40係覆蓋於該主體15、該導線3〇、與該金 屬片20上。該基板10係用以安置一半導體晶片(圖中未 示)’並藉由打線電氣連接至該基板1〇上該導線之銲墊 1111 1 n I 11KB iil_l ill U _ 11H ίίί_ 00483,ptd 第5頁 531816[Field of the Invention] The present invention relates to a substrate for a semiconductor package structure, and more particularly to a substrate for a ball grid array (BGA) package, so that the plastic sealing branch does not cause pores or overflow during the process. Disadvantages and good heat dissipation. Ding Chou 1 、 Gen [Previous technology] In the industrial world, semiconductor packaging processing procedures can generally be roughly divided into wafer cutting, die bonding, wire bonding, sealing, printing, and packaging. Among them, the main purpose of the sealant (mo 1 d 1 ng) is to prevent moisture from invading from the outside, to mechanically support the wires, to effectively discharge the internally generated heat to the outside, and to provide a form that can be held by hand. Taking the ball grid array (BGA) package as an example, the process is generally placing a mold on a substrate, heating and melting a solid sealing plastic (Eρ〇π Molding Compound; EMC) into a liquid, and passing the plunger Apply pressure to enter the cavity of the mold, so that the sealant ^ plastic seals the wafer or electronic component on the substrate to form a completely airtight ^ colloid. After the sealant is hardened, it is demolded to complete the sealant. ^. For example, the substrate 10 of a conventional ball grid array (BGA) package structure, as shown in FIG. 1, typically has a main body 15, a plurality of wires 30 on the main body 15, and a copper planar metal sheet. 20 is arranged at the corner of the main body 15 and can be used for ground (ground) or power (power), and can be used to dissipate heat. As shown in FIG. 2, a layer of solder mask 40 covers the main body 15, the lead 30, and the metal sheet 20. The substrate 10 is used to place a semiconductor wafer (not shown in the figure) and is electrically connected to the pads 1111 1 n I 11KB iil_l ill U _ 11H of the wire on the substrate 10 by wire bonding. Page 531816
上。之後’再藉由封膠塑料包封該基板即可完成該球格 列(BGA)封裝構造。 早 然而’在該封膠塑料模造過程中,此種基板丨〇易導致封 f塑料於模造過程中產生氣孔或無法完全填滿模穴的缺 點。如第2圖所示,於該複數條導線3 〇之上方,該綠漆4 〇 之上表面43具有複數個稍微下凹之凹處50。於模造注膠的 ί壬中由於該凹處5 0提供相當良好之排氣作用,使得封 料(圖中未示)可完全填滿該防焊綠漆表面4 3上方之模 八空間:然而’位在該基板1 〇角落處之該平面金屬片20上 方=防焊綠漆表面42便不具有上述之凹處50,而與模具形 成益封=狀態’使得封膠塑料不易填滿該防焊綠漆表面42 上^之杈穴空間,而造成封膠體之表面不平整或氣泡,甚 至‘線裸露等缺點。 若去除 圖所示, 該導線3 0 成溢膠現 之散熱功 要求。綜 20,雖可 膠塑料無 20,則不 程中導致 該基板1 0 由於該基 處之防焊 象。再者 效亦會下 上所述, 提供較佳 法完全填 但失去原 溢膠。 之角落 板1 0角 綠漆表 ,由於 降,而 在該基 之散熱 滿模穴 先散熱 處之該平 落之防焊 面4 3,故 缺少該平 無法滿足 板1 0之角 效果,但 。反之, 性佳之優 面金屬片20,如第3 綠漆表面42之高度 於模造注膠過程中 面金屬片20,該基板1〇 現今I C產品散發熱量的 落配置銅質平面金屬片 往往在注膠過程中使封 若去除該平面金屬片 點,同時亦會在注膠過 _ 有鑑於此 便有需要提供一種半導體封裝構造之基板,on. After that, the substrate is encapsulated with a plastic sealant to complete the ball grid array (BGA) package structure. However, during the molding process of the sealing plastic, such substrates easily lead to the formation of air holes in the sealing plastic or the defects that cannot completely fill the mold cavity. As shown in FIG. 2, above the plurality of wires 3 0, the upper surface 43 of the green paint 4 0 has a plurality of slightly concave recesses 50. Because the recess 50 provides a fairly good exhausting effect in the mold injection molding, the sealing material (not shown) can completely fill the mold eight space above the solder mask green paint surface 4: 'Positioned above the flat metal sheet 20 at the corner of the substrate 10 = solder mask green paint surface 42 does not have the above-mentioned recess 50, but forms a seal with the mold = state' makes the sealing plastic difficult to fill the mask Welding the space on the surface of the green paint surface 42 causes the surface of the sealant to be uneven or air bubbles, and even to the point that the line is bare. If it is removed as shown in the figure, the wire 30 will be required to dissipate heat due to overflow. To sum up, although there is no plastic 20, the substrate 10 is not in the process due to the solder mask at the base. In addition, the effect will be described below, providing a better method to completely fill but lose the original spilled glue. The green paint surface of the corner board 10 corners, due to the drop, and the flat soldering prevention surface 4 3 at the base where the heat dissipation is full of the mold cavity, so the lack of the plane cannot meet the corner effect of the board 10, but . Conversely, the superior surface metal sheet 20, such as the third green lacquer surface 42, is higher than the surface metal sheet 20 during the molding process. The substrate 10 is currently equipped with copper planar metal sheets that are radiating heat from IC products. If the flat metal sheet point is removed during the sealing process, it will also be injected before the sealing. In view of this, it is necessary to provide a substrate for a semiconductor package structure.
第6頁 531816 五、發明說明(3) :得封膠塑料能夠於模造注膠過程中,完全地填滿模穴, 果不會產生氣’泡或溢膠之缺點,纟同時提供良好的散熱效 【發明概要】 本發明之主要目的将摇供_絲屯;皆 使得封膠塑料能夠於模造注膠中:J J J基:’ 而不會產生氣泡之缺點。 “王填滿模穴, 本發明之次要目的係提供一種半 使得封膠塑料能夠避免在注膠過程中溢膠&之基板’ I =明之另—目的係、提供一種半導體封裝構 二有良好之散熱性,可將該晶片 土板’ 效排出。 保作日守所產生之熱量有 為達上述目的,本發明之提供一 之基板,包括:一主體,具有複數3 = +導體封裝構造 上,用以藉由打線連接盥該基板 ¥f,配置於該主體 複數個條狀金屬條,體渗 作為5亥基板之接地或電源接點, 角洛處上, 所產生之熱量排出; 呼、1該晶片於操作時 主體及金屬條。 方知,、、求漆,覆蓋並用以保護該 根據本發明之基板, ίΐ於注膠過程中,具=氣=:;:屬·,使得該 ::模穴,且不致發生溢膠的現象。::助於封膠塑料填 Α 5亥半導體裝置操作時之散熱作用。5亥金屬條亦有 為了讓本發明之上述和其他目的、 将徵、和優點能更明 531816Page 6 531816 V. Description of the invention (3): The sealant plastic can completely fill the mold cavity during the molding and injection process, so that it will not produce the disadvantages of air bubbles or overflowing glue, and it also provides good heat dissipation. Effectiveness [Summary of the invention] The main purpose of the present invention is to shake the supply_Situn; all make the sealing plastic in the injection molding: JJJ-based: 'without the disadvantage of air bubbles. "The king fills the mold cavity. The secondary purpose of the present invention is to provide a substrate that semi-encapsulates the plastic to avoid overflow & during the injection process. 'I = another thing-the purpose is to provide a semiconductor package structure. Good heat dissipation, the chip soil plate can be effectively discharged. The heat generated by Baoshou Rishou can achieve the above purpose. The present invention provides a substrate including a main body with a plurality of 3 = + conductor packaging structures. It is used to connect the substrate ¥ f by a wire, and is arranged on the main body of a plurality of strip-shaped metal strips. The body permeation serves as the ground or power contact of the substrate, and the heat generated at the corner is discharged; 1 、 The main body and metal strip of the wafer during operation. It is known that ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, required to protect, the substrate according to the invention, :: Mould cavity, and the phenomenon of glue overflow will not occur. :: Helps the heat-seal effect of the plastic seal filling A 5 Hai semiconductor device during operation. The 5 Hai metal strip also has the purpose of allowing the above and other purposes of the present invention. , And advantages can be more clear 531816
實施例,並配合所附圖示 顯特徵,下文特舉本發明較佳 作詳細說明如下。 【發明說明】 如第5及6圖所+,甘% &丄上 A板11 (1 #用认,其顯不根據本發明之一基板11 〇,該 土板no係用於球格陣列(BGA)之封裝構造中。嗲美 具有一主體115,為大髀卜 古 以土板 m 0^ ]Ί u 馮大體上之方形。該主體11 5具有複數個 用以兹士士 ^防焊綠漆(solder mask)140。該導線130係 狀^、曾^、、、連接(wire bonding),與該基板110上所加 二晶片(圖中未示)電氣連接。該防焊綠漆14〇係 主體115及該導線13G。該主體115 —般係以樹脂、 玉、、、維強化BT (bismaieimide —triazine)樹脂、陶瓷材 料等材料所製得。 一該基板110之主體丨15上另具有複數個條狀金屬條丨25及 環繞$屬帶126,分別配置於該主體115之各角落處,位於 該防焊綠漆140之下方。該環繞金屬帶126與每一個該_ 條=5之^端相連並包圍該金屬條125,使得該金屬條^::. 及金屬ητ 1 26構成一網狀(mesh)外形,藉此使得個別之該 金屬條125與該金屬帶丨26間係電氣連接的。藉此該金屬條 1 2 5及金屬帶1 2 6可用以作為接地或電源接點,以增強該基 板11 0之電氣特性,並有助於散發該球格陣列封裝構造操 作時所產生的熱量。當然,精於本技藝者應可瞭解該金屬 條1 2 5及金屬帶1 2 6之數量可視需要予以減少,亦即該基板 110之某些角落並未具有該金屬條125及金屬帶126。 又’參考第6圖,位於該複數條導線13〇處,該綠漆140The embodiments, together with the features shown in the accompanying drawings, are described in detail below with reference to the preferred embodiments of the present invention. [Explanation of the invention] As shown in Figs. 5 and 6, +% A &11; A plate 11 (1 # is recognized, it is not according to one of the substrate 11 of the present invention, the soil plate is used for ball grid array (BGA) package structure. Amami has a main body 115, which is a large rectangular plate with a soil plate m 0 ^] Ί u Feng. The main body 11 5 has a plurality of solder masks for soldering. Green paint (solder mask) 140. The wire 130 is wire bonding, and is electrically connected to two chips (not shown) added to the substrate 110. The solder resist green paint 14 〇 is the main body 115 and the wire 13G. The main body 115 is generally made of resin, jade, and dimensional reinforced BT (bismaieimide-triazine) resin, ceramic materials and other materials. One of the main body of the substrate 110, 15 on the other There are a plurality of strip-shaped metal strips 25 and surrounding metal strips 126, which are respectively arranged at the corners of the main body 115, under the solder-resistant green paint 140. The surrounding metal strips 126 and each of the _ strips = 5 The ^ ends are connected and surround the metal strip 125, so that the metal strip ^ ::. And the metal ητ 1 26 form a mesh shape. The individual metal strip 125 and the metal strip 26 are electrically connected. With this, the metal strip 1 2 5 and the metal strip 1 2 6 can be used as ground or power contacts to enhance the electrical properties of the substrate 110. Characteristics, and help to dissipate the heat generated during the operation of the ball grid array package construction. Of course, those skilled in the art should understand that the number of metal strips 1 2 5 and metal strips 1 2 6 can be reduced as needed, and That is, some corners of the substrate 110 do not have the metal strip 125 and the metal strip 126. Referring to FIG. 6 again, the green paint 140 is located at the plurality of wires 130.
531816 五、發明說明(5) " 上表面143具有複數個凹處151,且位於該金屬條125處, 该綠漆140之上表面142具有複數個凹處15〇。由於該金屬 條125之尺寸與間隔係大體上等於該主體115上之複數個導 線130之尺寸與間隔,故該上表面143處之該凹處151之外 形與尺寸將大體上等同於該上表面142處之該凹處15〇。當 然,若而要,例如提高散熱及電性特性,該金屬條1 2 5與 該金屬帶126之尺寸與間隔亦可不同於該導線13〇之尺寸盥 間隔。 如可所述,在注膠過程中,該凹處15〇、151提供相當良 好之排氣作用’使得封膠塑料能夠完全填充於該模穴中。 此外,由^提供該金屬條125及金屬帶126使該防焊綠漆表 面142之咼度大體上與該導線13〇及其周圍之防焊綠漆表面 1 4 3相同,故旎緊靠該模具並避免注膠過程中的溢膠情 況。再著,當於模造注膠的過程中,該模具可平均的抵住 該綠漆140之上表面142及143,使該封膠塑料不致於^^據 或產生未填滿之缺陷。 %/ 精於本技藝者將可瞭解,本發明之金屬條125及金屬帶 126,—可配置於該基板之周邊任何未具有導線之任何區域 上,籍此使4基板之綠漆表面具有均勻之凹處,以提^共、、主 膠過程之排氣作用並防止注膠過程之溢膠。 〆 第7圖顯示一具有根據本發明之基板丨丨〇之半導體封 造30 0,該金屬條125及金屬帶126係位於該基板11〇之^ 落。第8圖所示為沿著第7圖之剖線8_8之剖面圖,一 體晶片2 0 0係加裝於該基板丨丨〇上,並藉由複數條連接線531816 V. Description of the invention (5) " The upper surface 143 has a plurality of recesses 151 and is located at the metal strip 125, and the upper surface 142 of the green paint 140 has a plurality of recesses 150. Since the size and spacing of the metal strip 125 is substantially equal to the size and spacing of the plurality of wires 130 on the main body 115, the outer shape and size of the recess 151 at the upper surface 143 will be substantially equal to the upper surface The recess is 152 at 142. Of course, if it is desired, for example, to improve heat dissipation and electrical characteristics, the size and spacing of the metal strip 1 2 5 and the metal strip 126 may also be different from the size of the lead wire 130. As can be mentioned, during the injection process, the recesses 15 and 151 provide a relatively good venting effect 'so that the sealing plastic can be completely filled in the cavity. In addition, the metal strip 125 and the metal strip 126 are provided to make the thickness of the solder mask green paint surface 142 substantially the same as that of the wire 13 and the solder mask green paint surface 1 4 3 around it, so Mold and avoid spillage during the injection process. Furthermore, during the molding and injection molding process, the mold can evenly resist the upper surfaces 142 and 143 of the green paint 140, so that the sealant plastic will not cause ^^ or unfilled defects. % / Those skilled in the art will understand that the metal strip 125 and metal strip 126 of the present invention can be arranged on any area around the substrate without any wires, thereby making the green paint surface of the 4 substrate uniform. The recess is used to improve the venting effect of the main and main glue process and prevent the overflow of glue during the injection process. Figure 7 shows a semiconductor package 300 with a substrate according to the present invention. The metal strip 125 and the metal strip 126 are located on the substrate 110. Fig. 8 is a cross-sectional view taken along the section line 8_8 of Fig. 7. A chip 200 is mounted on the substrate 丨 丨 0, and a plurality of connecting lines are used.
00483.ptd 第9頁 531816 五、發明說明(6) 2 2 2以打線電氣連接至該基板1丨〇上之該複數個導線丨3 〇 上。該基板110上亦提供多個錫球(s〇lde]r ball) 160,用 以與外部之基板11 〇電氣連接。之後,一封膠體2 2 〇係包封 該半導體晶片2 0 0,而形成該球格陣列半導體封裝構造。 現請參考第9及1 0圖,其中顯示根據本發明之另一實施 例之基板310,類似於圖5及6圖所示之該基板U〇且類似的 元件標示相同的圖號。相較於圖5及6圖所示之該基板 11 0,該基板31 0具有一金屬塊320,以取代該基板11 〇之該 金屬條125及金屬帶126,該金屬塊丨20具有複數個條狀突 起1 21,且每一該突起1 21之間隔係大體上等於該主體丨工5 上之複數個導線1 30之間隔。如此,此一基板丨丨〇之該綠漆 1 4 0之該上表面亦具有複數個凹處丨5 〇,而亦提供相去 之排氣作用。 胃 雖然本發明已以前述較佳實施例揭示,然其並非用以 ^本發明,任何熟習此技藝者,在不脫離本發明之精神轟 範圍内,當可作各種之更動與修改。因此本發明之保^ 圍當視後附之申請專利範圍所界定者為準。00483.ptd Page 9 531816 V. Description of the invention (6) 2 2 2 is electrically connected to the plurality of wires 丨 3 on the substrate 1 丨 0 by wiring. A plurality of solder balls 160 are also provided on the substrate 110 to be electrically connected to the external substrate 110. After that, a colloid 2 2 0 encapsulates the semiconductor wafer 2000 to form the ball grid array semiconductor package structure. Please refer to Figs. 9 and 10, which shows a substrate 310 according to another embodiment of the present invention. Similar elements to the substrate U0 shown in Figs. 5 and 6 are indicated by the same drawing numbers. Compared to the substrate 11 0 shown in FIGS. 5 and 6, the substrate 3 10 has a metal block 320 to replace the metal strip 125 and the metal strip 126 of the substrate 110. The metal block 20 has a plurality of The strip-shaped protrusions 1 21 and the interval between each of the protrusions 1 21 are substantially equal to the interval between the plurality of wires 1 30 on the main body 5. In this way, the upper surface of the green paint 14 of the substrate 丨 〇 0 also has a plurality of recesses 501, and also provides a degassing effect. Stomach Although the present invention has been disclosed in the foregoing preferred embodiments, it is not intended to be used in the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit of the present invention. Therefore, the protection of the present invention shall be determined by the scope of the appended patent application.
00483.ptd 第10頁 531816 圖式簡單說明 【圖示說明】 第1圖:為具有習用平面金屬片之一基板之正視圖。 第2圖:為沿著第1圖之剖線2-2之基板之剖面圖。 第3圖:為不具有該習用平面金屬片之一基板之正視 圖。 第4圖:為沿著第3圖之剖線4-4之基板之剖面圖。 第5圖:為根據本發明之一具有條狀金屬條之基板之正 視圖。 第6圖:為沿著第5圖之剖線5-5之基板之剖面圖。 第7圖:為根據本發明之半導體封裝構造之剖面視圖。 第8圖:所示為沿著第7圖之剖線8-8之半導體封裝構造 之剖面圖。 第9圖:為根據本發明之另一實施例之具有金屬塊之基 板之正視圖。00483.ptd Page 10 531816 Brief description of the drawings [Illustration] Figure 1: A front view of a substrate with a conventional flat metal sheet. FIG. 2 is a cross-sectional view of the substrate along section line 2-2 of FIG. 1. Fig. 3: A front view of a substrate without the conventional planar metal sheet. FIG. 4 is a cross-sectional view of the substrate along section line 4-4 of FIG. 3. Fig. 5 is a front view of a substrate having strip-shaped metal strips according to the present invention. FIG. 6 is a cross-sectional view of the substrate along section line 5-5 of FIG. 5. FIG. 7 is a cross-sectional view of a semiconductor package structure according to the present invention. Fig. 8: A cross-sectional view of the semiconductor package structure taken along section line 8-8 of Fig. 7. Fig. 9 is a front view of a substrate having a metal block according to another embodiment of the present invention.
第1 0圖:為沿著第9圖之剖線1 0 - 1 0之基板之剖面圖 【圖號說明】 10 基 板 15 主 體 20 平 面 金 屬 片 30 導 線 40 防 焊 綠 漆 42 防 焊 綠漆表面 43 防 焊 綠 漆 表面 50 凹 處 110 基 板 115 主 體 121 突 起 125 金 屬 條 126 金 屬 帶Fig. 10: Sectional view of the substrate along the section line 10-10 of Fig. 9 [Illustration of the drawing number] 10 Substrate 15 Main body 20 Flat metal sheet 30 Lead 40 Anti-solder green paint 42 Anti-solder green paint surface 43 solder-resistant green paint surface 50 recess 110 substrate 115 main body 121 protrusion 125 metal strip 126 metal strip
00483.ptd 第11頁 53181600483.ptd Page 11 531816
圖式簡單說明 130 導線 140 防焊綠漆 142 防焊綠漆表面 143 防焊綠漆表面 150 凹處 151 凹處 160 錫球 200 晶片 220 封膠體 222 連接線 300 半導體封裝構造 310 基板 320 金屬塊 321 突起 00483.ptd 第12頁Brief description of the drawing 130 wire 140 solder-resistant green paint 142 solder-resistant green paint surface 143 solder-resistant green paint surface 150 recess 151 recess 160 solder ball 200 chip 220 sealant 222 connection line 300 semiconductor package structure 310 substrate 320 metal block 321 00483.ptd Page 12
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW91106113A TW531816B (en) | 2002-03-26 | 2002-03-26 | Semiconductor package substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW91106113A TW531816B (en) | 2002-03-26 | 2002-03-26 | Semiconductor package substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
TW531816B true TW531816B (en) | 2003-05-11 |
Family
ID=28788561
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW91106113A TW531816B (en) | 2002-03-26 | 2002-03-26 | Semiconductor package substrate |
Country Status (1)
Country | Link |
---|---|
TW (1) | TW531816B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104022087A (en) * | 2013-02-28 | 2014-09-03 | 阿尔特拉公司 | Heat spreading in molded semiconductor packages |
-
2002
- 2002-03-26 TW TW91106113A patent/TW531816B/en not_active IP Right Cessation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104022087A (en) * | 2013-02-28 | 2014-09-03 | 阿尔特拉公司 | Heat spreading in molded semiconductor packages |
US9870978B2 (en) | 2013-02-28 | 2018-01-16 | Altera Corporation | Heat spreading in molded semiconductor packages |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7971351B2 (en) | Method of manufacturing a semiconductor device | |
US6660558B1 (en) | Semiconductor package with molded flash | |
US7399658B2 (en) | Pre-molded leadframe and method therefor | |
US9570405B2 (en) | Semiconductor device and method for manufacturing same | |
US8351217B2 (en) | Wiring board | |
US7288440B2 (en) | Method of manufacturing a semiconductor device | |
US20030045030A1 (en) | Method of manufacturing a semiconductor device | |
US20070273019A1 (en) | Semiconductor package, chip carrier structure thereof, and method for fabricating the chip carrier | |
KR20170092096A (en) | Manufacturing apparatus of electronic component and manufacturing method and electronic component | |
JP4068336B2 (en) | Semiconductor device | |
US9099294B1 (en) | Molded leadframe substrate semiconductor package | |
CN101236963B (en) | Semiconductor device and packaging structure therefor | |
JP2004528729A (en) | A resin package having a plurality of semiconductor chips and a wiring board, and a method of manufacturing the resin package using an injection mold | |
JP2000031343A (en) | Semiconductor device | |
JP4001608B2 (en) | Semiconductor device and manufacturing method of semiconductor device | |
TW531816B (en) | Semiconductor package substrate | |
US10186432B2 (en) | Method for manufacturing semiconductor device | |
JP2010141261A (en) | Intermediate structure for semiconductor device and method for manufacturing intermediate structure | |
KR101239117B1 (en) | Power semiconductor package and method for fabricating the same | |
US8039941B2 (en) | Circuit board, lead frame, semiconductor device, and method for fabricating the same | |
JP2008153491A (en) | Method for manufacturing semiconductor device | |
US20060091567A1 (en) | Cavity-down Package and Method for Fabricating the same | |
JP4823161B2 (en) | Semiconductor device | |
TW200522300A (en) | Chip package sturcture | |
JP3964438B2 (en) | Semiconductor device and manufacturing method of semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GD4A | Issue of patent certificate for granted invention patent | ||
MK4A | Expiration of patent term of an invention patent |