JP3964438B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Semiconductor device and manufacturing method of semiconductor device Download PDF

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JP3964438B2
JP3964438B2 JP2005187175A JP2005187175A JP3964438B2 JP 3964438 B2 JP3964438 B2 JP 3964438B2 JP 2005187175 A JP2005187175 A JP 2005187175A JP 2005187175 A JP2005187175 A JP 2005187175A JP 3964438 B2 JP3964438 B2 JP 3964438B2
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substrate
semiconductor device
resin
mold
semiconductor
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JP2007005730A (en
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好美 高橋
正純 雨海
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日本テキサス・インスツルメンツ株式会社
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Priority to JP2005187175A priority Critical patent/JP3964438B2/en
Priority to US11/426,622 priority patent/US7520052B2/en
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Publication of JP3964438B2 publication Critical patent/JP3964438B2/en
Priority to US12/400,474 priority patent/US7971351B2/en
Priority to US13/114,554 priority patent/US8304883B2/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can individually mold a plurality of semiconductor chips mounted on a single face of a substrate. <P>SOLUTION: The semiconductor device manufacturing method consists of steps of arranging a plurality of semiconductor elements 102 on the surface of a substrate 100; fixing the rear face side of the substrate 100 on a lower metal mold 130; supplying a liquid resin 114 to each semiconductor element 102 from a nozzle 112 so that at least part of each semiconductor element 102 is covered by the liquid resin 114; pressing an upper metal mold formed with a plurality of cavities 144 on one surface against the lower metal mold and then molding the liquid resin 114 by these cavities 144 at a predetermined temperature; and separating the cavities 144 of the upper metal mold 140 from the substrate to form a plurality of individual mold resins, as a lump on the substrate. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

本発明は、基板上の一面に搭載された複数の半導体チップを樹脂封止するための方法に関し、特に、半導体装置の小型化、薄型化に適応することができるモールド方法に関する。   The present invention relates to a method for resin-sealing a plurality of semiconductor chips mounted on one surface of a substrate, and more particularly to a molding method that can be adapted to miniaturization and thinning of a semiconductor device.

携帯電話、携帯型コンピュータ、その他の小型電子機器の普及に伴って、これらに搭載する半導体装置の小型化・薄型化の要求が高まっている。こうした要求に応えるべく、ＢＧＡパッケージやＣＳＰパッケージが開発され、実用化されている。   With the widespread use of cellular phones, portable computers, and other small electronic devices, there is an increasing demand for smaller and thinner semiconductor devices mounted on them. In order to meet these requirements, BGA packages and CSP packages have been developed and put into practical use.

特許文献１は、ＢＧＡパッケージに関する。図１３に示すように、ポリイミド製の絶縁フィルム基板３の表面には、半導体チップ２と半田バンプ７とを電気的に接続するための多数の銅パターン４が形成されている。各銅パターン４の一端は、絶縁基板３に形成されたビアホール３ａを介して半田バンプ７と接続され、銅パターン４の他端は、半導体チップ２の電極パッド２ａから伸びる導体ワイヤ５の一端が接続されている。銅パターン４を含む絶縁基板３上には、エポキシ系樹脂からなる半田レジスト６が塗布されている。半導体チップ２は、ダイアタッチテープ８上に接着され、そして、トランスファーモールド法により成型されたモールド樹脂９内に封止されている。   Patent Document 1 relates to a BGA package. As shown in FIG. 13, a large number of copper patterns 4 for electrically connecting the semiconductor chip 2 and the solder bumps 7 are formed on the surface of the polyimide insulating film substrate 3. One end of each copper pattern 4 is connected to a solder bump 7 through a via hole 3a formed in the insulating substrate 3. The other end of the copper pattern 4 is one end of a conductor wire 5 extending from the electrode pad 2a of the semiconductor chip 2. It is connected. On the insulating substrate 3 including the copper pattern 4, a solder resist 6 made of an epoxy resin is applied. The semiconductor chip 2 is bonded onto the die attach tape 8 and sealed in a mold resin 9 molded by a transfer molding method.

また、特許文献２は、基板の一方の面に複数の半導体チップがマトリクス状に搭載された被成形品を樹脂モールドするモールド金型及び該モールド金型を用いた樹脂モールド方法に関するものである。図１４（ｂ）は、ＱＦＮ（Quad Flat Non-leaded）タイプの半導体パッケージを例示したものである。被成形品であるリードフレーム５６の一方の面にはダイパッド部５７に半導体チップ５２がマトリクス状に搭載されている。各半導体チップ５２と周囲のリード部５８とがワイヤボンディングされて、半導体チップ５２の電極部と端子接続部となるリード部５８の一方の面とがボンディングワイヤ５４により電気的に接続されている。樹脂基板５１やリードフレーム５６は下型５９に搭載された際に、キャビティ凹部６０にマトリクス状に搭載された半導体チップ５２が収容される。樹脂基板５１やリードフレーム５６は、上型６１と下型５９とで基板周縁部がクランプされ、モールド樹脂が下型ランナゲート６２を通じてキャビティ凹部６０に充填されて一方の面が一括して樹脂モールドされる。樹脂モールド後、成形品（樹脂基板５１やリードフレーム５６）は、半導体チップ毎にダイシングされて個片に切断されて半導体装置が製造される。Ｃがダイサーカットラインである。   Patent Document 2 relates to a mold for resin-molding a molded product in which a plurality of semiconductor chips are mounted in a matrix on one surface of a substrate, and a resin molding method using the mold. FIG. 14B illustrates a QFN (Quad Flat Non-leaded) type semiconductor package. A semiconductor chip 52 is mounted in a matrix on a die pad portion 57 on one surface of a lead frame 56 that is a molded product. Each semiconductor chip 52 and the surrounding lead portion 58 are wire-bonded, and the electrode portion of the semiconductor chip 52 and one surface of the lead portion 58 serving as a terminal connection portion are electrically connected by a bonding wire 54. When the resin substrate 51 and the lead frame 56 are mounted on the lower mold 59, the semiconductor chips 52 mounted in a matrix in the cavity recesses 60 are accommodated. The resin substrate 51 and the lead frame 56 are clamped at the periphery of the substrate by the upper mold 61 and the lower mold 59, and the mold resin is filled into the cavity recess 60 through the lower mold runner gate 62, so that one surface is collectively molded into the resin mold. Is done. After the resin molding, the molded product (the resin substrate 51 and the lead frame 56) is diced for each semiconductor chip and cut into individual pieces to manufacture a semiconductor device. C is a dicer cut line.

特開２０００−３１３２７号JP 2000-31327 A 特開２００３−２３４３６５号JP 2003-234365 A

しかしながら、上記従来のモールド方法には次のような課題がある。図１４に示すように、基板の一面に搭載された複数の半導体チップを一括してモールドした場合、ダイサーカットＣの線上でモールド樹脂を切断するため、モールド樹脂の切断面にクラックが生じたり、また、切断に伴いパーティクル等が発生してしまう。さらに、複数の半導体チップを一括してモールドするに際し、隣接する半導体チップ間にまで不必要な樹脂を供給しなければならず、使用する樹脂に無駄が生じている。このことは、モールド樹脂の外形の小型化、薄型化にとっての障害にもなり得る。   However, the conventional molding method has the following problems. As shown in FIG. 14, when a plurality of semiconductor chips mounted on one surface of the substrate are molded together, the mold resin is cut on the dicer cut C line, so that a crack occurs on the cut surface of the mold resin, In addition, particles and the like are generated along with the cutting. Furthermore, when molding a plurality of semiconductor chips at a time, an unnecessary resin must be supplied between adjacent semiconductor chips, and the resin used is wasted. This can be an obstacle to downsizing and thinning of the outer shape of the mold resin.

また、ＩＣパッケージを積み重ねる部品実装形態が普及しつつある。積み重ねたＩＣパッケージは、マザー基板に実装される際にリフロー炉を通るため、高温に晒され、これが原因で、パッケージに使用されている主材料の熱膨張係数の差により機械的な反りが発生する。この反りによりパッケージの端子（はんだボール）がマザー基板の端子と接触する機会を失い、接合不良となる不具合が発生している。   In addition, component mounting forms in which IC packages are stacked are becoming widespread. Stacked IC packages pass through a reflow oven when mounted on a mother board, and are therefore exposed to high temperatures. This causes mechanical warping due to differences in the thermal expansion coefficients of the main materials used in the package. To do. Due to this warpage, the package terminal (solder ball) loses the opportunity to contact the mother board terminal, resulting in a problem of poor bonding.

積層されるＩＣパッケージは、一般的にトランスファーモールドが用いられているが、この工法では、高温時に液化した樹脂をゲートと呼ばれる注入口から注入し、樹脂の仮硬化後にゲートを機械的に切断し、単体のモールド成形部が構成される。ゲートは機械的に切断されるので、パッケージの外形寸法精度や外観に不具合をもたらす。さらに、樹脂封止後に、樹脂残りが発生し、ＩＣパッケージを積層する際に実装不良の要因となり得る課題を有していた。   Generally, transfer molds are used for stacked IC packages. In this method, resin liquefied at high temperatures is injected from an injection port called a gate, and the gate is mechanically cut after the resin is temporarily cured. A single molded part is formed. Since the gate is mechanically cut, it causes defects in the external dimension accuracy and appearance of the package. Furthermore, after resin sealing, a resin residue is generated, which has a problem that may cause a mounting failure when stacking IC packages.

本発明は、上記従来の課題を解決し、基板の一面に搭載された複数の半導体チップを個別にモールドすることが可能な半導体装置の製造方法を提供することを目的とする。
さらに本発明の目的は、基板の一面に搭載された複数の半導体チップのモールド樹脂を小型化、薄型化することができる半導体装置の製造方法を提供する。
さらに本発明の目的は、モールド樹脂が形成された基板の一面上に他の表面実装型の半導体装置を積層することができる半導体装置およびその製造方法を提供することを目的とする。 An object of the present invention is to solve the above conventional problems and to provide a method for manufacturing a semiconductor device capable of individually molding a plurality of semiconductor chips mounted on one surface of a substrate.
Furthermore, the objective of this invention provides the manufacturing method of the semiconductor device which can reduce in size and thickness the mold resin of the several semiconductor chip mounted in the one surface of a board | substrate.
Another object of the present invention is to provide a semiconductor device in which another surface-mount type semiconductor device can be stacked on one surface of a substrate on which a mold resin is formed, and a method for manufacturing the same.

本発明に係る、基板上に搭載された半導体素子を樹脂封止する半導体装置の製造方法は、基板の第１の主面上に複数の半導体素子を配し、基板の第１の主面と対向する第２の主面を支持部材（下部金型）上に固定し、各半導体素子の少なくとも１部を覆うように、各半導体素子のそれぞれに液状樹脂を供給し、一面に複数の凹部（キャビティ）が形成された型形成部材（上部金型）を支持部材に対して押圧し、一定の温度下において各凹部により各半導体素子の液状樹脂をモールドし、型形成部材の凹部を基板から離脱させるステップを含み、液状樹脂のガラス転移点が１００〜１６０℃であり、ガラス転移点以下の温度領域での線膨張係数（ＣＴＥ１）が２０〜３０ｐｐｍ、ガラス転移点を越える温度領域での線膨張係数（ＣＴＥ２）が８０〜１２０ｐｐｍ、ガラス転移点以下の温度領域での縦弾性率（ＹＭ１）が１〜２０ＧＰａ、ガラス転移点を越える温度領域での縦弾性率（ＹＭ２）が０．１〜１．０ＧＰａである。また、ガラス転移点、ＣＴＥ１、ＣＴＥ２、ＹＭ１、ＹＭ２は、それぞれ、１３０〜１６０℃、２４〜２５ｐｐｍ、９０〜１００ｐｐｍ、９〜１１ＧＰａ、０．２〜０．５ＧＰａであることが好ましい。好ましくは、基板の線膨張係数は、３０〜２００℃の温度範囲において約１７ｐｐｍである。   According to the present invention, a method of manufacturing a semiconductor device for resin-sealing a semiconductor element mounted on a substrate includes arranging a plurality of semiconductor elements on a first main surface of the substrate, The opposing second main surface is fixed on a support member (lower mold), liquid resin is supplied to each of the semiconductor elements so as to cover at least one part of each semiconductor element, and a plurality of concave portions ( The mold forming member (upper mold) in which the cavity is formed is pressed against the support member, the liquid resin of each semiconductor element is molded by each recess at a constant temperature, and the recess of the mold forming member is detached from the substrate. The glass transition point of the liquid resin is 100 to 160 ° C., the linear expansion coefficient (CTE1) in the temperature region below the glass transition point is 20 to 30 ppm, and the linear expansion in the temperature region exceeding the glass transition point. The coefficient (CTE2) is 8 ～120Ppm, longitudinal elastic modulus at a temperature region below the glass transition point (YM1) is 1～20GPa, longitudinal elastic modulus at a temperature region exceeding the glass transition point (YM2) is 0.1～1.0GPa. Moreover, it is preferable that glass transition point, CTE1, CTE2, YM1, and YM2 are 130-160 degreeC, 24-25 ppm, 90-100 ppm, 9-11 GPa, and 0.2-0.5 GPa, respectively. Preferably, the linear expansion coefficient of the substrate is about 17 ppm in the temperature range of 30-200 ° C.

製造方法はさらに、モールドされた半導体素子の領域に応して基板を切断するステップ、基板の第２の主面に接続端子を取り付けるステップ、基板の第１の主面上に他の半導体装置を積層するステップ、基板の第２の主面に接続された接続端子をマザー基板に接続するステップを含むものであってもよい。   The manufacturing method further includes a step of cutting the substrate in accordance with a region of the molded semiconductor element, a step of attaching a connection terminal to the second main surface of the substrate, and another semiconductor device on the first main surface of the substrate. The step of laminating may include a step of connecting a connection terminal connected to the second main surface of the substrate to the mother substrate.

好ましくは、本発明に係る半導体装置は、上記製造方法で製造されたモールド樹脂を含む基板と、モールド樹脂内に封止された半導体素子とを含む。半導体装置は、基板の第１の主面上には配線パターンが形成され、他の半導体装置の裏面に形成された複数の接続端子が前記配線パターンに電気的に接続される、ＰＯＰ構造とすることができる。他の半導体装置の接続端子は、モールド樹脂の外周に配され、モールド樹脂は、当該基板と他の半導体装置との間に配されている。   Preferably, a semiconductor device according to the present invention includes a substrate including a mold resin manufactured by the above manufacturing method and a semiconductor element sealed in the mold resin. The semiconductor device has a POP structure in which a wiring pattern is formed on the first main surface of the substrate, and a plurality of connection terminals formed on the back surface of the other semiconductor device are electrically connected to the wiring pattern. be able to. The connection terminals of the other semiconductor devices are arranged on the outer periphery of the mold resin, and the mold resin is arranged between the substrate and the other semiconductor device.

好ましくは、液状樹脂が成型されたときのモールド樹脂の占有面積は、基板表面の面積の少なくとも６１％以下である。例えば、基板上のモールドするエリアが、１０．９×１０．９ｍｍ、パッケージサイズが１４×１４ｍｍの比から算出される。   Preferably, the area occupied by the mold resin when the liquid resin is molded is at least 61% of the area of the substrate surface. For example, the area to be molded on the substrate is calculated from a ratio of 10.9 × 10.9 mm and the package size is 14 × 14 mm.

支持部材または型形成部材の温度を約１５０度に保持し、液状樹脂をモールドする。この際、型形成部材の複数の凹部に、可撓性のリリースフィルムを密着させるようにしてもよい。リリースフィルムは、モールド樹脂の離形材として機能する。フィルムの軟化温度は、液状樹脂をモールドするときの温度に近いものとすることが望ましい。さらに、フィルムの複数の凹部に接する面は、粗さ加工が施されている。また、フィルムは、基板に形成された段差を被覆できるように、少なくとも５０μｍの厚さを有することが望ましい。フィルムは、例えば熱可塑性フッ素樹脂（ＥＴＦＥ）である。   The temperature of the support member or mold forming member is maintained at about 150 degrees, and the liquid resin is molded. At this time, a flexible release film may be brought into close contact with the plurality of concave portions of the mold forming member. The release film functions as a mold resin release material. The softening temperature of the film is desirably close to the temperature at which the liquid resin is molded. Furthermore, the surface which contacts the some recessed part of a film is roughened. Further, it is desirable that the film has a thickness of at least 50 μm so as to cover the step formed on the substrate. The film is, for example, a thermoplastic fluororesin (ETFE).

製造方法はさらに、型形成部材の凹部により液状樹脂をモールドする前に、液状樹脂の雰囲気を真空に引くステップを有することが望ましい。半導体素子の雰囲気を真空にすることで、モールド樹脂内に気泡やボイドなどの発生を抑制することができる。絶対真空度は、少なくとも５キロパスカル［ｋＰａ］である。   It is desirable that the manufacturing method further includes a step of evacuating the atmosphere of the liquid resin before molding the liquid resin by the concave portion of the mold forming member. By making the atmosphere of the semiconductor element a vacuum, it is possible to suppress the generation of bubbles and voids in the mold resin. The absolute vacuum is at least 5 kilopascals [kPa].

本発明によれば、基板の一面に形成された複数の半導体素子を一括して、かつ個別に樹脂封止することができるため、より薄型化、小型化の半導体装置を提供することができる。さらに、複数の半導体素子を個別に樹脂封止するので、モールド樹脂の無駄をなくすことができる。同時に、モールド樹脂をダイシングすることなく個別の半導体装置を得ることができるため、モールド樹脂に切断時のせん断応力等が直接印加されることがない。従って、モールド樹脂にクラック等が生じることがなく、モールド樹脂の寸法精度を安定化させ、外観を高品質に保つことができる。   According to the present invention, since a plurality of semiconductor elements formed on one surface of a substrate can be collectively and individually resin-sealed, a thinner and smaller semiconductor device can be provided. Furthermore, since a plurality of semiconductor elements are individually resin-sealed, it is possible to eliminate the waste of mold resin. At the same time, an individual semiconductor device can be obtained without dicing the mold resin, so that shear stress or the like during cutting is not directly applied to the mold resin. Therefore, cracks or the like do not occur in the mold resin, the dimensional accuracy of the mold resin can be stabilized, and the appearance can be kept high.

以下、本発明の最良の実施形態について図面を参照して詳細に説明する。   DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the best embodiment of the present invention will be described in detail with reference to the drawings.

図１（ａ）は、複数の半導体チップを搭載した基板の平面図、図１（ｂ）は、そのＡ−Ａ線断面図である。本実施例では、基板１００の一面に複数の半導体チップがマトリックス状に配置されている。基板１００は、その構成を特に限定するものではないが、多層配線基板やフィルム基板を用いることができる。例えば、ガラスエポキシ樹脂、ポリイミド樹脂等の絶縁基板を用いる。半導体チップ１０２は、ダイアタッチ等を介して基板１００の所定位置に取り付けられる。半導体チップ１０２の電極は、ボンディングワイヤ１０４により基板１００の表面に形成された銅パターンに接続されている。   FIG. 1A is a plan view of a substrate on which a plurality of semiconductor chips are mounted, and FIG. 1B is a cross-sectional view taken along line AA. In this embodiment, a plurality of semiconductor chips are arranged in a matrix on one surface of the substrate 100. Although the board | substrate 100 does not specifically limit the structure, a multilayer wiring board and a film board | substrate can be used. For example, an insulating substrate such as glass epoxy resin or polyimide resin is used. The semiconductor chip 102 is attached to a predetermined position of the substrate 100 via a die attach or the like. The electrodes of the semiconductor chip 102 are connected to a copper pattern formed on the surface of the substrate 100 by bonding wires 104.

次に、図１に示す基板上に搭載された半導体チップ１０２を一括に、かつ個別にモールドする方法について説明する。図２に示すように、液状樹脂を充填した供給部１１０を基板１００の長手方向Ｐに走査し、先端のノズル１１２から液状樹脂１１４を基板１００上に供給する。このとき、ノズル１１２からは、個々の半導体チップ１０２の表面を覆うように液状樹脂１１４が断続的に供給される。これにより、半導体チップ１０２の隣接する領域１１６には、液状樹脂１１４が供給されず、そこから基板が露出される。液状樹脂１１４の供給量は、モールド樹脂の寸法精度を左右するものであるから、非常に精度良く制御する必要がある。好ましくは、後述する上部金型１４０のキャビティ１４４の体積の±３％の範囲内で液状樹脂１１４が供給される。   Next, a method for molding the semiconductor chips 102 mounted on the substrate shown in FIG. 1 collectively and individually will be described. As shown in FIG. 2, the supply unit 110 filled with the liquid resin is scanned in the longitudinal direction P of the substrate 100, and the liquid resin 114 is supplied onto the substrate 100 from the nozzle 112 at the tip. At this time, the liquid resin 114 is intermittently supplied from the nozzle 112 so as to cover the surface of each semiconductor chip 102. Thereby, the liquid resin 114 is not supplied to the adjacent region 116 of the semiconductor chip 102, and the substrate is exposed therefrom. Since the supply amount of the liquid resin 114 affects the dimensional accuracy of the mold resin, it needs to be controlled with very high accuracy. Preferably, the liquid resin 114 is supplied within a range of ± 3% of the volume of the cavity 144 of the upper mold 140 described later.

液状樹脂１１４の特性として、室温では液状であり、その粘度は、約３０〜１５０パスカル秒［Ｐａ ｓ］である。より望ましくは４５パスカル秒である。液状樹脂１１４に一定の粘度を持たせることで、ノズルから供給された液状樹脂１１４が半導体チップ１０２の全体を好適に被覆することができる。液状樹脂１１４は、例えば、エポキシ樹脂を用いることができ、速乾性を有するものであってもよい。   The liquid resin 114 is liquid at room temperature and has a viscosity of about 30 to 150 Pascal seconds [Pa s]. More desirably, it is 45 Pascal seconds. By giving the liquid resin 114 a certain viscosity, the liquid resin 114 supplied from the nozzle can suitably cover the entire semiconductor chip 102. For example, an epoxy resin can be used as the liquid resin 114, and the liquid resin 114 may have a quick drying property.

次に、図３に示すように、基板１００を下部金型１３０上にセットする。下部金型１３０には、好ましくは、基板１００を位置決めするためのピン等が設けられている。本実施例では、半導体チップ１０２上に液状樹脂１１４を供給した基板を下部金型１３０にセットするようにしたが、これに限らず、下部金型１３０に基板１０２をセットした状態で、液状樹脂１１４を半導体チップ１０２上に供給するようにしてもよい。   Next, as shown in FIG. 3, the substrate 100 is set on the lower mold 130. The lower mold 130 is preferably provided with pins or the like for positioning the substrate 100. In this embodiment, the substrate supplied with the liquid resin 114 on the semiconductor chip 102 is set in the lower mold 130. However, the present invention is not limited to this, and the liquid resin is set in a state where the substrate 102 is set in the lower mold 130. 114 may be supplied onto the semiconductor chip 102.

次に、上部金型１４０の押圧面側にリリースフィルム１４２が準備される。上部金型１４０の押圧面側には、複数の凹部すなわちキャビティ１４４が形成されている。これらのキャビティ１４４は、下部金型に固定された基板上の半導体チップ１０２の位置に対応している。各キャビティ１４４内には押圧部材１４６が収容され、押圧部材１４６はバネ１４８により弾性的に支持されている。キャビティ１４４は、脚部１５２の側面と押圧部材１４６の押圧面によって包囲された矩形状の窪みであって、成型されるモールド樹脂の外形を規定する。脚部１５２の側面および押圧部材１４６の押圧面によって包囲されたキャビティ１４４の寸法は、例えば、幅１０．９ｍｍ、奥行き１０．９ｍｍ、高さ０．２７ｍｍである。また、半導体チップ１０２の寸法は、例えば、幅８．８ｍｍ、奥行き８．６ｍｍ、高さ０．１ｍｍである。   Next, a release film 142 is prepared on the pressing surface side of the upper mold 140. A plurality of recesses, that is, cavities 144 are formed on the pressing surface side of the upper mold 140. These cavities 144 correspond to the position of the semiconductor chip 102 on the substrate fixed to the lower mold. A pressing member 146 is accommodated in each cavity 144, and the pressing member 146 is elastically supported by a spring 148. The cavity 144 is a rectangular recess surrounded by the side surface of the leg portion 152 and the pressing surface of the pressing member 146, and defines the outer shape of the molded resin to be molded. The dimensions of the cavity 144 surrounded by the side surface of the leg 152 and the pressing surface of the pressing member 146 are, for example, a width of 10.9 mm, a depth of 10.9 mm, and a height of 0.27 mm. The dimensions of the semiconductor chip 102 are, for example, a width of 8.8 mm, a depth of 8.6 mm, and a height of 0.1 mm.

さらに上部金型１４０には、各キャビティ１４４に連通する吸気孔１５０が形成されている。この吸気孔１５０から空気を吸気させることで、リリースフィルム１４２が、上部金型１４０のキャビティ１４４の押圧面に倣うように吸着または密着される。   Further, the upper mold 140 is formed with intake holes 150 communicating with the cavities 144. By sucking air from the suction holes 150, the release film 142 is adsorbed or brought into close contact with the pressing surface of the cavity 144 of the upper mold 140.

リリースフィルム１４２は、リール１５４から供給され、リール１５６によって巻き取られるようになっている（図３を参照）。リリースフィルム１４２は、可撓性および耐熱性を有し、加熱された上部金型１４０の温度よりも低い温度で軟化する性質を有することが望ましい。本実施例では、上部金型１４０は、約１５０度に加熱されるため、リリースフィルム１４２の軟化温度は１５０度に近いものが選択される。例えば、熱可塑性フッ素樹脂（ＥＴＦＥ）の可撓性フィルムを用いることができる。   The release film 142 is supplied from the reel 154 and is wound up by the reel 156 (see FIG. 3). The release film 142 desirably has flexibility and heat resistance, and has a property of softening at a temperature lower than the temperature of the heated upper mold 140. In this embodiment, since the upper mold 140 is heated to about 150 degrees, the softening temperature of the release film 142 is selected to be close to 150 degrees. For example, a thermoplastic fluororesin (ETFE) flexible film can be used.

また、リリースフィルム１４２は、少なくとも５０μｍ程度の厚さを有することが望ましい。これは、後述するように、液状樹脂１１４の成型に際し、リリースフィルム１４２が脚部１５２によって基板１００に押圧されるが、このとき、液状樹脂１１４がリリースフィルム１４２と基板１００の接触面から外部へはみ出さないようにするためである。基板１００の表面には、銅パターンおよびソルダレジストが形成され、これらの基板表面からの段差は約２０μｍある。この段差を被覆できるようにリリースフィルム１４２の厚さが５０μｍ以上に選択される。さらに好ましくは、リリースフィルム１４２の一面は、粗さ加工が施される。粗さは、例えば、Ｒｚ：１５μｍである。粗さ加工が施された面は、上部金型１４０に接触される。これにより、液状樹脂の成型後に、上部金型１４０からリリースフィルム１４２が容易に離脱され、リール１５６により巻き取られる。   Further, it is desirable that the release film 142 has a thickness of at least about 50 μm. As will be described later, when the liquid resin 114 is molded, the release film 142 is pressed against the substrate 100 by the legs 152. At this time, the liquid resin 114 is released from the contact surface between the release film 142 and the substrate 100 to the outside. This is to prevent it from protruding. A copper pattern and a solder resist are formed on the surface of the substrate 100, and the step from the substrate surface is about 20 μm. The thickness of the release film 142 is selected to be 50 μm or more so that this step can be covered. More preferably, one surface of the release film 142 is roughened. The roughness is, for example, Rz: 15 μm. The surface subjected to the roughness processing is brought into contact with the upper mold 140. Thereby, after the liquid resin is molded, the release film 142 is easily detached from the upper mold 140 and wound around the reel 156.

次に、図４に示すように、上部金型１４０を下部金型１３０に向けて接近させる。一定の距離まで接近すると、上部金型１４０が下部金型１３０の図示しないオーリングと接触し、それぞれのキャビティ１４２内の空気が排出され、キャビティ１４２内が真空状態に引かれる。絶対真空度は、５キロパスカル［ｋＰａ］以上であることが望ましい。また、上部金型１４０および下部金型１３０は、約１５０度に加熱されている。   Next, as shown in FIG. 4, the upper mold 140 is moved toward the lower mold 130. When approaching a certain distance, the upper mold 140 comes into contact with an O-ring (not shown) of the lower mold 130, the air in each cavity 142 is discharged, and the inside of the cavity 142 is evacuated. The absolute degree of vacuum is desirably 5 kilopascals [kPa] or more. The upper mold 140 and the lower mold 130 are heated to about 150 degrees.

次に、図５に示すように、上部金型１４０が降下され、脚部１５２が基板１００に一定の接圧で当接する。これにより、基板上の各半導体チップを含む領域上に密閉空間が形成される。各キャビティ１４４内の押圧部材１４６は、リリースフィルム１４２を介して弾性的に液状樹脂１１４を加圧成型し、この状態を約１００秒間保つ。この間に、脚部１５２が一定の接圧で基板１００に接触しているため、キャビティ１４４から液状樹脂１１４が外部へはみ出すことはない。こうして、一定温度下で液状樹脂１１４が加圧成型されることで、キャビティ１４４の形状を反映した形状のモールド樹脂が成型される。   Next, as shown in FIG. 5, the upper mold 140 is lowered, and the legs 152 abut against the substrate 100 with a constant contact pressure. As a result, a sealed space is formed on a region including each semiconductor chip on the substrate. The pressing member 146 in each cavity 144 press-molds the liquid resin 114 elastically via the release film 142 and keeps this state for about 100 seconds. During this time, since the leg 152 is in contact with the substrate 100 with a constant contact pressure, the liquid resin 114 does not protrude from the cavity 144 to the outside. In this way, the liquid resin 114 is pressure-molded at a constant temperature, so that a mold resin having a shape reflecting the shape of the cavity 144 is molded.

次に、図６に示すように、上部金型１４０を下部金型１３０から離間させる。リリースフィルム１４２は、上部金型１４０の押圧面から離脱され、リール１４６に巻き取られる。同時に、基板上のモールド樹脂１６０がリリースフィルム１４２から離脱される。基板１００上には、半導体チップの数に相当する数のモールド樹脂１６０が形成され、モールド樹脂１６０は、半導体チップ１０２およびボンディングワイヤ１０４を含む領域を封止する。   Next, as shown in FIG. 6, the upper mold 140 is separated from the lower mold 130. The release film 142 is detached from the pressing surface of the upper mold 140 and wound around the reel 146. At the same time, the mold resin 160 on the substrate is released from the release film 142. A number of mold resins 160 corresponding to the number of semiconductor chips are formed on the substrate 100, and the mold resin 160 seals a region including the semiconductor chips 102 and the bonding wires 104.

次に、図７に示すように、下部金型１３０から基板１００が取り外される。基板１００上には、半導体チップ１０２を封止する非常に薄く、かつ小さな占有面積のモールド樹脂１６０が形成されている。   Next, as shown in FIG. 7, the substrate 100 is removed from the lower mold 130. On the substrate 100, an extremely thin mold resin 160 having a small occupied area for sealing the semiconductor chip 102 is formed.

以降の工程として、基板１００の裏面に接続端子としてのはんだボールを接続する工程、および基板をダイシングする工程が行われる。ダイシング工程では、モールド樹脂１６０とモールド樹脂１６０の間に設定されたダイシングラインＣに沿って基板が切断される。つまり、ダイシング工程においてモールド樹脂１６０が切断されることがないため、モールド樹脂１６０の外形は、キャビティの形状を反映したままの形状で残すことができるため、パーティクルやモールド樹脂のクラック等の発生を抑制することができる。   As subsequent steps, a step of connecting solder balls as connection terminals to the back surface of the substrate 100 and a step of dicing the substrate are performed. In the dicing process, the substrate is cut along a dicing line C set between the mold resin 160 and the mold resin 160. In other words, since the mold resin 160 is not cut in the dicing process, the outer shape of the mold resin 160 can be left in a shape that reflects the shape of the cavity. Can be suppressed.

次に、本発明の第２の実施例について説明する。上記実施例では、上部金型１４０のキャビティ（凹部）１４４の内部形状を矩形状としたが、第２の実施例では、キャビティ１４４のコーナーにチャンファー（面取り）にエアポケットを形成している。   Next, a second embodiment of the present invention will be described. In the above embodiment, the internal shape of the cavity (recess) 144 of the upper mold 140 is rectangular, but in the second embodiment, air pockets are formed in the chamfer (chamfer) at the corner of the cavity 144. .

図８（ａ）は、上部金型１４０の１つの押圧部分を裏面側から見たときの模式的な平面図であり、図８（ｂ）は、チャンファー部分の断面を示す図である。上部金型１４０のキャビティ１４４の各コーナーには、チャンファー１７０が形成されている。さらに、チャンファー１７０には、対角線状に延びる、一定の閉じた内部空間であるエアポケット１８０が連通されている。各コーナーのエアポケット１８０は、真空状態において液状樹脂を成型するときに、ボイドを吸収する機能を有する。すなわち、キャビティ１４４内が真空に引かれた状態から、液状樹脂が加圧成型されると、液状樹脂内の気泡等のボイドがエアポケット１８０の方向に押しやられるため、成型後のモールド樹脂内にボイドが残存し難くなる。   FIG. 8A is a schematic plan view when one pressing portion of the upper mold 140 is viewed from the back side, and FIG. 8B is a diagram showing a cross section of the chamfer portion. A chamfer 170 is formed at each corner of the cavity 144 of the upper mold 140. In addition, the chamfer 170 communicates with an air pocket 180 that is a certain closed internal space extending diagonally. The air pocket 180 at each corner has a function of absorbing voids when a liquid resin is molded in a vacuum state. That is, when the liquid resin is pressure-molded from a state in which the inside of the cavity 144 is evacuated, voids such as bubbles in the liquid resin are pushed in the direction of the air pocket 180, so that the mold resin is molded. Voids are difficult to remain.

図９は、第２の実施例に係る上部金型を用いて半導体素子をモールド成型したときの平面図である。ここでは、便宜上、基板上の単一の領域を示している。基板１００の上面には、銅パターンに接続される複数のランド１８２が形成されている。ランド１８２は、基板１００に形成されたスルーホールを介して、基板裏面のはんだボールに接続される領域である。基板１００上の各半導体素子は、モールド樹脂１８４によってそれぞれ封止されている。モールド樹脂１８４は、上部金型１４０のキャビティ１４４を反映し、そのコーナーにはチャンファー１８６が形成されている。さらに、モールド樹脂１８４のチャンファー１８６には、エアポケット１８０に相当する微小な突起１８８が形成されている。   FIG. 9 is a plan view when a semiconductor element is molded using the upper mold according to the second embodiment. Here, for convenience, a single region on the substrate is shown. A plurality of lands 182 connected to the copper pattern are formed on the upper surface of the substrate 100. The land 182 is an area connected to a solder ball on the back surface of the substrate through a through hole formed in the substrate 100. Each semiconductor element on the substrate 100 is sealed with a mold resin 184. The mold resin 184 reflects the cavity 144 of the upper mold 140, and a chamfer 186 is formed at the corner. Further, a minute protrusion 188 corresponding to the air pocket 180 is formed on the chamfer 186 of the mold resin 184.

本実施例では、エアポケット１８０を設けることで、モールド樹脂１８４へのボイドの発生を抑制することができるため、パッケージの歩留まりを向上させることができる。エアポケット１８０の大きさは、ボイドを吸収するために一定の容積を必要とするが、その許容される大きさは、微小な突起１８８がランド１８２から一定距離Ｄだけ離れる必要がある。   In this embodiment, by providing the air pocket 180, generation of voids in the mold resin 184 can be suppressed, so that the package yield can be improved. The size of the air pocket 180 requires a certain volume to absorb the void, but the allowable size requires that the minute protrusion 188 be separated from the land 182 by a certain distance D.

次に、本発明の第３の実施例について説明する。図１０は、第１の実施例によるモールド方法を用いて形成された第１の半導体装置上に、第２の半導体装置が積層されたＰＯＰ（パッケージ・オン・パッケージ）構造を示す断面図である。   Next, a third embodiment of the present invention will be described. FIG. 10 is a cross-sectional view showing a POP (package on package) structure in which a second semiconductor device is stacked on a first semiconductor device formed by using the molding method according to the first embodiment. .

第１の半導体装置２００は、厚さが０．３ｍｍの多層配線基板２０２と、多層配線基板２０２の裏面に形成された、高さが０．２３ｍｍの複数のはんだボール２０４と、多層配線基板２０２の上面に形成されたモールド樹脂２０６とを備えたＢＧＡパッケージを有している。基板２０２の上面にダイアタッチ２０８を介して半導体チップ２１０が取り付けられ、半導体チップ２１０の電極はボンディングワイヤ２１２により基板上の銅パターン２１４に接続されている。半導体チップ２１０およびボンディングワイヤ２１２を含む領域がモールド樹脂２０６によって封止されている。ボンディングワイヤ２１２のチップ表面からのループ高さは、約０．０５ｍｍであり、ボンディングワイヤ２１２からモールド樹脂２０６の表面までの距離が約０．０９５ｍｍであり、第１の半導体装置のパッケージ全体の高さは、０．８ｍｍである。   The first semiconductor device 200 includes a multilayer wiring board 202 having a thickness of 0.3 mm, a plurality of solder balls 204 having a height of 0.23 mm formed on the back surface of the multilayer wiring board 202, and the multilayer wiring board 202. A BGA package including a mold resin 206 formed on the upper surface of the BGA package. A semiconductor chip 210 is attached to the upper surface of the substrate 202 via a die attach 208, and electrodes of the semiconductor chip 210 are connected to a copper pattern 214 on the substrate by bonding wires 212. A region including the semiconductor chip 210 and the bonding wire 212 is sealed with a mold resin 206. The loop height of the bonding wire 212 from the chip surface is about 0.05 mm, the distance from the bonding wire 212 to the surface of the mold resin 206 is about 0.095 mm, and the height of the entire package of the first semiconductor device is high. The thickness is 0.8 mm.

第１の半導体装置２００上に、第２の半導体装置３００が積層されている。第２の半導体装置３００は、例えば基板３０２の上面に半導体チップ３０４、３０６を積層し、これらの半導体チップ３０４、３０６がモールド樹脂３０８によって封止されている。このモールド樹脂３０８は、トランスファーモールドによるものであってもよい。基板３０２の裏面には、その４方向に２列のはんだボール３１０が形成されている。   A second semiconductor device 300 is stacked on the first semiconductor device 200. In the second semiconductor device 300, for example, semiconductor chips 304 and 306 are stacked on the upper surface of the substrate 302, and these semiconductor chips 304 and 306 are sealed with a mold resin 308. The mold resin 308 may be a transfer mold. Two rows of solder balls 310 are formed on the back surface of the substrate 302 in the four directions.

第２の半導体装置３００を第１の半導体装置２００上に積層したとき、はんだボール３１０は、モールド樹脂２０６を取り囲むように配置される。第２の半導体装置のはんだボール３１０は、第１の半導体装置２００の基板２０２の上面に形成された電極２１６に接続される。モールド樹脂２０６の基板２０２の表面からの高さは、約２７０μｍであり、はんだボール３１０の基板３０２からの高さは、これより若干大きくなっている。これにより、基板３０２の裏面とモールド樹脂２０６の間には僅かな間隙が形成されている。   When the second semiconductor device 300 is stacked on the first semiconductor device 200, the solder balls 310 are disposed so as to surround the mold resin 206. The solder ball 310 of the second semiconductor device is connected to the electrode 216 formed on the upper surface of the substrate 202 of the first semiconductor device 200. The height of the mold resin 206 from the surface of the substrate 202 is about 270 μm, and the height of the solder ball 310 from the substrate 302 is slightly larger than this. Thereby, a slight gap is formed between the back surface of the substrate 302 and the mold resin 206.

このように、第１の実施例に係る製造方法を用いた場合、極薄かつ小型のモールド樹脂２０６を含む第１の半導体装置２００上に第２の半導体装置を積層することで、薄型のＰＯＰ構造を得ることができる。同様に第２の実施例に係る製造方法により薄型のＰＯＰ構造を得ることができる。   As described above, when the manufacturing method according to the first embodiment is used, a thin POP is formed by stacking the second semiconductor device on the first semiconductor device 200 including the extremely thin and small mold resin 206. A structure can be obtained. Similarly, a thin POP structure can be obtained by the manufacturing method according to the second embodiment.

次に、本発明の第４の実施例について説明する。第１の実施例に係る方法により製造された半導体装置２００（図１０を参照）をマザー基板に実装するとき、リフロー炉内を通すことで高温に晒され、基板に反りが発生する。図１１は、半導体装置の反りをモデル化した図であり、同図（ａ）に示すように、基板４００およびモールド樹脂４１０が凹状になるプラスの反りと、同図（ｂ）に示すように、凸状になるマイナスの反りがある。基板４００の最下面からモールド樹脂４１０の最上面までの大きさをｈ１、ｈ２としたとき、ｈ１、ｈ２の大きさが１５０μｍを超えると、はんだボールとマザー基板との間に接合不良が生じ易い。   Next, a fourth embodiment of the present invention will be described. When the semiconductor device 200 (see FIG. 10) manufactured by the method according to the first embodiment is mounted on a mother substrate, the substrate is warped by passing through a reflow furnace and being exposed to a high temperature. FIG. 11 is a diagram in which the warpage of the semiconductor device is modeled. As shown in FIG. 11A, as shown in FIG. There is a negative warpage that becomes convex. When the size from the lowermost surface of the substrate 400 to the uppermost surface of the mold resin 410 is h1 and h2, if the sizes of h1 and h2 exceed 150 μm, poor bonding is likely to occur between the solder balls and the mother substrate. .

本実施例では、基板の反りｈ１、ｈ２を低減させるため、図１２に示すような特性の液状樹脂を選択する。ＣＴＥ１は、ガラス転移点以下の温度領域での線膨張係数であり、ＣＴＥ２は、ガラス転移点を越える温度領域での線膨張係数である。ＹＭ１は、ガラス転移点以下の温度領域での縦弾性率（ヤング率）であり、ＹＭ２は、ガラス転移点を越える温度領域での縦弾性率（ヤング率）である。図１２（ａ）には、２種類の条件Ａ、Ｂを示しているが、条件Ｂの液状樹脂を用いることが好ましい。また、半導体装置２００の構成を図１２（ｂ）に示す。半導体チップは、シリコンチップであり、幅８．８ｍｍ、奥行き８．６ｍｍ、高さ０．１ｍｍである。また、多層配線基板は、その材質がＢＴであり、その線膨張係数が３０〜２００℃の温度範囲で約１７ｐｐｍであり、サイズは、幅１．４ｍｍ、奥行き１．４ｍｍ、高さ０．３ｍｍである。   In this embodiment, in order to reduce the warpage h1 and h2 of the substrate, a liquid resin having characteristics as shown in FIG. 12 is selected. CTE1 is a linear expansion coefficient in a temperature region below the glass transition point, and CTE2 is a linear expansion coefficient in a temperature region exceeding the glass transition point. YM1 is the longitudinal elastic modulus (Young's modulus) in the temperature region below the glass transition point, and YM2 is the longitudinal elastic modulus (Young's modulus) in the temperature region exceeding the glass transition point. FIG. 12A shows two types of conditions A and B, but it is preferable to use a liquid resin under condition B. The configuration of the semiconductor device 200 is shown in FIG. The semiconductor chip is a silicon chip, and has a width of 8.8 mm, a depth of 8.6 mm, and a height of 0.1 mm. The multilayer wiring board is made of BT and has a linear expansion coefficient of about 17 ppm in the temperature range of 30 to 200 ° C. The size is 1.4 mm in width, 1.4 mm in depth, and 0.3 mm in height. It is.

このような構成により、室温（例えば、２５℃）での半導体装置の反りの大きさｈ１、ｈ２をそれぞれ８０μｍ以下、高温（例えば、２６０℃）での半導体装置の反りの大きさｈ１、ｈ２をそれぞれ１１０μｍ以下にすることができ、これにより、基板実装時に良好なはんだ接合が可能となる。   With such a configuration, the warp magnitudes h1 and h2 of the semiconductor device at room temperature (eg, 25 ° C.) are 80 μm or less, respectively, and the warp magnitudes h1 and h2 of the semiconductor device at a high temperature (eg, 260 ° C.) are respectively set. Each of the thicknesses can be 110 μm or less, which makes it possible to achieve good solder bonding during board mounting.

本発明の好ましい実施の形態について詳述したが、本発明に係る特定の実施形態に限定されるものではなく、特許請求の範囲に記載された本発明の要旨の範囲内において、種々の変形・変更が可能である。   Although the preferred embodiment of the present invention has been described in detail, the present invention is not limited to the specific embodiment according to the present invention, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

上記実施例では、ＢＧＡまたはＣＳＰタイプの半導体装置の製造方法を示したが、勿論、これ以外の半導体装置であってもよい。要は、基板の一面に搭載された半導体チップを樹脂封止するものであれば、特に、パッケージの構成が限定されるものではない。さらに、半導体チップの基板上への実装方法は、ワイヤボンディングによる接続以外にも、フェースダウンによる接続等であってもよい。さらに上部金型に形成されるキャビティを矩形状としたが、樹脂モールドの側面が傾斜するようにキャビティの側面に傾斜を持たせるようにしてもよい。   In the above-described embodiment, the manufacturing method of the BGA or CSP type semiconductor device has been described. However, other semiconductor devices may be used as a matter of course. In short, the configuration of the package is not particularly limited as long as the semiconductor chip mounted on one surface of the substrate is resin-sealed. Furthermore, the mounting method of the semiconductor chip on the substrate may be face-down connection or the like in addition to connection by wire bonding. Furthermore, although the cavity formed in the upper mold is rectangular, the side surface of the cavity may be inclined so that the side surface of the resin mold is inclined.

本発明に係る半導体チップのモールド方法は、従来のトランスファーモールド工法やポッティング工法に置き換え可能であり、本発明のモールド方法を用いることにより超小型、超極薄の寸法精度の安定した半導体装置を提供することができる。特に、表面実装型の半導体装置の超薄型化を実現することができる。   The semiconductor chip molding method according to the present invention can be replaced with a conventional transfer molding method or potting method, and by using the molding method according to the present invention, an ultra-small and ultra-thin semiconductor device with stable dimensional accuracy is provided. can do. In particular, an ultra-thin surface-mount type semiconductor device can be realized.

図１（ａ）は、複数の半導体チップが搭載された基板の平面図、図１（ｂ）はＡ−Ａ線断面図である。FIG. 1A is a plan view of a substrate on which a plurality of semiconductor chips are mounted, and FIG. 1B is a cross-sectional view taken along line AA. 本発明の実施例に係るモールド方法の工程を示す図である。It is a figure which shows the process of the molding method which concerns on the Example of this invention. 本発明の実施例に係るモールド方法の工程を示す図である。It is a figure which shows the process of the molding method which concerns on the Example of this invention. 本発明の実施例に係るモールド方法の工程を示す図である。It is a figure which shows the process of the molding method which concerns on the Example of this invention. 本発明の実施例に係るモールド方法の工程を示す図である。It is a figure which shows the process of the molding method which concerns on the Example of this invention. 本発明の実施例に係るモールド方法の工程を示す図である。It is a figure which shows the process of the molding method which concerns on the Example of this invention. 本発明の実施例に係るモールド方法の工程を示す図であり、同図（ａ）はモールド樹脂が形成された基板の平面図、同図（ｂ）はＡ１−Ａ１断面図である。It is a figure which shows the process of the molding method which concerns on the Example of this invention, The figure (a) is a top view of the board | substrate with which mold resin was formed, The figure (b) is A1-A1 sectional drawing. 本発明の第２の実施例に係る上部金型を示し、図８（ａ）は、上部金型を裏面側からみた平面図、図８（ｂ）は、チャンファー部分の断面図である。The upper metal mold | die which concerns on the 2nd Example of this invention is shown, Fig.8 (a) is the top view which looked at the upper metal mold | die from the back surface side, FIG.8 (b) is sectional drawing of a chamfer part. 第２の実施例によるモールド樹脂の外形を示す図である。It is a figure which shows the external shape of the mold resin by a 2nd Example. 半導体装置の積層構造を示す概略断面図である。It is a schematic sectional drawing which shows the laminated structure of a semiconductor device. 半導体装置の反りを説明する図である。It is a figure explaining the curvature of a semiconductor device. 液状樹脂の樹脂特性および半導体装置の主要部のサイズを示す表である。It is a table | surface which shows the resin characteristic of liquid resin, and the size of the principal part of a semiconductor device. 従来のＢＧＡパッケージの一部断面を含む斜視図である。It is a perspective view containing the partial cross section of the conventional BGA package. 従来のマトリックス基板のモールド方法を説明する図である。It is a figure explaining the molding method of the conventional matrix substrate.

符号の説明Explanation of symbols

１００：基板
１０２、２１０、３０４、３０６：半導体チップ
１０４、２１２：ボンディングワイヤ
１１０：供給部
１１２：ノズル
１１４：液状樹脂
１３０：下部金型
１４０：上部金型
１４２：リリースフィルム
１４４：キャビティ
１４６：押圧部材
１５０：吸気孔
１５２：脚部
１６０、１８４、２０６、４１０：モールド樹脂
１７０、１８６：チャンファー
１８０：エアポケット
１８２：ランド
１８８：突起
２００：第１の半導体装置
２０２：多層配線基板
２０４：はんだボール
２０８：ダイアタッチ
３００：第２の半導体装置 100: Substrate 102, 210, 304, 306: Semiconductor chip 104, 212: Bonding wire 110: Supply unit 112: Nozzle 114: Liquid resin 130: Lower mold 140: Upper mold 142: Release film 144: Cavity 146: Press Member 150: Air intake hole 152: Legs 160, 184, 206, 410: Mold resin 170, 186: Chamfer 180: Air pocket 182: Land 188: Projection 200: First semiconductor device 202: Multilayer wiring board 204: Solder Ball 208: Die attach 300: Second semiconductor device

Claims (12)

基板上に搭載された半導体素子を樹脂封止する半導体装置の製造方法であって、
基板の第１の主面上に複数の半導体素子を配し、
基板の第１の主面と対向する第２の主面を支持部材上に固定し、
各半導体素子の少なくとも１部を覆うように、各半導体素子のそれぞれに液状樹脂を供給し、
一面に複数の凹部が形成された型形成部材を支持部材に対して押圧し、一定の温度下において各凹部により各半導体素子の液状樹脂をモールドし、
型形成部材の凹部を基板から離脱させるステップを含み、
液状樹脂のガラス転移点が１００〜１６０℃であり、ガラス転移点以下の温度領域での線膨張係数が２０〜３０ｐｐｍ、ガラス転移点を越える温度領域での線膨張係数が８０〜１２０ｐｐｍ、ガラス転移点以下の温度領域での縦弾性率が１〜２０ＧＰａ、ガラス転移点を越える温度領域での縦弾性率が０．１〜１．０ＧＰａである、
半導体装置の製造方法。 A method of manufacturing a semiconductor device for resin-sealing a semiconductor element mounted on a substrate,
Arranging a plurality of semiconductor elements on the first main surface of the substrate;
Fixing a second main surface opposite to the first main surface of the substrate on the support member;
Supplying a liquid resin to each of the semiconductor elements so as to cover at least a part of each semiconductor element;
A mold forming member having a plurality of recesses formed on one surface is pressed against the support member, and a liquid resin of each semiconductor element is molded by each recess under a certain temperature.
Detaching the recess of the mold forming member from the substrate,
The glass transition point of the liquid resin is 100 to 160 ° C., the linear expansion coefficient in the temperature region below the glass transition point is 20 to 30 ppm, the linear expansion coefficient in the temperature region exceeding the glass transition point is 80 to 120 ppm, and the glass transition. The longitudinal elastic modulus in the temperature region below the point is 1 to 20 GPa, and the longitudinal elastic modulus in the temperature region exceeding the glass transition point is 0.1 to 1.0 GPa.
A method for manufacturing a semiconductor device. 基板上に搭載された半導体素子を樹脂封止する半導体装置の製造方法であって、
基板の第１の主面上に複数の半導体素子を配し、
基板の第１の主面と対向する第２の主面を支持部材上に固定し、
各半導体素子の少なくとも１部を覆うように、各半導体素子のそれぞれに液状樹脂を供給し、
一面に複数の凹部が形成された型形成部材を支持部材に対して押圧し、一定の温度下において各凹部により各半導体素子の液状樹脂をモールドし、
型形成部材の凹部を基板から離脱させるステップを含み、
液状樹脂のガラス転移点が１３０〜１６０℃であり、ガラス転移点以下の温度領域での線膨張係数が２４〜２５ｐｐｍ、ガラス転移点を越える温度領域での線膨張係数が９０〜１００ｐｐｍ、ガラス転移点以下の温度領域での縦弾性率が９〜１１ＧＰａ、ガラス転移点を越える温度領域での縦弾性率が０．２〜０．５ＧＰａである、
半導体装置の製造方法。 A method of manufacturing a semiconductor device for resin-sealing a semiconductor element mounted on a substrate,
Arranging a plurality of semiconductor elements on the first main surface of the substrate;
Fixing a second main surface opposite to the first main surface of the substrate on the support member;
Supplying a liquid resin to each of the semiconductor elements so as to cover at least a part of each semiconductor element;
A mold forming member having a plurality of recesses formed on one surface is pressed against the support member, and a liquid resin of each semiconductor element is molded by each recess under a certain temperature.
Detaching the recess of the mold forming member from the substrate,
The glass transition point of the liquid resin is 130 to 160 ° C., the linear expansion coefficient in the temperature range below the glass transition point is 24 to 25 ppm, the linear expansion coefficient in the temperature range exceeding the glass transition point is 90 to 100 ppm, and the glass transition. The longitudinal elastic modulus in the temperature region below the point is 9 to 11 GPa, and the longitudinal elastic modulus in the temperature region exceeding the glass transition point is 0.2 to 0.5 GPa.
A method for manufacturing a semiconductor device. 基板の線膨張係数は、３０〜２００℃の温度範囲において約１７ｐｐｍである、請求項１または２に記載の製造方法。 The manufacturing method according to claim 1 or 2, wherein the linear expansion coefficient of the substrate is about 17 ppm in a temperature range of 30 to 200 ° C. 製造方法はさらに、モールドされた半導体素子の領域に応じて基板を切断するステップを含む、請求項１または２に記載の製造方法。 The manufacturing method according to claim 1, further comprising a step of cutting the substrate in accordance with a region of the molded semiconductor element. 製造方法はさらに、基板の第２の主面に接続端子を取り付けるステップを含む、請求項１または２に記載の製造方法。 The manufacturing method according to claim 1, further comprising a step of attaching a connection terminal to the second main surface of the substrate. 製造方法はさらに、基板の第１の主面上に他の半導体装置を積層するステップを含む、請求項１ないし５いずれか１つに記載の製造方法。 6. The manufacturing method according to claim 1, further comprising a step of stacking another semiconductor device on the first main surface of the substrate. 製造方法はさらに、基板の第２の主面に接続された接続端子をマザー基板に接続するステップを含む、請求項５に記載の製造方法。 The manufacturing method according to claim 5, further comprising connecting a connection terminal connected to the second main surface of the substrate to the mother substrate. 請求項１ないし７のいずれか１つに記載された製造方法によって製造されたモールド樹脂を含む基板と、モールド樹脂内に封止された半導体素子とを含む、半導体装置。 A semiconductor device comprising: a substrate including a mold resin manufactured by the manufacturing method according to claim 1; and a semiconductor element sealed in the mold resin. 基板の第１の主面上には配線パターンが形成され、他の半導体装置の裏面に形成された複数の接続端子が前記配線パターンに電気的に接続される、請求項８に記載の半導体装置。 9. The semiconductor device according to claim 8, wherein a wiring pattern is formed on the first main surface of the substrate, and a plurality of connection terminals formed on the back surface of another semiconductor device are electrically connected to the wiring pattern. . 他の半導体装置の接続端子は、モールド樹脂の外周に配され、モールド樹脂は、当該基板と他の半導体装置との間に配されている、請求項９に記載の半導体装置。 10. The semiconductor device according to claim 9, wherein connection terminals of the other semiconductor device are arranged on an outer periphery of the mold resin, and the mold resin is arranged between the substrate and the other semiconductor device. 液状樹脂が成型されたときのモールド樹脂の占有面積は、基板表面の面積の少なくとも６１％以下である、請求項８または９に記載の半導体装置。 The semiconductor device according to claim 8 or 9, wherein an area occupied by the mold resin when the liquid resin is molded is at least 61% or less of an area of the substrate surface. 半導体装置の基板の反りは、１１０μｍ以下である、請求項８ないし１１いずれか１つに記載の半導体装置。 The semiconductor device according to claim 8, wherein a warp of the substrate of the semiconductor device is 110 μm or less.
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