TW531780B - Method for forming uniform anti-reflection layer - Google Patents

Abstract

A method for forming uniform anti-reflection layer is provided and is suitable for a substrate having first, second and third regions. It comprises the following steps. Coat the substrate with a first anti-reflection layer whose thickness on the first, second and third regions are first, second and third thickness respectively. The first thickness is smaller than the second and the second thickness is smaller than the third. Etch the first anti-reflection layer for a designated time and coat a second anti-reflection layer to form an uniform anti-reflection layer.

Description

531780

V. Description of the Invention (1) Field of the Invention This case is a method for uniformly forming a thin film, especially a method for uniformly forming an anti-reflection layer on a half-substrate. A background of the invention With the increase in component integration requirements, many processes have also changed. Please refer to the first figure (a), which is on a semiconductor substrate * Λ, ah, "body circuit", especially dynamic random storage. Take the production of the memory circuit, this is 1 Γ 3¾ Cheng Li q and the schematic diagram 'It mainly shows how to define the metal layer (usually referred to as the MO level) that is connected at the first layer. For related technologies, please refer to US Patent No. 6258727. Content) before the job. However, according to different functions, this integrated circuit is divided into two areas, the first area is the array area 11 (array, especially the array completed by the dynamic random access memory circuit unit), and the second area is Peripheral area 12 (periphery, especially the peripheral control circuit of the dynamic random access memory), and in the array area i 丄 there are many contact holes contacting the bit line, and 3, and polycrystalline silicon plugs have been formed therein. 14 (polySi 1 icon piUg). Then we can easily apply an anti-reflection layer 15 'above the substrate, especially a bottom anti-reflective coating layer (barl, for example, BARL 9 0 0 produced by SHIPLEY USA), and then provide it for subsequent optical micro- The shadow process is used to define the trenches and contact holes (not shown) required to form the interconnect metal layer thereon.

Page 4 531780 V. Description of the invention (2) Refer to the first figure (b) again, which is a schematic cross-sectional view of another fabrication process of a integrated circuit completed on a semiconductor substrate, especially a dynamic random access memory circuit. The biggest difference from the first figure (a) is that the polycrystalline silicon plug is not manufactured separately, but the plug and the inner connecting wire are directly completed by using M0 (the material is usually tungsten). It can be seen from the figure that since the contact holes 13 in the array region j ^ no longer have polycrystalline silicon plugs, the subsequently applied anti-reflection layer 15 will fill a large number of these contact holes 3, Therefore, the coated anti-reflection layer 15 will have a significant thickness difference between the array region 11 and the peripheral region 2. In this way, when using photoresistors 6 and anti-reflection layers 5 to define the trenches and contact holes required for M0, the required etching caused by the excessively thick antireflection layer 15 in the surrounding area 2 The time (ARC 〇peri ti me) is too long, which leads to the thinner anti-reflection layer in the array area. 5 has been penetrated by # and eroded sideways (as shown by the dotted line in the figure). The width of M 0 of Yan Yuan Cheng cannot be effectively reduced, which also increases the probability of short circuit of the metal wire. Therefore, the thickness uniformity of the coated anti-reflection layer 15 in the array area 丨 丨 and the surrounding area 12 will seriously affect the critical dimension (Critical Dimension, CD) of the subsequent completed M0 (usually a revolution), and how effective The improvement of the thickness of the anti-reflection layer 15 in the array region 丨 丨 and the peripheral region 12 is the main purpose of developing this case. Summary of the Invention _ This case is a method for uniformly forming an anti-reflection layer, which is applicable to a substrate with a first region, a second region, and a first,

Page 5 531780 V. Description of the invention (3) Region, the method includes the following steps: coating a first anti-reflection layer on the substrate, the first anti-reflection layer on the first region, the second region and the third region The thicknesses are a first thickness, a second thickness, and a third thickness, and the first thickness is less than the second thickness, and the second thickness is less than the third thickness; the first anti-reflection layer is etched to A predetermined time; and coating a second anti-reflection layer on the first anti-reflection layer after etching to form an anti-reflection layer having a uniform thickness. According to the above concept, the substrate in this case is a semiconductor substrate. ~ According to the above idea, the semiconductor substrate in this case is a silicon substrate. According to the above concept, the first region, the second region, and the third region on the substrate in the present case are an array region, a peripheral region, and a cutting region of a dynamic random access memory circuit, respectively. According to the above concept, the material of the first anti-reflection layer in this case is a bottom anti-reflection layer. According to the above concept, the time required to completely remove the first anti-reflection layer on the third region in this case is the predetermined time. According to the above idea, the etching of the first anti-reflection layer in the present case includes the following steps: performing a first etching step; and performing a second etching step, wherein the first etching step is performed on the first anti-reflection layer The etching rate is greater than the remaining etching rate of the first anti-radiation layer in the second etching step. According to the above concept, the material of the second anti-reflection layer in the present case is a bottom anti-reflection layer. ‘According to the above idea, in this case, the first anti-reflection layer or the second anti-

531780 V. Description of the invention (4) After the reflection layer is completed, the baking process is performed at a temperature of 400 to 600 degrees Celsius for 30 seconds to 90 seconds. According to the above concept, the number of contact holes on the first region, the second region, and the third region on the substrate in this case are a first number, a second number, and a third number, and the The first quantity is greater than the second quantity, and the second quantity is greater than the third quantity. ^ Another aspect of the case is a method for uniformly forming a thin film, which is applicable to a substrate having a first region and a second region. The method includes the following steps: coating a first A thickness of the first film on the first region and the second region is a first thickness and a second thickness, respectively, and the first thickness is smaller than the second thickness; the first film is etched For a predetermined time; and coating a second film on the first film after the etching to form a film having a uniform thickness. According to the above idea, the material of the films in this case is an anti-reflection layer. According to the above idea, the material of the anti-reflection layers in this case is a bottom anti-reflection layer. According to the above idea, the substrate in the present case is a semiconductor substrate. According to the above idea ', the semiconductor substrate in this case is a broken substrate. _ According to the above idea, in this case, there is a third region on the substrate. The thickness of the first film on the third region is a third thickness, and the second thickness is smaller than the third thickness. 1 According to the above idea, the first area on the substrate in the case is ·

Page 7 531780 V. Description of the Invention (5) The domain, the second area and the third area are an array area, a peripheral area and a cutting area of a dynamic random access memory circuit, respectively. According to the above concept, the time required to completely remove the first anti-reflection layer on the third region in this case is the predetermined time. According to the above idea, the etching of the first film in this case includes the following steps: performing a first etching step; and performing a second etching step, wherein the etching rate of the first film to the first film is greater than The second etching step etches the first thin film. According to the above idea, after the first anti-reflection layer or the second anti-reflection layer is completed, the baking process is performed at a temperature of 400 to 600 degrees Celsius for 30 to 90 seconds. . According to the above concept, the number of contact holes on the first region and the second region on the substrate in this case are a first number and a second number, respectively, and the first number is greater than the second number. Simple diagram description This case can gain a deeper understanding through the following diagrams and detailed descriptions: # First picture (a): It is a complete integrated circuit completed on a semiconductor substrate, especially dynamic random access Schematic sectional view of the manufacturing process of the memory circuit. 1 The first picture (b): It is an integrated circuit completed on a semiconductor substrate, especially a schematic cross-section of another manufacturing process of a dynamic random access memory circuit.

Page 531780

5. Description of the invention (6) Figure. The second picture (a) (b) (c): It is the preferred embodiment developed in this case. The process shows the formation of an anti-reflection layer uniformly. The third picture: It is the experimental position of this embodiment. Fruit data list. The components included in the drawings in this case are not as follows: Array area 1 1 Peripheral area 1 2 Contact hole 1 3 Polycrystalline silicon plug 1 4 Anti-reflection layer 1 5 Photoresist 1 6 Dotted line 1 7 Substrate 2 0 Array area 2 1 Peripheral area 2 2 cutting area 2 3 first anti-reflective layer 2 4 second anti-reflective layer 2 5 For a description of the preferred embodiment, please refer to the first figure (a) (b) (c), which is an anti-reflective layer for achieving uniformity in this case. Schematic diagram of the developed process of the preferred embodiment, where > The second figure (a) shows a surface with a dynamic random access memory circuit on the substrate 20-an array area 21, a peripheral area 22, and a Cutting area 2 3. Since the cutting region 23 does not have contact holes, it is coated on the array region 21 with a large number of contact holes and the peripheral region 22 with a small number of contact holes at a temperature of 40 ° to 60 ° C. Temperature for 30 seconds to 90 seconds

Page 9 531780 V. Description of the invention (7) The thickness of the first anti-reflection layer 24 in the baking process will be as shown in the figure. The thickness of the anti-reflection layer on the array region 21 is smaller than that on the peripheral region 22. The thickness of the anti-reflection layer on the peripheral region 22 is smaller than the thickness of the anti-reflection layer on the cutting region 23. I then performed the first anti-reflection layer 24 for a predetermined time, and the instrumentation may preferably include the following steps: performing a first step; and performing a second step. The remaining etching rate of the first anti-reflection layer in the one-etching step is greater than the touching rate of the first anti-reflection layer in the second # -etching step. As a result, the second-name step with a slower #etch rate will precisely control the required etch depth. The preferred predetermined time is the time required to completely remove the first anti-reflection layer on the third region. The structure after the etching is as shown in the second figure (b). Then I applied a second anti-reflection layer 25 on the first anti-reflection layer 24 after the remaining time and carried out a baking process of 30 seconds to 90 seconds at a temperature of 400 to 600 degrees Celsius. (Baking), so that an anti-reflection layer with a uniform thickness can be formed as shown in the second figure (c). According to the above concept, the substrate in this embodiment may be a semiconductor substrate (such as a Shixi substrate), and the material of the first anti-reflection layer and the second anti-reflection layer is a bottom anti-reflection layer (bottom anti-reflection layer). -reflective coating layer, referred to as BARL, for example, BARL 9 0 0 produced by SHIPLEY USA. The process parameters for the first etching step are "pressure / power / nitrogen / hydrogen = 130mtorr / 300W / 20sccm / 20sccm", and the process parameters for the second etching step are "pressure / power / nitrogen / hydrogen = 25mtorr / 300W / 20sccm / 20sccm ". As for the experiment of this example

Page 10 531780 V. Description of the invention (8) The data of the result is shown in the third figure, from which it can be clearly seen that the improved efficacy achieved in this case has successfully improved the lack of uneven thickness of the anti-reflection layer in conventional methods. To achieve the main purpose of developing this case. Therefore, the invention of this case can be modified by people who are familiar with this technique, but they are not inferior to those who want to protect the scope of patent application.

Page 11 531780 Brief description of the diagrams First diagram (a): It is a schematic diagram of the cross-section of the fabrication process of an integrated circuit on a semiconductor substrate, especially a dynamic random access memory circuit. First figure (b): It is a schematic cross-sectional view of another fabrication process of a integrated circuit completed on a semiconductor substrate, especially a dynamic random access memory circuit. The second diagram (a) (b) (c): It is a schematic diagram of a preferred embodiment process developed in this case to achieve uniform formation of an anti-reflection layer. The third figure: it is the experimental result data list of this embodiment. (9

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Claims (1)

3 3 Amendment No. 90122291 VI. Method of Patent Application 'Applicable to a substrate, the base second area and a third area, the method 1 · A uniformly formed anti-reflection plate has a first area, including The following steps: the first anti-reflective coating, the first anti-reflective layer, the thickness of the first anti-reflective layer on the poor 3 domain and the third area are -th-and-the third thickness, and the- The thickness is less than the first thickness, and the second thickness is less than the third thickness; the first anti-reflection layer is etched for a predetermined time; the first anti-reflection layer shot layer is etched to form a uniform thickness The anti-reflection layer is coated with the anti-reflection layer according to item 1 of the anti-reflection H 81 item, wherein the substrate is a semiconductor sand. Square = I ΐ #s The method of uniformly forming an anti-reflection layer as described in item 1 'wherein the tenth and third regions on the substrate are randomly stored t ^ the second region and the domain, -Peripheral area and the method of uniformly forming an anti-reflection layer as described in item 1 of the array region H㈣s, wherein the material of the-anti-reflection layer is a bottom square 5. If the scope of application for patent is item 丨-a method, in which the \ ^ \ Λ layer on the third region is completely removed is the predetermined time. When the first anti-reflection layer on the surface of the mystery is needed, 6 ^ Such as the scope of patent application! The method described in the above item, wherein the first anti-reflection layer is sharply formed into several reflective layers, and the -th step- (ii) step is performed; 531780 A second etching step is further performed, wherein the etching rate of the anti-reflection layer in the first etching step is greater than the etching rate of the first anti-reflection layer in the first etching step by 50-80%. The material of the mean-square anti-reflection layer described in item 1 is a bottom anti-reflection layer. 8. The method of uniformly forming an anti-reflection layer as described in item 丨 of the patent scope of the patent application & After the first anti-reflection layer or the second anti-reflection layer is completed, it is performed at a temperature of 600 degrees to 3 degrees. Baking process from 0 seconds to 90 seconds. ', 9 · The method of uniformly forming an anti-reflection layer as described in item 丨 of the scope of application for patent, i, wherein the number of contact holes on the first region, the second region, and the f region on the substrate are respectively Are a first number, a second number I, and a second number, and the first number is greater than the second number, and the second number is greater than the third number. 10. A method for uniformly forming a thin film is applicable to a substrate having a first region and a second region. The method includes the following steps of coating a first film on the substrate, and the first film is applied on the substrate. The thicknesses on the first region and the second region are a first thickness and a second thickness, respectively, and the first thickness is smaller than the second thickness; the first thin film is etched for a predetermined time; and after the etching, A second film is coated on the first film to form a film with a uniform thickness. 11 · The method for uniformly forming a thin film as described in item 10 of the scope of patent application, Page 14 2002. 09.04. 007 531780 ----- Surface 901222Q1_ Amendment 6. Scope of patent application '---------- Among them, the material of these films is / anti-reflective layer. 1 2 · The method for uniformly forming a thin film as described in item 丨 丨 of the scope of patent application, wherein the material of the anti-reflection layers is a bottom anti-reflection layer. (1) The method for uniformly forming a thin film as described in the item No. of the patent application scope, wherein the substrate is a semiconductor. 14. The method for uniformly forming a thin film as described in item 丨 丨 of the scope of patent application, wherein the substrate further has a third region, and the thickness of the first film on the third region is a third thickness, and The second thickness is smaller than the third thickness 7 1 5 · The method X for uniformly forming a thin film as described in item 14 of the scope of the patent application, wherein the first region, the second region, and the third region on the substrate are An array region, two peripheral regions, and a cutting region of a dynamic random access memory circuit, respectively. 16 · The method for uniformly forming a thin film as described in item 15 of the scope of patent application, wherein the time required to completely remove the first anti-reflection layer on the third region is the predetermined time. 17. The method for uniformly forming a thin film as described in item 10 of the scope of patent application, wherein the etching of the first thin film includes the following steps: performing a first etching step; and The etching rate of the thin film is 80-1 20 mm / min, which is greater than the remaining etching rate of the first thin film in the second etching step by 50-80 nm / min. 18 · The method for uniformly forming agricultural wheat as described in item 10 of the scope of patent application, wherein after the first anti-reflection layer or the second anti-reflection layer is completed, it is at a temperature of 400 to 600 degrees Celsius A baking process of 30 seconds to 90 seconds is performed. Page 15 2002. 09.10.008 531780 Amendment No. 90122291 6. Application for patent scope 1 9. The method for uniformly forming a thin film as described in item 10 of the patent application scope, wherein the first region on the substrate, The number of contact holes in the second area is a first number and a second number, and the first number is greater than the second number. Page 16 2002.09.10.009