529121 A7 B7 經濟部智.€財產局員工消費合作社印製 五、發明說明（） 發明領域· 一種介電層的製造方法，特別是適用於一爐管式化學 氣相沉積反應器’可以修正基底中離子濃度因溫度效應而 造成的影響。 發明背景 在半導體製程中’ 一般介電材質係以化學氣相沉積的 方法形成，而爐管式化;學氣相丨冗胃反應器可以同時對多片 晶圓進行沉積製程。 第1圖係繪示一直立式爐管式化學氣相沉積反應器的 剖面示意圖。請參照第1圖’反應器100本身是以經回火 (Annealed)後的石英（Quartz)所構成的。反應氣體102通常 從爐管的下端氣體入口 104，送入爐管內（當然也有其他不 同的設計方式）。預備進行沉積製程的晶圓106則置於同樣 以石英所製成的晶舟(Boat)108上，並隨著晶舟1〇8，放入 爐管110的適當位置，以便進行沈積。沈積反應所剩下的 廢氣112，則經由真空系統而從氣體出口 114被排出。加熱 器（未繪示於圖上）不但對爐管110內的晶圓106加熱， 而且也會把整個爐管110的溫度提升到與晶圓106所承受 的溫度相當。第1圖所顯示的反應器100，是結合低壓、熱 2 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公f ) (請先閱讀背面之注意事項再填寫本頁) 丨費 訂---------線* 529121 經濟部智慧財產局員工消費合作社印製 Λ7 __B7 _ 五、發明說明（） 壁、及整批式設計爲一體的化學氣相沉積設備。一般而言， 每次進行沈積的晶圓數量’可以多達片以上。 反應器100設計的最大特點是，爐管內的每一片晶圓 106的表面溫度都可以控制在極其均勻的狀態。但是因爲反 應氣體的濃度會隨著反應的進行而降低，因此，爐管110 的設計，會面臨接近製程氣體入口 104的晶圓106的表面 沈積速率，較其他部份爲高的情形。爲了使反應爐管110 內的每一片晶圓106的沉積都在一定的均勻度之內。因此， 爐管110內的溫度是成一梯度的變化，使接近製程氣體入 口 104的區域，處於較低的溫度下，然後依次逐步地提高， 讓接近氣體出口 Π4的晶圓1〇6處在較高的溫度下，以便 彌補因氣體濃度下降所導致的沈積速率的差距。依製程的 不同，這個爐管內的前後溫度差，大約在20到40°C之間。 在現在商業化的VLSI製程裡，以爐管式化學氣相沉積 反應器進行沈積的材料，主要有多晶矽(Poly Silicon)，氧 化矽（Silicon Oxide)，氮化矽（Silic〇rl Nitride)及氮氧化矽 (Silicon-Oxy-Nitdde)等。製程所控制的溫度，大約在400 °C到850°C左右。 爐管式化學氣相沉積反應器雖然可以同時對多片晶圓 進行沉積製程’但是爲了修正因氣體濃度下降所導致的沈 3 II----------變--------tr---------線# (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4 (210 x 297 公餐） 經濟部智慧財產局員工消費合作社印製 529121 A7 五、發明說明（） 積速率的差距而在爐管內產生一溫度的梯度變化卻會對原 先已佈植於晶圓中的摻雜離子濃度產生了不同的溫度效應 影響。如此溫度效應影響的結果會導致在較窄線寬製程的 產品之電性發生差異，經由測試發現，經過在780°C、760 °(：及740°C的溫度梯度沉積氮化矽層而形成的金氧半導體 元件，在上下層的晶圓中的飽和汲極電流（saturated drain current，Idsat) 的差異就高達5〜10% ，在有些樣品中差 異甚至更高。 發明目的與槪沭 因此本發明的主要目的就是在提供一種介電層的製造 方法，特別是適用於一爐管式化學氣相沉積反應器，可以 修正基底中離子濃度因溫度效應而造成的影響。 本發明的另一目的是在提供一種介電層的製造方法， 可以降低因溫度效應影響的結果而導致在較窄線寬製程的 產品之電性發生差異。 根據本發明之上述目的，提出一種介電層的製造方 法’適用於一爐管式化學氣相沉積反應器。此一介電層的 材質可以爲氮化矽、氧化矽、氧氮化矽或是這三種材質的 任意組合。製造方法至少包括一沉積步驟及一淸除管路步 4 本紙張尺度適用中國國家標準（CNs)A4規格（210 X 297公f ) --------------------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 529121 A7 B7 五、發明說明（） 驟。在沉積步驟提供一反應氣體至爐管式化學氣相沉積反 應器內，此反應氣體隨所需沉積的材質不同而改變，例如’ 以矽烷鹵化物及氨氣沉積氮化矽、以矽烷、氧化二氮及氣 氣沉積氧氮化矽以及以氧氣、矽烷或氧氣、四乙氧基矽院 沉積氧化矽。 同時，提供一梯度溫度於該爐管式化學氣相沉積反應 器以校正該反應氣體之濃度與壓力之差異。梯度溫度的範 圍會隨所需沉積的材質不同而異，不過適用的溫度範圍約 介於攝氏400度至攝氏850度之間。在沉積步驟結束後必 須進行淸除管路步驟，以淸除反應器中殘留的有毒氣體。 此一淸除管路步驟所需的時間，約與沉積步驟進行的時間 相當，所以，在淸除管路步驟的同時反轉梯度溫度可以減 少位於反應室內上中下層，特別是上下層間的的晶圓所遭 遇的溫度環境的差異，以修正基底中離子濃度因溫度效應 而造成的影響。 圖式之簡單說明 桌1圖係繪不一直立式爐管式化學氣相沉積反應器的 剖面示意圖。 圖式之標記說明 5 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公餐） II-------------费--------訂---------線0 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 529121 A7 B7 五、發明說明（） 100 :反應器 102 :反應氣體 104 :氣體入口 106 :晶圓 108 :晶舟 110 :爐管 112 :廢氣 114 :氣體出口 116 :內管 118 :分段控溫溫度計 發明之詳細說明 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 實施例 本實施例係將本發明提供的介電層的製造方法，應用 於一氮化矽閘極間隙壁的製程。 請參照第1圖，晶圓106裝置於晶舟108上，並將晶 6 本紙張瓦度適用中國國家標準（CNS)A4規格（210 X 297公t ) --------------------訂--------- (請先閱讀背面之注意事項再填冩本頁) 529121 經 濟 部 智 .¾ 財 產 Λ7 B7 五、發明說明（） 最後，經由一非均向回蝕製程移除氮化矽層至閘極的 頂部及源/汲極暴露出來爲止’而在閘極的側壁上形成間隙 壁結構。 經過在淸除管路步驟引入溫度梯度反轉的程序後進行 氮化矽層的沉積而形成的金氧半導體元件，在上下層的晶 圓中的飽和汲極電流（saturated drain current，Idsat) 的 差異就降至5%以下，約介於2〜5%之間。 由上述本發明較佳實施例可知，應用本發明具有可以 修正基底中離子濃度因溫度效應而造成的影響，降低因溫 度效應影響的結果可以減低在較窄線寬製程的產品之電性 發生差異的優點。 本發明所揭露的介電層製造方法並不限只適用於直立 式爐管式化學氣相沉積反應器，水平式爐管式化學氣相沉 積反應器亦可適用。本發明所揭露的方法亦不僅適用於氮 化矽材質的沉積，其他介電層，例如氧化矽和氧氮化矽的 沉積亦可適用。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 --------^--------- (請先閱讀背面•之注意事項再填寫本頁) 消 費 合 社 印 製529121 A7 B7 Printed by the Intellectual Property Agency of the Ministry of Economic Affairs. Consumption Cooperative of Employees of the Property Bureau V. Invention Description () Field of invention · A method for manufacturing a dielectric layer, especially for a furnace-tube chemical vapor deposition reactor 'can modify the substrate The effect of medium ion concentration due to temperature effects. BACKGROUND OF THE INVENTION In a semiconductor process, a general dielectric material is formed by a chemical vapor deposition method, and a furnace tube type; a gas phase and a redundant stomach reactor can perform a deposition process on multiple wafers simultaneously. Figure 1 is a schematic cross-sectional view of a vertical furnace tube chemical vapor deposition reactor. Please refer to FIG. 1 'The reactor 100 itself is made of Quartz which is annealed. The reaction gas 102 is usually sent into the furnace tube from the gas inlet 104 at the lower end of the furnace tube (of course, there are other different design methods). The wafer 106 to be subjected to the deposition process is placed on a boat 108 also made of quartz, and is placed in an appropriate position of the furnace tube 110 with the boat 108 for deposition. The exhaust gas 112 remaining from the deposition reaction is discharged from the gas outlet 114 through the vacuum system. The heater (not shown in the figure) not only heats the wafer 106 in the furnace tube 110, but also raises the temperature of the entire furnace tube 110 to be equivalent to the temperature to which the wafer 106 is subjected. The reactor 100 shown in Figure 1 is a combination of low pressure and heat. 2 The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 male f) (Please read the precautions on the back before filling this page) 丨 Fees Order --------- line * 529121 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Λ7 __B7 _ V. Description of the invention () Walls and batch-type chemical vapor deposition equipment. In general, the number of wafers to be deposited at a time can be as large as or more. The biggest feature of the reactor 100 design is that the surface temperature of each wafer 106 in the furnace tube can be controlled in an extremely uniform state. However, because the concentration of the reaction gas will decrease with the progress of the reaction, the design of the furnace tube 110 may face a higher deposition rate on the surface of the wafer 106 near the process gas inlet 104 than in other parts. In order to make the deposition of each wafer 106 in the reactor tube 110 within a certain uniformity. Therefore, the temperature in the furnace tube 110 changes in a gradient, so that the area close to the process gas inlet 104 is at a lower temperature, and then gradually increased in order to make the wafer 106 near the gas outlet Π4 at a relatively high temperature. High temperature in order to make up for the difference in deposition rate caused by the decrease in gas concentration. Depending on the process, the temperature difference between the front and back of the furnace tube is between 20 and 40 ° C. In the current commercial VLSI process, the materials deposited by furnace-tube chemical vapor deposition reactors are mainly poly silicon, silicon oxide, silicon nitride, and nitrogen. Silicon oxide (Silicon-Oxy-Nitdde) and so on. The temperature controlled by the process is about 400 ° C to 850 ° C. Although the furnace tube chemical vapor deposition reactor can perform the deposition process on multiple wafers at the same time, but in order to correct the Shen 3 II caused by the decrease in gas concentration ---------- change ----- --- tr --------- 线 # (Please read the notes on the back before filling out this page) This paper size applies Chinese National Standard (CNS) A4 (210 x 297 meals) Intellectual Property of the Ministry of Economic Affairs Printed by the Bureau ’s Consumer Cooperatives 529121 A7 V. Description of the invention () The difference in product rate and a temperature gradient in the furnace tube produces different temperatures for the dopant ion concentration that has been implanted in the wafer. Effect. The results of such temperature effects will cause differences in the electrical properties of products in narrower line width processes. It was found through testing that silicon nitride layers were formed by depositing silicon nitride layers at temperature gradients of 780 ° C, 760 ° (:, and 740 ° C). The difference between the saturated drain current (Idsat) of the metal oxide semiconductor device in the upper and lower wafers is as high as 5 ~ 10%, and the difference is even higher in some samples. Purpose of the Invention The main object of the present invention is to provide a method for manufacturing a dielectric layer, which is particularly applicable to a furnace-tube chemical vapor deposition reactor, which can correct the influence of the ion concentration in the substrate due to temperature effects. Another object of the present invention The invention is to provide a method for manufacturing a dielectric layer, which can reduce the difference in electrical properties of products in a narrower line width process due to the effect of temperature effects. According to the above object of the present invention, a method for manufacturing a dielectric layer is proposed 'Suitable for a furnace tube chemical vapor deposition reactor. The material of this dielectric layer can be silicon nitride, silicon oxide, silicon oxynitride, or these three materials Any combination of manufacturing methods. At least one deposition step and one step of removing the pipeline. The paper size is applicable to China National Standards (CNs) A4 (210 X 297 male f). ------------ -------- Order --------- line (please read the notes on the back before filling this page) Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 529121 A7 B7 V. Invention Description ( ) Step. In the deposition step, a reaction gas is provided to the furnace-tube chemical vapor deposition reactor. The reaction gas varies with the material to be deposited, such as' depositing silicon nitride with silane halides and ammonia, and Silane, dinitrogen oxide, and gas deposition of silicon oxynitride and silicon oxide deposition with oxygen, silane, or oxygen, tetraethoxy silicon courtyard. At the same time, a gradient temperature was provided in the furnace-tube chemical vapor deposition reactor for calibration The difference between the concentration and pressure of the reaction gas. The range of the gradient temperature will vary depending on the material to be deposited, but the applicable temperature range is between about 400 ° C and 850 ° C. It must be performed after the deposition step is completed Steps for removing the pipeline to remove the reactor Residual toxic gas. The time required to remove the pipeline step is about the same as that of the deposition step. Therefore, inverting the gradient temperature while removing the pipeline step can reduce the temperature in the upper, lower and middle layers of the reaction chamber, especially It is the difference of the temperature environment encountered by the wafers between the upper and lower layers to correct the effect of the ion concentration in the substrate due to the temperature effect. The simple description of the table is not shown in the vertical furnace tube chemical vapor deposition. Sectional schematic diagram of the reactor. Marking description of the drawing 5 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (21 × X 297 meals) II ------------- Fees --- ----- Order --------- Line 0 (Please read the notes on the back before filling out this page) Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 529121 A7 B7 V. Description of Invention () 100 : Reactor 102: reaction gas 104: gas inlet 106: wafer 108: wafer boat 110: furnace tube 112: exhaust gas 114: gas outlet 116: inner tube 118: detailed description of the invention of the segmented temperature control thermometer These and other objectives, features, and advantages can be made more apparent Understand, a preferred embodiment is given below, and it is described in detail with the accompanying drawings as follows: EXAMPLE This embodiment applies the manufacturing method of the dielectric layer provided by the present invention to a silicon nitride gate gap. Wall process. Please refer to Figure 1, the wafer 106 is mounted on the wafer boat 108, and the wafer 6 paper wattage is in accordance with the Chinese National Standard (CNS) A4 specification (210 X 297 g t) ---------- ---------- Order --------- (Please read the notes on the back before filling out this page) 529121 Ministry of Economic Affairs. ¾ Property Λ7 B7 V. Description of Invention () Finally A spacer structure is formed on the sidewall of the gate by removing the silicon nitride layer through a non-uniform etchback process until the top of the gate and the source / drain are exposed. The saturation drain current (Idsat) of the metal-oxide-semiconductor element formed by the deposition of a silicon nitride layer after the introduction of a temperature gradient inversion step in the erasing pipeline step The difference is reduced to less than 5%, which is between 2 and 5%. It can be known from the foregoing preferred embodiments of the present invention that the application of the present invention can correct the effect of the ion concentration in the substrate due to temperature effects, and reduce the effect of the temperature effect can reduce the difference in electrical properties of products in narrower line width processes The advantages. The manufacturing method of the dielectric layer disclosed in the present invention is not limited to a vertical furnace tube type chemical vapor deposition reactor, and a horizontal furnace tube type chemical vapor deposition reactor is also applicable. The method disclosed in the present invention is not only applicable to the deposition of silicon nitride materials, but also other dielectric layers, such as the deposition of silicon oxide and silicon oxynitride. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. -------- ^ --------- (Please read the notes on the back side before filling out this page)