TW526613B - Packaging method of image sensor - Google Patents

Packaging method of image sensor Download PDF

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Publication number
TW526613B
TW526613B TW091106108A TW91106108A TW526613B TW 526613 B TW526613 B TW 526613B TW 091106108 A TW091106108 A TW 091106108A TW 91106108 A TW91106108 A TW 91106108A TW 526613 B TW526613 B TW 526613B
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TW
Taiwan
Prior art keywords
substrate
image sensor
long hole
packaging
flange layer
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TW091106108A
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English (en)
Inventor
Jr-Hung Shie
Jiun-Hua Juang
Jr-Cheng Wu
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Kingpak Tech Inc
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Priority to TW091106108A priority Critical patent/TW526613B/zh
Priority to US10/147,030 priority patent/US20030213124A1/en
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Publication of TW526613B publication Critical patent/TW526613B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49169—Assembling electrical component directly to terminal or elongated conductor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49789—Obtaining plural product pieces from unitary workpiece
    • Y10T29/49798—Dividing sequentially from leading end, e.g., by cutting or breaking

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Description

526613 五、發明說明（1) 象置背—景— 發明之41^ 本發明為 造便捷及可提 習知技 按，習知 首先提供一基 7，用以使複 二；提供一凸 鏤空區域1 6， 基板1 Q上之複 將複數條導線 基板1 0切割成 示；請參閱圖 定位出容置透 凸緣層1 4上， 請參閱圖 相互連接導通 依切割線2 4切 出線路2 2予以 如是，前 即’當欲切割 22，且由於基 在切割時，黏 一種影像感測写社 高產品良率者封m，特別係指-種製 與述 ^ =感^日日片封裝構造，請參閱圖1及圖2， ^ 〃上佈植有線路12圍成複數個區域 像感測晶片13配置於該複數個區域17 ^ a ’其亡形成有數個與線路1 2相對應之 鉍f 3層14藉由黏膠15黏著於基板1 〇上，使 數個影像感測晶片1 3由鏤空區域1 6露出，再 18電連接影像感測晶片13及基板1〇， 皁顆黏著有凸緣層U之封裝體，如圖2所 3，將該早顆封裴體擺置於一治具22内，以 光玻璃20之區域，再行將透光玻璃2〇封蓋於 而元成影像感測晶片1 3之封裝。 4，基板1 〇之背面設有輸出線路23與線路 ，且相鄰區域之輸出線路22係相互連接，卷 割成單顆封裝體時，可將每一相鄰區域二 切開。 輸 述習知影像感測器構造存在有下之缺點。 成單顆封裝體時，常損及基板1 0之輸出線敗 板1 0與凸緣層1 4係藉由黏膠層1 5黏著， 膠層1 5將溢膠而覆蓋住輸出線路2 2，而影響
526613 五 到 、發明說明（2) 影像感測器之良率 、 有鑑於此，本發明人本於精益求精， 神，研發出本發明影像感測器封裝方法， 穴破之精 知影像感測器封裝方法之缺失，使其更為警可改進上述習 八 匈耳用者。 I迴概要 之目 其上 有貝 區隔 相對 之第 ，將 於該 於該 及延 完成 可有 上述 明並 主要目的’在於提供一插旦彡你4 -¾ ^ α , ^ ^ 種〜像感測器封裝方 间產°°良率之功效，以達到降低封裝成本之 本 法，其 目的。 為 提供一 區域周 由該第 上’該 且相對 影像感 區域上 一透光 晶片包 長孔切 如 本 施例之 發明之 具有提 達上述 基板， 邊形成 一 I孑匕 凸緣層 於基板 測晶片 ，並位 層覆蓋 覆住； 割，而 是，其 發明之 詳細說 的，本 形成複 通基板 ;提供 一長孔 該影像 鏤空槽 凸緣層 者該基 單顆影 效降低 及其他 參考圖 發明之特 數個佈植 之第一長 一凸緣層 於該基板之每一 位置亦形 感測晶片 内；提供 之鏤空槽 板之第一 像感測器 生產成本 目的、優 式俾得以 徵在於包括 有線路之區 孔，使相鄰 ，其係設置 區域位置形 第二長孔； 分別置入該 複數個透光 上，而將該 長孔及該凸 之封裝。 及提南產品 點和特色由 更深入了解 下列步驟； 域，該每一 之邊區域藉 於該基板 成鏤空槽， 提供複數個 基板之每一 層，將該每 等影像感測 緣層之第二 良率。 以下較佳實
第5頁 526613 五、發明說明（3) 較佳實施例之詳細說明 請參閱圖5，本發明影像感測器封裝方法，其包括下 列步驟： 提供提供一基板3 0，其上形成複數個周圍佈植有線路 3 2之區域34，每一區域3 4周邊形成有貫通基板30之第一長 孔3 6，使相鄰之區域3 4藉由第一長孔3 6區隔。請配合參閱 圖6’為基板3 0之背面圖，其於每一區域3 4周邊形成有輸 出線路3 8，輸出線路3 8係與線路3 2相互導通，且每一相鄰 區域3 4之輸出線路3 8係藉由第一長孔3 6區隔分開。 提供一凸緣層4 0，其係以粘膠設置於基板3 〇上，凸緣 層4 0相對於基板3 0之每一區域3 2位置形成鏤空槽42，且相 對於基板30之第一長孔36位置亦形第二長孔44。請參閱圖 7，凸緣層4 0設置於基板3 0上時，基板3 0上之區域3 4係由 鏤空槽4 2露出’且第一長孔3 6係與第二長孔4 4相互疊合。 請參閱圖8，將複數個影像感測晶片4 6分別設置於基 板3 0之每一區域3 4上，並位於凸緣層4 0之鏤空槽4 2内，而 由鏤空槽42露出。 提供複數條導線3 9電連接影像感測晶片4 6及基板3 0之 線路3 2，使影像感測晶片4 6之訊號傳遞至基板3 〇之線路3 2 上’並使訊號傳遞至基板3 0背面之輸出線路3 8。 將複數個透光層4 8，本實施例中為透光玻璃，將其 蓋於每一個凸緣層40之鏤空槽42上，而將每一影像感測= 片4 6覆蓋住，用以接收光訊號。 " 延著基板3 0之第一長孔3 6及凸緣層4 0之第二長孔4 4切
第6頁 526613 五、發明說明（4) 割，將基板3 0上 單顆影像感測器 之每一 另一實施例中，亦 單顆封裝 層4 8之區 藉由 1.由於基 長孔3 6預 長孔3 6切 的提昇產 2·由於預 長孔4 4， 利，甚者 製造時間 在較 了易於說 於實施例 所作種種 體置入 域，再 如上之 板30背 先分離 割時， 品的良 先於基 因此， ，可直 〇 佳實施 明本發 ’凡依 變化實 一治具 行將透 構造組 面之相 ，使得 並不會 率。 板3 0及 在切割 接以手 例之詳 明之技 本發明 施均屬 個封裝完成之影像感測晶片切割成 可在完成基板3 0之切割後，再行將 (圖未顯示）内，以定位出置放透光 光層4 8覆蓋於凸緣層4 0上。 合’本發明具有如下之優點： 鄰區域3 4之輸出線路3 8係藉由第一 在切割成單顆封裝體時，延著第一 損害到輸出線路38，是以，可有效 凸緣層4 0上形成第一長孔3 6及第二 基板30形成單顆封裝體時相當便 工方式分割每一封裝體，更可節省 細說明中所提出之具體實施例僅為 術内容，並非將本發明狹義地限制 ΐ ί神及以下申請專利圍之情況 本發明之範圍。
第7頁 526613 圖式簡單說明 圖1為習知影像感測器構造之分解圖。 圖2為習知影像感測器構造的第一示意圖 圖3為習知影像感測器構造的第二示意圖 圖4為習知基板之背面圖。 圖5為本發明之分解圖。 圖6為本發明之基板的背面圖。 圖7為圖6之組合圖。 圖8為本發明之第一示意圖。 習知圖號 基板 10 線路 12 影像感測晶片 13 凸緣層 14 鏤空槽 16 黏膠 15 導線 18 透光玻璃 20 治具 22 輸出線路 23 切割線 24 本發明 基板 30 線路 32 區域 34 第一長孔 36 輸出線路 38 凸緣層 40 鏤空槽 42 第二長孔 44 複數條導線 39 影像感測晶片 46 複數個透光層4 8
第8頁

Claims (1)

  1. 526613 六、申請專利範圍 1 · 一種影像感測器封裝方法，其包括有下列步驟： 提供一基板，其上形成複數個佈植有線路之區域，該每一 區域周邊形成有貫通基板之第一長孔，使相鄰之該區域藉 由該第一長孔區隔； g 提供一凸緣層，其係設置於該基板上，該凸緣層相對於該 基板之每一區域位置形成鏤空槽，且相對於基板之第一^ 孔位置亦形第二長孔； 提供複數個影像感測晶片，將該影像感測晶片分別置入該 基板之每一區域上，並位於該鏤空槽内； 將該複數個影像感測晶片電連接於該基板上； &供複數個透光層，將該每一透光層覆蓋於該凸緣層之透 空槽上，而將該等影像感測晶片包覆住；及 延著該基板之第一長孔及該凸緣層之第二長孔切割，而完 成單顆影像感測器之封裝。 2 ·如申請專利範圍第1項所述之影像感測器封裝方法，其 中該凸緣層係藉由黏膠黏著於該基板上者。 3 ·如申請專利範圍第1項所述之影像感測器封裝方法，其 中該透光層為透光玻璃。 4 ·如申請專利範圍第1項所述之影像感測器封裝方法，其 中該影像感測晶片係藉由複數條導線電連接於該基板。 5 · —種影像感測器封裝方法，其包括下列步驟： 提供一基板，其上形成複數個佈植有線路之區域，該每一 區域周邊形成有貫通基板之第一長孔，使相鄰之該區域藉 由該第一長孔區隔；
    526613 六、申請專利範圍 提供一凸緣層，其係設置於該基板上，該凸緣層相對於該 基板之每一區域位置形成鏤空槽； 提供複數個影像感測晶片，將該影像感測晶片分別置入該 基板之每一區域上，並位於該鏤空槽内； 將該複數個影像感測晶片電連接於該基板上； 提供複數個透光層，將該每一透光層覆蓋於該凸緣層之鏤 空槽上’而將該等影像感測晶片包覆住；及 延著該基板之第一長孔切割，而完成單顆影像感測器之封 裝。 6 ·如申請專利範圍第5項所述之影像感測器封裝方法，其 中該凸緣層係藉由黏膠黏著於該基板上者。 7 ·如申請專利範圍第5項所述之影像感測器封裝方法，其 中該透光層為透光玻璃。 8 ·如申請專利範圍第5項所述之影像感測器封裝方法，其 中該影像感測晶片係藉由複數條導線電連接於該基板。
    第10頁
TW091106108A 2002-03-27 2002-03-27 Packaging method of image sensor TW526613B (en)

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TW091106108A TW526613B (en) 2002-03-27 2002-03-27 Packaging method of image sensor
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