TW525303B - MOS transistor and method for producing the same - Google Patents

Abstract

A MOS transistor at least comprises a gate, a first doping layer, a second doping layer, a source, and a drain. The first doping layer having a first conductivity and a first dopant concentration is located in a substrate and below the gate. The second doping layer having a first conductivity and a second dopant concentration higher than the first dopant concentration is located below the first doping layer. The source and the drain are located on the two opposed sides of the gate, and are all directly contacting the first doping layer and the second dopaning layer, and all have a second conductivity. One feature of the MOS transistor is it contains no lightly doped drain. However, a first doping layer and a second doping layer having a different dopant concentration exist along the perpendicular direction below the gate.

Description

525303 ___Case No. 90113682_year month __; _ V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to a metal-oxygen half which does not require a shallow junction (sha 1 1 〇wjuncti ο η). A transistor (metal oxide semiconductor, MOS) is also a method for manufacturing a MOS that does not require a low-energy ion implantation process. 5-2 Background of the Invention: The basic structure of MOS includes a gate, a source, and a drain. As shown in Fig. 1a, the gate 12 is located on the substrate 10, and the source 12 and the drain 13 are located in the substrate 10 and located on opposite sides of the gate 11 respectively. Of course, as shown in the first B diagram, the source electrodes 12 and> and the electrodes 13 may also be located in the well region 14 instead of directly in the undoped substrate 10. With the trend of thinner, lighter and shorter semiconductor products, the size of MOS must continue to shrink. If the design of all parameters of the entire semiconductor transistor is kept unchanged, it is only a proportional reduction. When the distance between the source 丨 2 and the drain 丨 3 is short enough to make the empty region of the source 12 (^ e ρ 1 e ^ 丨〇 ^ regi ο η) When it is close to or even overlaps with the gap between 11 and 3 of the pole, the short channel effect becomes an unavoidable problem, which will cause the starting voltage to drop, and the secondary starting current. Increases, thermionic effects, and loss of gate oxide degradation.

525303 _Case No. 90113682 Rev. V. Description of the invention (2) Due to the method of reducing the short-circuit effect by reducing the operating voltage of MOS, it is inevitable that the configuration of the entire semiconductor device must be changed (configuration), cost Tall and implicated. Therefore, conventional techniques usually use lightly doper drain (LDD) to prevent short channel effects. As shown in FIG. 1C and FIG. 1d, a lightly doped electrode 1 5 is added to the side of the source 12 facing the drain 1 3 and / or the side of the electrode 13 facing the source 12. In order to change the formation and distribution of the empty region, change the distribution of the electric field and absorb hot electrons, and then slow down the short channel effect. Here, the lightly doped drain 丨 5 forms a thicker layer than the source 12 and the electrode 1 3 ϊ / u 1 1 _ 1 1 & shallow junction (sha 1 1 ow junction) ° Of course, «M0S. # V ^ # ^ The degree of doping of pole 1 is slightly more doped, and lightly doped, on the other hand. And with the semiconducting r ^: the process of the resistance between the source 12 to the drain 13 will become complicated and < needs to be shortened by 2 = 2 inches, the formation of shallow junctions with the most commonly used low energy Ionic cloth ^ increase in drama, no matter the shallow interface is shaped by law <. The Zibucaihuang program is shaped by & thermal diffusion, etc. ^ The conventional technique has many modifications / changes to the structure of the shallow junction M0S and a lightly doped region with a lightly doped drain, so it is short. But ^ Yu still uses the shallow junction to form some unavoidable missing Γ channel effects. Prevention and control will always accompany the work.

525303 _Case No. 90Π3682_ Year, Month, Day, and Amendment V. Description of the Invention (3) 5-3 Purpose and Summary of the Invention: One of the main purposes of the present invention is to propose a MOS that can effectively prevent and control the short channel effect and its forming method. Another main object of the present invention is to propose a MOS that does not require the use of a lightly doped drain formed with a shallow junction and a method of forming the same. As · Once implanted in the sub-cloth can be so low with no need to provide the J-containing side 〇J manufacturing method of square hair Μ S made out of sequence present process Μ drain electrode species and a source of extremely embodiment, application layer doped solid heteroaryl good Compared with the 21st, the mixed layer of the bright layer is mixed-the first includes the pole gate gate in the •• position system gate gate is mixed in the first phase system, and the layer electrode is mixed in the second electrode phase. In the degree of concentration, the dopants in the dopant are mixed first with the dopant of the paraelectric system. The doped layer is the first; the upper layer is doped with AF. Straightness, and the second dopant electrode with two side gates has two gates and the source source, the power source is conductive, and the first dopant is doped with the second and second gates. The first miscellaneous contact is straight. Absorptive, there are two pairs of parallel phase layer gates on the second side of the electrode guide, which are doped in the second position and the source layer and doped with one •, the first to the French S 〇 种 shaped species-as an example Shi Shijia compares with another Mingfa

Page 6 525303 V. Description of the invention ΛΜ 90113682 (4) Λ_3. The correction is close to the first doped layer, the first change: located at the first doped concentration :: and the doped concentration of the second doped layer is ϊη : The ratio of the layers is large to form the source and the drain in the substrate, and the mask is whitened; the thickness of the first doped layer. The thickness of the electrode and the drain electrode = these embodiments can be further included and the width of the two doped layers is related to the gate; for the purpose: the shape of the IR field 0 on the side wall of the gate: Ϊ ί ”: The formation process must be greater than the source and drain electrodes with a larger thickness. Therefore, the above problem should be solved from another angle? Is it the second implementation / ugliness, the L effect? Does it require the use of lightly doped electrodes? Do not use lightly doped drain and do not change the operating voltage, # Shanghai right to effectively prevent short channel effects? This is due to the paper (IEEE Electron Device Letters, V〇i. 20, No · 2, ρ · 95, Feb 1 9 9 9) It is mentioned that for MOS with super steep retrograde well, when the equivalent channel length is approximately equal, the short channel effect is basically independent of the interface thickness.

Page 7 525303 _Case No. 90113682_ Modification of the month of the year _ i. Description of the invention (5) The inventor of the invention further deduced this concept and pointed out that when the equivalent channel length can be effectively controlled and fixed, use a steeply varying well area The prevention of short channel effects can be achieved without using shallow junctions or changing the operating voltage. Further, the inventor of the present invention pointed out that because the expansion and contact between the empty regions of the source and the drain will cause a short channel effect, a steeply varying well region between the source and the drain can be used to control the source and the The distribution of the empty regions between the drain electrodes further replaces the function of lightly doped non-electrodes in the MOS that do not use the steeply-elevated well area. In other words, a steeply varying well region can be used instead of a lightly doped drain formed with a shallow junction, thereby avoiding the difficulty of forming the shallow junction. In order to specifically implement the above-mentioned concept of replacing the lightly doped non-polar electrode formed by a shallow junction with a steeply varying well area, a preferred embodiment of the present invention is a MOS using a steeply varying well area, as shown in Figure A and Figure 2 As shown in FIG. 2B, at least: a gate electrode 2, a first doped layer 2 2, a second doped layer 2 3, a source electrode 24, and a drain electrode 25. The gate electrode 21 is located on the substrate 20, and may further include a gap wall on the side wall of the gate electrode 21. The first doped layer 22 is located in the substrate 20 and below the gate electrode 21. The first doped layer 22 has a first conductivity and a first doping concentration, and the first doped layer 22 is usually fastened. Facing the surface of the base material 20. The second doped layer 2 3 is located below the first doped layer 2 2 and has a second

525303 _Case No. 90113682_Year Month Day _ ^ _ V. Description of the Invention (6) Electrical conductivity and second doping concentration, the second doping concentration is greater than the first doping concentration. Here, the first conductivity and the second conductivity are generally the same, and the width of the first doped layer 22 and the width of the second doped layer 23 are generally approximately the same as the width of the gate electrode 21. The source electrode 24 is located in the substrate 20 and on one side of the gate electrode 21. The source electrode 24 is directly in contact with the first doped layer 22 and the second doped layer 23, and the source electrode 24 has a second Conductivity. The pole electrode 2 5 and the source electrode 24 are located on opposite sides of the gate electrode 21, and the pole electrode 2 5 is in direct contact with the first doped layer 22 and the second doped layer 23 and has a second conductivity. The thicknesses of the source 24 and the drain 25 are generally larger than those of the first doped layer 22, and the interface between the first doped layer 2 2 and the source 24 and the first doped layer 22 and the drain The contour of the interface of 25 can be a straight line that is almost perpendicular to the surface of the substrate 20 or a curved line segment, which basically depends on the formation process of the source 24 and the drain 25, and the present invention is not limited. In this detail. Obviously, by comparing the second A-picture to the second D-picture and the first A-picture and the first D-picture, it can be seen that a major feature of this embodiment is that there is no lightly doped drain between the source and the non-electrode. Another major feature is that there is not a well region or substrate with a single doping concentration under the gate and between the source and the drain, but there are a first doped layer 22 and a second doped layer with different concentrations at the same time. Miscellaneous layers 2 3. Here, the difference between the second doping concentration and the first doping concentration must be so large that when the first doping layer 22 below the gate 21 is reversed by the gate voltage (operating voltage),

Revised 525303 Case No. 90113682 V. Description of the invention (7) Forming a channel connecting the source 24 and the drain 25 (channel) ^, the second doped layer 23 will not be reversed. A third A picture Figure 3 and Figure B show the change in short channel effects in MOS using steeply varying wells. Figure 3 A shows the basic architecture of this type of MO using steeply varying wells' here the first doped layer 2 2 The thickness is set to 2000 angstroms, the first doping concentration is lx l0i6 / cm ^, and the second doping concentration is 5x10S / cm3. The simulated variable is the thickness of the source 24 and the drain 25, Three thicknesses of 0.06um, 0.12Um, and 0.18_ are simulated here, and the relationship between the equivalent channel length and the starting voltage is calculated. Figure 2B does not show the results of the simulation. Obviously, except for the short channel effect When the equivalent channel length is too short, the starting voltage will decrease, and the short-channel effect caused by the thickness of the homologous pole 2 4 / not pole 25 will be almost exactly the same. Say, 'Using this embodiment, Not only do you need to use lightly doped drains formed on the surface, but also the thickness of the source 24 and drain 25 I thicken with an arbitrary adjustment 'does not need to reduce the thickness of the source 24 and the drain 25 or even use the source 24 and the drain 25 as the critical dimension of the semiconductor element is shortened. Therefore, the source 24 The formation process with the drain electrode can be simplified, and it is not necessary to use a low-energy ion implantation procedure. ^ However, although this embodiment does not require the use of a lightly doped electrode, as shown in Figure 2 < and Figure 2 F As shown in the example, this embodiment may further include an implantation pocket 27 (implantation pocket) to enhance the prevention and control of the short channel effect of this embodiment.

Page 10 525303 _Case No. 90113682_Year Month and Day__ Jade, description of invention (8) Ability. It must be emphasized that the details of the doping bag, such as the profile and concentration, are not the focus of this embodiment. Another preferred embodiment of the present invention is a method for forming a MOS, especially a method for forming a MOS using a steeply varying well area. As shown in FIG. 4A, at least the following steps are included: As shown in the substrate block 41 A substrate with a first doped layer and a second doped layer is provided. The first doped layer is immediately adjacent to the surface of the substrate, and the second doped layer is located below the first doped layer and immediately adjacent to the first doped layer. Layer, the first doped layer has the same electrical properties as the second doped layer, and the doped concentration of the second doped layer is greater than the doped concentration of the first doped layer. The formation process of the first doped layer and the second doped layer is not the focus of this embodiment, and the embodiment is not limited thereto. As shown in the gate block 42, the gate is formed on the substrate. As shown in the doping block 4 3, the substrate is doped with a gate electrode mask to form a source and a drain. In the substrate, the thickness of the source and the drain is greater than that of the first and the thickness of a doped layer. . Of course, since the gap wall can be used to protect the gate sidewall and change the distance between the source and the drain, this embodiment can also be modified to the situation shown in Figure 4B.

525303

It is called Leyi repairing a doped layer, the first strain = the doping concentration of the doped layer, the first layer and the second doping layer. This embodiment is also not limited. For the substrate, the first doped layer is located immediately below the first doped layer and immediately adjacent to the second and second doped layers, and has the same doping concentration as the first / doped layer. The formation process here is not the focus of this embodiment. As shown in the gate block 42, the gate is formed on the substrate. As shown by the spacer wall block 44, a spacer wall is formed on the side wall of the gate. As shown in block 43, the gate and the spacer are used as a mask to perform a doping process on the substrate to form a source and a drain. In the substrate, the source and the drain are both larger than the thickness of the first doped layer. . The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of the patent application. °

525303 _Case No. 90113682_ Year Month Revised _ The diagrams briefly illustrate the first A to D diagrams are the basic structure of the MOS with the conventional use and without using lightly doped drains: the second A to the second F Figures are schematic diagrams of several possible cross-sections of a preferred embodiment of the present invention; Figures A and B are schematic diagrams of a simulation example of the present invention; and Figures A and B are the present invention A basic flowchart of another preferred embodiment. Representative symbols of the main parts: 10 substrate 11 gate 12 source 13 drain 14 well region 15 lightly doped electrode 20 substrate 21 gate 22 first doped layer 23 second doped layer 24 source 25 drain pole

Prepared Page 13 525303 Case No. 90113682 Revised

Page 14

Claims (1)

525303 _Case No. 90113682_ Amendment of the month of the year _ 6. The scope of the patent application 1. A metal-oxygen semi-transistor including at least: a gate electrode, which is located on a substrate; a first doped layer, the A first doped layer is located in the substrate and below the gate. The first doped layer has a first conductivity and a first doping concentration; a second doped layer, the second doped layer The impurity layer is located below the first doped layer, the second doped layer has the first conductivity and a second doping concentration, and the second doping concentration is greater than the first doping concentration; a source electrode The source electrode is located on one side of the gate electrode, the source electrode directly contacts the first doped layer and the second doped layer, the source electrode has a second conductivity; and a drain electrode, the drain electrode The source electrode is located on two opposite sides of the gate electrode, the drain electrode directly contacts the first doped layer and the second doped layer, and the drain electrode has the second conductivity. 2. For the gold-oxygen semi-transistor of the first patent application, the first conductivity is opposite to the second conductivity. 3. For the gold-oxygen semi-transistor of the first patent application, the widths of the gate, the first doped layer and the second doped layer are approximately the same. 4. For the gold-oxygen semi-transistor of the scope of patent application, the first doped layer is directly adjacent to the surface of the substrate. Page 15 525303 _Case No. 90113682_Year Month _Ifi_ VI. Application for patent scope 5. For the gold-oxygen semi-electric crystal of the first scope of the patent application, the second doped layer is close to the first doped layer . 6. For example, the thickness of the source and the electrode of the metal-oxide semi-transistor according to item 1 of the patent application is greater than the thickness of the first doped layer. 7. For a gold-oxygen semitransistor under the scope of patent application 1, the difference between the second doping concentration and the first doping concentration must be so large that when the first doping layer is located below the gate electrode, When the voltage of the gate is reversed to form a channel connecting the source and the drain, the second doped layer is not reversed. 8. A metal-oxygen semi-transistor including at least: a gate electrode, which is located on a substrate; a gap wall, which is located on a side wall of the gate electrode; a first doped layer, The first doped layer is located in the substrate and under the gate. The first doped layer has a first conductivity and a first doping concentration; a second doped layer, the second The doped layer is located under the first doped layer and is close to the first doped layer. The second doped layer has the first conductivity and a second doping concentration, and the second doping concentration is greater than The first doping concentration; a source electrode, which is located on one side of the gate electrode, the source electrode directly contacts the first doped layer and the second doped layer, and the source electrode has a second conductivity Sex; and Page 16 525303 _Case No. 90113682_Year Month_iMz_ Sixth, the scope of patent application is a drain electrode, which is located on the opposite side of the gate electrode from the source electrode, and the drain electrode directly contacts the first dopant. The impurity layer and the second doped layer, the drain electrode has the second conductivity. 9. The metal-oxygen semi-transistor according to item 8 of the application, wherein the first conductivity is opposite to the second conductivity. 10. The thickness of the source electrode and the drain electrode is greater than the thickness of the first doped layer, such as a gold-oxygen semi-transistor according to item 8 of the scope of patent application. 11. According to the gold-oxygen semitransistor of the scope of application for patent No. 8, the difference between the second doping concentration and the first doping concentration must be so large that the first doped layer under the gate is covered by When the voltage of the gate is reversed to form a channel connecting the source and the drain, the second doped layer is not reversed. 1 2. If the gold-oxygen semi-transistor of claim 8 is applied, the first doped layer is close to the surface of the substrate. 1 3. According to the gold-oxygen semi-transistor of claim 8, the second doped layer is close to the first doped layer. 1 4. A method for forming a metal-oxide semiconductor transistor, at least comprising: providing a substrate, the substrate having a first doping layer and a second doping Page 17 525303 _Case No. 90113682 _ Amendment Month_ Sixth, the scope of patent application, the first doped layer is close to the surface of the substrate, and the second doped layer is located in the first doped layer Under the layer and immediately adjacent to the first doped layer, the first doped layer has the same electrical properties as the second doped layer, and the doping concentration of the second doped layer is greater than that of the first doped layer Impurity concentration; forming a gate electrode on the substrate; and using the gate electrode as a mask, performing a doping process on the substrate to form a source electrode and a drain electrode in the substrate, the source electrode Both the thickness and the thickness of the drain electrode are greater than the thickness of the first doped layer. 15. The method according to item 14 of the scope of patent application, further comprising, after forming the gate electrode, forming a gap wall on the side wall of the gate electrode, and then using the gate electrode and the gap wall as the cover. Page 18