TW525242B - Method for removing carbon-rich particles adhered on a copper surface - Google Patents
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525242 五、發明說明(1) 5 - 1發明領域: 本發明係有關於一種半導體製程;特別是有關於一種 去除金屬表面上富碳顆粒之方法,尤其是指一銅/低k值介 電質雙鑲嵌構造上經曝露之銅表面。 5-2發明背景: 在半導體製程進入深次微米領域後,以銅導線鑲嵌( damascene)製程配合金屬間介電層使用低k值材料,可有 效降低R C延遲時間及提升電子遷移(electromigration) 的特性。第一 A圖係一典型的銅/低k值介電質雙鑲嵌構造 。具有複數個元件之一次構造(substructure)(圖中未示 出)係形成於一半導體基底1 00中,而一金屬層(圖中 未示出)形成於此基底1 0 0上方。一氮化石夕或碳化石夕的 阻障層化學機械研磨終止層1 〇 4及一 T a或T a N的阻障層 1 0 6係介於位於基底上方之一低k值介電層1 〇 2與一 銅金屬層1 0 8之間。此阻障層1 0 6用以防止銅擴散至 低k值介電層102中。 參照第一 B圖,在此銅/低k值介電質雙鑲嵌製程期間 ,首先進行一銅化學機械研磨步驟,以平坦化嵌入位於低 k值介電層中之渠溝1 1 2及介層洞1 1 0之銅金屬層1525242 V. Description of the invention (1) 5-1 Field of invention: The present invention relates to a semiconductor process; in particular, it relates to a method for removing carbon-rich particles on a metal surface, especially a copper / low-k dielectric. Exposed copper surface on double mosaic structure. 5-2 Background of the Invention: After the semiconductor process enters the deep sub-micron field, the copper wire damascene process is used in conjunction with the intermetal dielectric layer to use low-k materials, which can effectively reduce the RC delay time and improve the electron migration (electromigration). characteristic. The first A is a typical copper / low-k dielectric dual damascene structure. A substructure (not shown) having a plurality of elements is formed in a semiconductor substrate 100, and a metal layer (not shown) is formed over the substrate 100. A barrier layer of a nitride stone or a carbide of a chemical mechanical polishing stop layer 104 and a barrier layer of Ta or Ta N 106 are a low-k dielectric layer 1 located above the substrate 1 〇2 and a copper metal layer 108. The barrier layer 106 is used to prevent copper from diffusing into the low-k dielectric layer 102. Referring to FIG. 1B, during this copper / low-k dielectric dual damascene process, a copper chemical mechanical polishing step is first performed to planarize the trenches 1 12 and the dielectric embedded in the low-k dielectric layer. Cu 1 1 0 copper metal layer 1
第5頁 525242 五 Ο 機4 、發明說明(2) 8 ,直至陴障層1 0 6。然後,接著進行 以移除此阻障層1 〇 阻障層化學 Ο 8 械研磨步驟,以移除此阻障層1 〇 6 ,直至終止層 。然而,典裘上’材質較軟的銅金屬研磨的速度… 圍的其它讨質,而造成如第一 Β圖所示之銅金屬層1 0 碟化,即經化學機械研磨之銅金屬層1 0 8之上表面/、 碟形構造(dished structure) 會快於 有虛線以下之 ______ …層1 〇 8的磘化現象,即使低值介電爲 ”〜办 予一阻障層化學機械研磨終止層1 0 4 ,S 1 0 2 丄 障層之化學機械研磨期間,低k值介電層在麵金上方埯 曝露出來,旅被研磨。此低k值介電層=1 Q ^屬層及也 …ch)層,包含至少9 〇 %的石炭 二=几素在銅化學機械研磨步驟及阻$ t, *為富 此二化學“ 研磨液中具有相反的2學,J麵会屬 匕::械研磨期間,會有許X、: 造成製程缺陷田反顆粒被吸附在經曝%抵k彼八b,在 。 、麵喪务7層 ,而 據此,g t 方法,特別11共-種可有效去除鋼表 銅表面上舍0 :—鋼/低k值介電質雙鑲资极上富妒 低k值介電質Ί粒之去除方法。此方法教^上^麵< 。 、镇肷製程中化學機械研磨赉Ύ克版曝%气 •、戶厅% 'Page 5 525242 5 〇 Machine 4, the description of the invention (2) 8 to the barrier layer 1 06. Then, a mechanical grinding step is performed to remove the barrier layer 10, and a chemical polishing step is performed to remove the barrier layer 106 until the termination layer. However, the speed of grinding of copper metal with softer materials on Dian Qiu ... other discouragements around the copper metal layer 10 as shown in the first B picture, the copper metal layer 1 after chemical mechanical polishing 1 The upper surface / dish structure will be faster than ______ with the dotted line below the layer 1 〇8 the phenomenon of degeneration, even if the dielectric value is low ~~ to a barrier chemical mechanical polishing During the chemical-mechanical polishing of the stop layer 10 4 and S 1 0 2 丄 barrier layer, the low-k dielectric layer was exposed on the surface of the metal and was polished. This low-k dielectric layer = 1 Q ^ metal layer And also ... ch) layer, containing at least 90% of carbon charcoal in the copper chemical mechanical grinding step and resistance $ t, * is rich in these two chemistries, "the polishing liquid has the opposite 2 science, the J surface will belong to the dagger During the mechanical grinding, there may be X, X: The particles causing the process defects will be adsorbed to the exposed%, and the particles will be absorbed. 7 layers of funeral services, and according to this, the gt method, special 11 in total-can effectively remove the steel surface copper surface 0:-steel / low-k dielectric dual-insertion pole on the jealous low-k value medium Removal method of electrolyte particles. This method teaches ^ upper face <. 、 Chemical-mechanical grinding 赉 Ύ gram version aeration in the town 肷 process
525242 五、發明說明(3) 5 - 3發明目的及概述: - 本發明之,,目的係提供一種去除銅表面上富碳顆粒 之方法,尤其是指一鋼/低k值介電質雙鑲嵌構造上經曝露 , 之銅表面。在一銅化學機械研磨步驟及一阻障層化學機械 · 研磨步驟兀成.之後,使用—酸性水溶液,在晶片施壓壓力 約0· 5至3 psi下,進行一化學緩衝研磨步驟(以㈣丨。。 buffing process)’以有效移除吸附在經曝露之銅表面上 的萄石反顆粒’此些萄碳顆粒之產生係由於銅金屬層之碟化 現象使彳于低k值介電質於此二化學機械研磨步驟期間曝露邐 出來,並被研磨所導致。 本發明之另一目的係提供一種去除銅表面上富碳顆粒 之方法’尤其是指一鋼/低k值介電質雙鑲嵌構造上經曝露 之銅表面。在一銅化學機械研磨步驟完成之後,使用一酸 性水溶液進行一第一化學緩衝研磨步驟,之後進行一阻障 層化學機械研磨步驟,接著使用一酸性水溶液進行一第二 化學緩衝研磨步驟;藉此二化學緩衝研磨步驟去除吸附在 鋼表面上的富碳顆粒。 本發明之又一目的係提供一種有效去除銅表面上富碳 顆粒之方法;此方法適用於低k值介電 學機械研磨製 r£,〇 矛王〇525242 V. Description of the invention (3) 5-3 Purpose and summary of the invention:-The purpose of the present invention is to provide a method for removing carbon-rich particles on the copper surface, especially a steel / low-k dielectric dual inlay Structurally exposed copper surface. After a copper chemical-mechanical polishing step and a barrier chemical-mechanical and polishing step are completed, an acidic aqueous solution is used, under a wafer pressure of about 0.5 to 3 psi, to perform a chemical buffer polishing step (with ㈣丨 ... buffing process) 'in order to effectively remove the vinegar anti-particles adsorbed on the exposed copper surface' The production of these vine carbon particles is due to the discontinuity of the copper metal layer, which results in a low-k dielectric The exposure was caused during these two CMP steps and was caused by the grinding. Another object of the present invention is to provide a method for removing carbon-rich particles on a copper surface ', in particular, an exposed copper surface on a steel / low-k dielectric dual damascene structure. After the copper chemical mechanical polishing step is completed, an acidic aqueous solution is used for a first chemical buffer polishing step, followed by a barrier layer chemical mechanical polishing step, and then an acidic aqueous solution is used for a second chemical buffer polishing step; Two chemical buffer grinding steps remove carbon-rich particles adsorbed on the steel surface. Yet another object of the present invention is to provide a method for effectively removing carbon-rich particles on a copper surface; this method is suitable for low-k dielectric mechanical polishing r £, 〇
第7頁 525242 五、發明說明(4) 根據以上所述之目的,本發明提供一種去除銅表面上 富碳顆粒之方法,特別是指一銅/低k值介電質雙鑲嵌構造 上經曝露之銅表面。首先,提供一半導體基底,其中包含 複數個元件之一次構造(s u b s t r u c t u r e)係形成於此基底 中,而一金屬層係形成於此基底上。形成一低k值介電層 於此基底上,接著形成一終止層於此低k值介電層上。圖 案蝕刻此終止層及低k值介電層,.以形成供做内連線用之 複數個介層洞。圖案#刻此終止層及低k值介電層,以形 成供做導線用之複數個渠溝。之後’形成一均覆的毯覆式 層於經圖案蝕刻的此終止層及低k值介電層上,以供做一 阻障層。形成一銅金屬層於此阻障層/上,以填滿此介層洞 及渠溝。接下來,進行一銅化學機械研磨步驟,以將此銅 金屬層平坦化至阻障層。然後,進行一阻障層機械研磨步 驟,以移除此阻障層至終止層。使用一酸性水溶液,在晶 片施壓壓力約0 . 5至3 p s i下,進行一化學緩衝研磨步驟( chemical buffing polishing process),以移除填充於 此渠溝及介層洞中之此銅金屬層之經曝露的銅表面上吸附 的富碳顆粒。最後,進行一化學機械研磨後清洗步驟,以 除去殘留於經曝露的銅表面上之雜質。另外,本發明亦可 在此銅化學機械研磨步驟完成之後,使用一酸性水溶液進 行一第一化學緩衝研磨步驟,接著進行阻障層化學機械研 磨步驟,之後,使用一酸性水溶液進行一第二化學緩衝研 磨步驟。Page 7 525242 V. Description of the invention (4) According to the above-mentioned object, the present invention provides a method for removing carbon-rich particles on a copper surface, in particular, a copper / low-k dielectric dual-mosaic structure is exposed. Of copper surface. First, a semiconductor substrate is provided. A primary structure (s u b s tr u c t u r e) including a plurality of elements is formed in the substrate, and a metal layer is formed on the substrate. A low-k dielectric layer is formed on the substrate, and then a termination layer is formed on the low-k dielectric layer. The pattern etches the termination layer and the low-k dielectric layer to form a plurality of via holes for interconnections. Pattern # Carves this termination layer and a low-k dielectric layer to form a plurality of trenches for conducting wires. After that, a uniform blanket layer is formed on the stop layer and the low-k dielectric layer which are pattern-etched for use as a barrier layer. A copper metal layer is formed on the barrier layer / to fill the via hole and trench. Next, a copper chemical mechanical polishing step is performed to planarize the copper metal layer to the barrier layer. Then, a mechanical polishing step of the barrier layer is performed to remove the barrier layer to the stop layer. Using an acidic aqueous solution, a chemical buffing polishing process is performed at a wafer pressure of about 0.5 to 3 psi to remove the copper metal layer filled in the trench and the via hole. Carbon-rich particles adsorbed on exposed copper surfaces. Finally, a post-chemical mechanical polishing step is performed to remove impurities remaining on the exposed copper surface. In addition, after the copper chemical mechanical polishing step is completed, the present invention can also use an acidic aqueous solution to perform a first chemical buffer polishing step, followed by a barrier layer chemical mechanical polishing step, and then use an acidic aqueous solution to perform a second chemical Buffer grinding step.
第8頁 525242 五、發明說明(5) 本發明之目的及諸多優點藉由以下具體實施例之詳細 說明,並參照所附圖式,將趨於明瞭。 5 - 4具體實施例之詳細說明: 本發明方法適用於除去一金屬表面上吸附的富碳顆粒 。在本發明之具體實施例中,係使用一銅/低k值介電質雙 鑲嵌構造,如第一 B圖所示,做為實施本發明方法之範例 第一 B.圖中,基底1 〇 〇為一半導體基底,其中具有 複數個元件的一次構造(substructure)(圖示中未示出 )係形成於此基底1 0 0中,而一金屬層(圖中未示出) 係形成於基底1 0 0上方。低k值介電層1 〇 2可由旋塗 式高分子(spin-on polymer)形成,例如芳香族碳氫化合 物、s i 1 k及f 1 a r e。此低k/{i介電層1 〇 2包含至少9 0 % 的碳元素,為一富碳(carbon-rich)層。一渠溝1 1 2及 一介層洞1 1 0之圖案係形成於此低k值介電層1 〇 2中 。阻障層106通常為一 Ta或TaN層,其做為渠溝1 1 2 及介層洞1 1 0之一襯墊層(liner layer),供防止銅金 屬擴散至此低k值介電層1 0 2中。一氮化矽(S i 3N 4)或碳 化石夕(s i 1 i c ο n c a r b i d e)之保護層係形成於此低k值介電 層1 0 2上,供做阻障層1 0 6之化學機械研磨步驟之一Page 8 525242 V. Description of the invention (5) The purpose and many advantages of the present invention will be made clear by the following detailed description of specific embodiments and with reference to the accompanying drawings. 5-4 Detailed description of specific embodiments: The method of the present invention is suitable for removing carbon-rich particles adsorbed on a metal surface. In a specific embodiment of the present invention, a copper / low-k dielectric dual damascene structure is used, as shown in FIG. 1B, as an example of implementing the method of the present invention. FIG. 1B, substrate 1 〇 is a semiconductor substrate, in which a substructure (not shown) having a plurality of elements is formed in the substrate 100, and a metal layer (not shown) is formed in the substrate Above 1 0 0. The low-k dielectric layer 102 may be formed of a spin-on polymer such as an aromatic hydrocarbon, si 1 k, and f 1 a r e. The low-k / {i dielectric layer 102 contains at least 90% of carbon elements and is a carbon-rich layer. A pattern of a trench 1 12 and a via 110 is formed in the low-k dielectric layer 102. The barrier layer 106 is usually a Ta or TaN layer, which is used as a liner layer of the trench 1 1 2 and the via 1 1 0 to prevent copper metal from diffusing into the low-k dielectric layer 1. 0 2 in. A protective layer of silicon nitride (S i 3N 4) or silicon carbide (si 1 ic ο ncarbide) is formed on this low-k dielectric layer 102 for chemical and mechanical use as the barrier layer 106. One of the grinding steps
525242 五、發明說明(6) 終止層1 0 4。化學機械研磨銅金屬係形成一碟形構造( dished structure)於銅金屬層1 〇 8之頂面之虛線下方 〇525242 V. Description of the invention (6) Termination layer 104. The chemical mechanical polishing of the copper metal system forms a dished structure under the dotted line on the top surface of the copper metal layer 108.
Ta或TaN之阻障層1 〇 6為一均勻覆蓋在渠溝1 1 2 及介層洞1 1 0之内外區域之毯覆式層。基於低薄膜應力 、覆蓋能力佳及良好的附著力之考量,Ta或Ta N之阻障層 1 0 6通常以物理氣相沈積法(PVD)形成。 銅金屬層1 0 8係填充於渠溝1 1 2及介層洞1 1〇 中,並且可以PVD、CVD或電鍍方法沈積形成。典型上,銅 金屬層之沈積厚度可從1微米(lum)至數微米(several microns)。 在一般的雙鑲嵌製程中,低k值介電層1 〇 2係以傳 統微影及蝕刻方式經圖案蝕刻兩次。第一次圖案蝕刻在低 k值介電層1 〇 2中形成供做内連線的介層洞1 1 0 ,然 後進行第二次圖案蝕刻在低k值介電層1 〇 2中形成導線 (conductive line)用的渠溝1 1 2 ,如銅線用的渠溝。 參照第二A圖,本發明之一具體實施例中,銅金屬層 1 0 8沈積在阻障層1 0 6上方之後,進行一銅化學機械 研磨步驟2 0 0將此銅金屬層1 0 8平坦化直至阻障層1 0 6。之後,進行一阻障層化學機械研磨步驟2 0 2 ,以The barrier layer 106 of Ta or TaN is a blanket-type layer uniformly covering the area inside and outside the trench 12 and the via hole 110. Based on the considerations of low film stress, good covering ability and good adhesion, the barrier layer 106 of Ta or Ta N is usually formed by physical vapor deposition (PVD). The copper metal layer 108 is filled in the trench 12 and the via hole 110, and can be formed by PVD, CVD, or electroplating. Typically, the thickness of the copper metal layer can be from 1 lum to several microns. In a general dual damascene process, the low-k dielectric layer 102 is pattern-etched twice in a conventional lithography and etching manner. The first pattern etching forms a via hole 1 1 0 for the interconnects in the low-k dielectric layer 1 0 2, and the second pattern etching forms a wire in the low-k dielectric layer 1 0 2 The trenches 1 1 2 for conductive lines, such as trenches for copper lines. Referring to FIG. 2A, in a specific embodiment of the present invention, after the copper metal layer 108 is deposited on the barrier layer 106, a copper chemical mechanical polishing step 2 0 0 is performed on the copper metal layer 108. Plane up to the barrier layer 106. After that, a barrier layer chemical mechanical polishing step 2 02 is performed to
第10頁 j^242 五、發明說明(7) " 一 - " ,1,随障層1 0 6直至終止層1 〇 4 。如第一 B圖所示 工〇此一化學機械研磨步驟期間,由於如上述之銅金屬層 1 8之碟化現象(dishing phenomenon),低k值介電層 2極容易曝露出來並被研磨。因此,許多的富碳顆粒 並吸附在經曝露的銅表面上,而造成雙鑲嵌製程缺陷 ^ : t,在本發明中,使用一酸性水溶液之一化學緩衝研 M ^ ( chemical buffing polishing process) 2 0 4 =片靶壓壓力約為〇 · 5至3 p s丨下,施予在含富碳顆粒Page 10 j ^ 242 V. Description of the invention (7) " a-", 1, followed by the barrier layer 10 6 to the termination layer 1 04. As shown in FIG. 1B, during this chemical mechanical polishing step, the low-k dielectric layer 2 is easily exposed and polished due to the dishing phenomenon of the copper metal layer 18 as described above. Therefore, many carbon-rich particles are adsorbed on the exposed copper surface, causing defects in the dual damascene process. ^: T, in the present invention, chemical buffing polishing process ^ (chemical buffing polishing process) 2 0 4 = the target pressure of the tablet is about 0.5 to 3 ps.
呤:t : ΐ : ί由一適當的化學反應,將此些富碳顆粒移 f :/合液可為一種含有機羧酸(carboxyl ic acid )之,性水洛液,如含有檸檬酸(…仏acid)或草酸( oxalic acid )之酸性又匕、、交、、杰 ,L . ι . 之銨鹽(ammonium caAo/ i 可為包含有機羧酸 後,-化學機械研磨後清:牛:=上的酸性水溶液。最 面t,以除丰盆:1 驟係被施予在經曝露的銅表 面上,以除去其上殘留的雜質。 在銅化學機械研磨期間,低k值介電可处 被曝露出來並被研磨,因此,本 s 1 0 2 T此已 ,夂昭筮-r同 各 ,+知Λ之另一具體實施例中 蒼’、、、弟一 Β圖,在銅化學機械研磨步 ’使用-酸性水— & 3 Q Q①成之後 在晶片施壓壓力約〇. 5至3psi下 研磨步驟3 〇 2 , -適當的化學反應,將吸…上銅表面上,經由 ,進行阻障層化學機械研磨步驟炭顆粒移除。接著 〇 6直至終止層i 〇 4…上^二以移除阻障層1 ^ m 醪性水溶液進行一Pyridine: t: ΐ: ί The carbon-rich particles are removed by an appropriate chemical reaction f: / The solution may be a succinic liquid containing carboxyl ic acid, such as containing citric acid ( … 仏 acid) or oxalic acid (ammonium caAo / i may contain organic carboxylic acid, after chemical-mechanical grinding, the ammonium salt is clear: cattle: = Acidic aqueous solution on the top surface. In order to remove the pots: 1 step is applied to the exposed copper surface to remove residual impurities thereon. During copper chemical mechanical polishing, the low-k dielectric may The parts are exposed and ground, so this s 1 0 2 T is here, 夂 昭 筮 -r with the same, + know Λ In another specific embodiment of the Cang ',,, and brother B picture, in copper chemistry The mechanical polishing step 'use-acid water— & 3 Q Q①After the wafer is pressed at a pressure of about 0.5 to 3 psi, the polishing step 3 〇2,-an appropriate chemical reaction, will suck ... on the copper surface, via, Carry out the chemical mechanical polishing step of the barrier layer to remove the carbon particles. Then 〇6 until the stop layer i 〇4 ... to remove the barrier layer 1 ^ m alkaline aqueous solution
525242 五、發明說明(8) 第二化學緩衝研磨步驟3 0 6 ,在晶片施壓壓力約為0. 5 ^ 至3 p s i下,除去銅表面上的富碳顆粒。此酸性水溶液係含 _ 有一種有機魏酸,如择樣酸或草酸。此外,亦可為一種含 有有機魏酸之銨鹽的酸性水溶液。最後,一化學機械研磨 ’ 後清洗步驟係被施予在經曝露的銅表面上,以除去其上殘 . 留的雜質。 以上所述僅為本發明之較佳具體實施例而已,並非用 以限定本發明之申請專利範圍;凡其它未脫離本發明所揭 示之精神下所完成之等效改變或修飾,均應包含在下述之 申請專利範圍内。525242 V. Description of the invention (8) The second chemical buffer grinding step 3 0 6 removes carbon-rich particles on the copper surface under a wafer pressure of about 0.5 ^ to 3 p s i. This acidic aqueous solution contains _ an organic pelic acid, such as selective acid or oxalic acid. Alternatively, it may be an acidic aqueous solution containing an ammonium salt of organic ferulic acid. Finally, a chemical mechanical polishing 'post-cleaning step is applied to the exposed copper surface to remove the remaining impurities thereon. The above descriptions are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the following Within the scope of the patent application.
第12頁 525242 圖式簡單說明 第 一 A 圖 係 — 一 般 的 銅 /低 k值 介 電 質 雙 鑲 敌 構 造 之 截 面 示 意 圖 , 第 一 B圖係第- - A圖 之 銅 /低 k值 介 電 質 雙 鑲 後 構 造 經 過 一 銅 化 學 機 械 研 磨 步 驟 及 一 阻障 層 化 學 機 械 研 磨 步 驟 之 後 之 截 面 示 意 圖 其 中 經 曝 露 的銅 表 面 發 生 碟 化 現 象 第 A 圖 係 本 發 明 之 一 具體 實 施 例 之 方 法 的 步 驟 流 程 圖 J 及 第 _—— B 圖 係 本 發 明 之 另 一具 體 實 施 例 之 方 法 的 步 驟 流 程 圖 0 主 要 部 分 之 代 表 符 號 ; 1 〇 〇 半 導 體 基 底 1 0 2 低 k值介電層 1 0 4 終 止 層 1 0 6 阻 障 層 1 0 8 銅 金 屬 層 1 1 0 介 層 洞 1 1 2 渠 溝 2 0 0 銅 化 學 機 械 研 磨 2 0 2 阻 障 層 化 學 機 械研 磨 2 0 4 第 一 化 學 緩 衝 研磨525242 on page 12 is a simple illustration of the first A picture series-a general cross section of the copper / low-k dielectric dual-inlay structure, the first B picture is the copper / low-k dielectric of the A-th picture. Cross-sectional view of the structure after the double-mounting process after a copper chemical mechanical polishing step and a barrier layer chemical mechanical polishing step. Among them, the exposed copper surface has a dishing phenomenon. Figure A shows the steps of the method of a specific embodiment of the present invention. Flowchart J and _—— B are flowcharts of the steps of the method of another specific embodiment of the present invention. The representative symbols of the main part 0; semiconductor substrate 1 0 2 low-k dielectric layer 1 0 4 termination Layer 1 0 6 barrier layer 1 0 8 copper metal layer 1 1 0 via hole 1 1 2 trench 2 0 0 Copper chemical mechanical grinding 2 0 2 Barrier layer chemical mechanical grinding 2 0 4 The first chemical slow grinding
第13頁 525242 圖式簡單說明 3 0 0 3 0 2 3 0 4 3 0 6 銅化學機械研磨 第二化學緩衝研磨 阻障層化學機械研磨 化學緩衝研磨Page 13 525242 Brief description of the drawing 3 0 0 3 0 2 3 0 4 3 0 6 Copper chemical mechanical polishing Second chemical buffer polishing Barrier layer chemical mechanical polishing Chemical buffer polishing
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