TW523910B - Method to form at least two memory-cells of a semiconductor memory - Google Patents

Method to form at least two memory-cells of a semiconductor memory Download PDF

Info

Publication number
TW523910B
TW523910B TW089118682A TW89118682A TW523910B TW 523910 B TW523910 B TW 523910B TW 089118682 A TW089118682 A TW 089118682A TW 89118682 A TW89118682 A TW 89118682A TW 523910 B TW523910 B TW 523910B
Authority
TW
Taiwan
Prior art keywords
trench
isolation
trenches
dielectric
layer
Prior art date
Application number
TW089118682A
Other languages
English (en)
Chinese (zh)
Inventor
Dr Martin Schrems
Dr Stefan Gernhardt
Dr Klaus-Dieter Morhard
Maik Stegemann
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Application granted granted Critical
Publication of TW523910B publication Critical patent/TW523910B/zh

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/01Manufacture or treatment
    • H10B12/02Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03Making the capacitor or connections thereto
    • H10B12/038Making the capacitor or connections thereto the capacitor being in a trench in the substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Element Separation (AREA)
TW089118682A 1999-09-14 2000-09-13 Method to form at least two memory-cells of a semiconductor memory TW523910B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19944011A DE19944011B4 (de) 1999-09-14 1999-09-14 Verfahren zur Bildung mindestens zweier Speicherzellen eines Halbleiterspeichers

Publications (1)

Publication Number Publication Date
TW523910B true TW523910B (en) 2003-03-11

Family

ID=7921984

Family Applications (1)

Application Number Title Priority Date Filing Date
TW089118682A TW523910B (en) 1999-09-14 2000-09-13 Method to form at least two memory-cells of a semiconductor memory

Country Status (3)

Country Link
DE (1) DE19944011B4 (fr)
TW (1) TW523910B (fr)
WO (1) WO2001020643A2 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6551874B2 (en) * 2001-06-22 2003-04-22 Infineon Technologies, Ag Self-aligned STI process using nitride hard mask
US6818534B2 (en) * 2002-08-19 2004-11-16 Infineon Technologies Richmond, Lp DRAM having improved leakage performance and method for making same

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4801988A (en) * 1986-10-31 1989-01-31 International Business Machines Corporation Semiconductor trench capacitor cell with merged isolation and node trench construction
KR930003857B1 (ko) * 1987-08-05 1993-05-14 마쯔시다덴기산교 가부시기가이샤 플라즈마 도우핑방법
US5250829A (en) * 1992-01-09 1993-10-05 International Business Machines Corporation Double well substrate plate trench DRAM cell array
US5895255A (en) * 1994-11-30 1999-04-20 Kabushiki Kaisha Toshiba Shallow trench isolation formation with deep trench cap
US5543348A (en) * 1995-03-29 1996-08-06 Kabushiki Kaisha Toshiba Controlled recrystallization of buried strap in a semiconductor memory device
US5643823A (en) * 1995-09-21 1997-07-01 Siemens Aktiengesellschaft Application of thin crystalline Si3 N4 liners in shallow trench isolation (STI) structures
US5905279A (en) * 1996-04-09 1999-05-18 Kabushiki Kaisha Toshiba Low resistant trench fill for a semiconductor device
US5937296A (en) * 1996-12-20 1999-08-10 Siemens Aktiengesellschaft Memory cell that includes a vertical transistor and a trench capacitor
US5867420A (en) * 1997-06-11 1999-02-02 Siemens Aktiengesellschaft Reducing oxidation stress in the fabrication of devices
US5831301A (en) * 1998-01-28 1998-11-03 International Business Machines Corp. Trench storage dram cell including a step transfer device
US6762447B1 (en) * 1999-02-05 2004-07-13 Infineon Technologies North America Corp. Field-shield-trench isolation for gigabit DRAMs
US6184107B1 (en) * 1999-03-17 2001-02-06 International Business Machines Corp. Capacitor trench-top dielectric for self-aligned device isolation

Also Published As

Publication number Publication date
WO2001020643A3 (fr) 2001-10-04
WO2001020643A2 (fr) 2001-03-22
DE19944011A1 (de) 2001-03-22
DE19944011B4 (de) 2007-10-18

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Legal Events

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GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees