523804 A7 B7 五、發明說明（） 發明領域： ''一： ' 本發明係有關於一種減小元件線寬的方法，特別是有 關於在半導體製程中，利用多次沈積及選擇性蝕刻等製程 方法來減小元件的線寬之方法。 發明背景： 在電子元件的線寬進入次微米（Sub-Micro)甚至深次微 米（Deep Sub-Micro)的領域，由於電子元件在有限的空間内 不斷堆疊’為了元件佔用面積的考置和積體電路的運 作效率，使得電子元件進入深次微米的領域時，元件的線 寬需大幅縮小。 但一直以來微影（Lithography)技術都是元件的線寬能 否再進一步縮小的關鍵，因此微影技術在整個半導體製程 中可說是舉足輕重，微影技術不僅影響了元件的集積度 (Integration)及性能，也影響了產能和製造成本。其中光學 破影因其高產能（High Throughout)而成為目前主要的微影 技術之一。 請參考第1圖至第5圖，其所繪示為習知微影製程的 過程之示意圖。首先於第1圖中提供具有材質層20的基材 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） ------------ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製523804 A7 B7 V. Description of the invention () Field of the invention: '' A: '' The present invention relates to a method for reducing the line width of a device, and in particular, to the use of multiple deposition and selective etching processes in a semiconductor process Method to reduce the line width of the component. Background of the Invention: In the field where the line width of electronic components enters the sub-micro or even deep sub-micro, the electronic components are continuously stacked in a limited space. The operating efficiency of the body circuit makes the line width of the component to be greatly reduced when the electronic component enters the field of deep sub-micron. However, Lithography technology has always been the key to whether the line width of components can be further reduced. Therefore, lithography technology plays an important role in the entire semiconductor manufacturing process. Lithography technology not only affects the integration of components. And performance have also impacted capacity and manufacturing costs. Among them, optical image breaking has become one of the main lithography technologies due to its high throughput. Please refer to FIG. 1 to FIG. 5, which are schematic diagrams showing the process of the conventional lithography process. First provide the substrate with the material layer 20 in the first figure. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 x 297 mm) ------------ (Please read the back first (Please note this page before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs
523804 A7 B7 五、發明說明（） 10°如第2圖所示於材質層2〇上形成光阻30。接著在第3 圖中利用微影技術定義出光阻3 0的圖案。然後在第4圖中 移除材質層20以曝露出基材1〇。最後如第5圖所示移除 光阻30，可形成線寬40的材質層20。 目前習知微影成像技術中汞（Hg)燈和添加物氙（xe)、 鑛（Cd)等’是最常被利用的光源，配合濾光設備可產生G_ line(波長 436nm)、H-line(波長 405nm)和 Mine(波長為 365nm)等光源。 不過在電子元件邁入〇·18μιη線寬甚至更微小的 0·13μιη線寬、〇.ΐ〇μιη線寬的世代時，依照Rayleigh理論， 光源可定義出的最小解析度與光波長成正比，在約〇·3 Ομιη 線寬至約0·25μπι線寬的半導體製程中i-Hne光源尚可應 用，但於0.25μπι線寬以下的半導體製程Mine光源已不足 以勝任。於是改用波長較短（約為2 1 〇nm以下）的深紫外線 (Deep UV)範圍的光源來代替Mine光源以製造具有0·20μιη 以下線寬的電子元件。 雖然採用較短波長的曝光光源可提高線寬漸小的電子 元件之解析度，卻造成了較嚴重的薄膜干涉效應（Film Interference Effect)等問題，雖然目前有多種解決的方法， 例如研發和改良光阻、光罩的材質以搭配不同的曝光光 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -------- I « — — — — —111 經濟部智慧財產局員工消費合作社印製 523804 Λ7 Β7 五、發明說明（） 源、改善曝光方法等，但製程的複雜度和成本也同時上升。 此外’除了光學微影技術外，還有電子束（Electronic Beam)微影技術、X-光微影技術等微影技術可應用在 0 ·20μιη以下線寬的半導體製程中。然而電子束微影技術和 X-光微影技術都有其各自的缺點，電子束微影技術雖可得 到小於0.1 μπι的解析度，但受限於其產出量低及設備昂 責’電子束微影技術無法像光學步進機大量生產晶片。而 X-光微影技術需要特殊材質的光罩，以及因X-光微影技術 不能以縮小投影的方式進行曝光，而是透過X-光步進機的 控制，將光罩上的圖形以1 : 1的形式轉換至晶片上，因此 在光罩生產的過程中需要非常高的精確度，亦即光罩生產 過程中需要高於晶圓曝光過程中的精確廑，所以應用於X-光微影技術的光罩非常昂貴，而且X-光微影技術的曝光技 術困難度亦高。 由於縮小電子元件的線寬，都必需搭配相應的製程方 法來實施，但研究和開發這些相應製程的成本高昂，特別 是開發相應的微影技術，更有其技術的瓶頸。於是如何在 半導體製程中保持產品的高可靠度、高準確度和低成本， 同時又能降低電子元件線寬之問題，是目前急欲解決的。 發明目的及概述： 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填冩本頁) 訂· I 1 I I · 經濟部智慧財產局員工消費合作社印製 523804523804 A7 B7 V. Description of the invention (10) A photoresist 30 is formed on the material layer 20 as shown in FIG. 2. Then use the photolithography technique to define the photoresist 30 pattern in Figure 3. Then, in FIG. 4, the material layer 20 is removed to expose the substrate 10. Finally, as shown in FIG. 5, the photoresist 30 is removed to form a material layer 20 with a line width of 40. At present, in conventional lithography imaging technology, mercury (Hg) lamps and additives xenon (xe), minerals (Cd), etc. are the most commonly used light sources, and G_line (wavelength 436nm), H- Line (wavelength 405nm) and Mine (wavelength 365nm) and other light sources. However, as electronic components enter the generation with a line width of 0.18 μm or even a smaller line width of 0.13 μm and a line width of 0.10 μm, according to Rayleigh theory, the minimum resolution that a light source can define is directly proportional to the wavelength of light. The i-Hne light source is still applicable in semiconductor processes with a line width of about 0.30 μm to a line width of about 0.25 μm, but Mine light sources in a semiconductor process below a line width of 0.25 μm are no longer sufficient. Therefore, a light source in the deep ultraviolet (Deep UV) range with a shorter wavelength (about 2 10 nm or less) is used instead of the Mine light source to manufacture electronic components having a line width of 0.20 μm or less. Although the use of a shorter-wavelength exposure light source can improve the resolution of electronic components with decreasing line widths, it has caused more serious problems such as film interference effect. Although there are many solutions, such as research and development and improvement Material of photoresist and photomask to match different exposure light This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) ----- --- I «— — — — — 111 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs's Consumer Cooperatives 523804 Λ7 Β7 V. Description of the invention () Source, improved exposure methods, etc., but the complexity and cost of the process also increased. In addition, in addition to optical lithography technology, there are lithography technologies such as Electronic Beam lithography technology and X-ray lithography technology, which can be applied to semiconductor processes with line widths below 0. 20 μm. However, both electron beam lithography and X-ray lithography have their own shortcomings. Although electron beam lithography can obtain a resolution of less than 0.1 μm, it is limited by its low output and equipment responsibilities. Beam lithography cannot mass produce wafers like an optical stepper. The X-ray lithography technology requires a special material mask, and because the X-ray lithography technology can not be used to reduce the exposure, it is controlled by the X-ray stepper. The 1: 1 format is converted to the wafer, so very high accuracy is required in the mask production process, that is, the mask production process needs higher precision than the wafer exposure process, so it is applied to X-rays. The lithography mask is very expensive, and the exposure technique of X-ray lithography is also difficult. Due to the reduction of the line width of electronic components, they must be implemented with corresponding process methods, but the cost of research and development of these corresponding processes is high, especially the development of corresponding lithography technology, and its technical bottlenecks. Therefore, how to maintain the high reliability, high accuracy, and low cost of the products in the semiconductor manufacturing process, and at the same time reduce the line width of electronic components is an urgent need to solve. Purpose and summary of the invention: This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the notes on the back before filling out this page) Revision · I 1 II · Employees of Intellectual Property Bureau, Ministry of Economic Affairs Printed by Consumer Cooperatives 523804
經濟部智慧財產局員工消費合作社印製 五、發明說明（） 1於上述之發明背景中，在電子元件的線寬進入次微 米甚至深次微米的領域，由於元件的線寬需大幅縮小，所 以各種半導體製程所要求的精準度就愈來愈高，因此必須 研發相應的製程方法。但是研究和開發這些相應製程的成 本兩叩’其中特別是研發各種相應的微影技術，所花費的 時間和成本都十分可觀。因此如何在半導體製程中保持產 口口的同可罪度、高準峰度和低成本，同時又能降低電子元 件線寬之問題，是目前急欲解決的。 本發明的主要目的為提供了一種減小元件線寬的方 法’用以在半導體製程中，將元件的線寬減小，達到於佈 線時增加圖案的解析度，降低積體電路的設計困難度，從 叩可提升產出量。同時更由於本發明所提供之減小元件線 見的方法只在製程步驟上稍加改良，便可達到減小電子元 件線寬的目的，因此產品的成本可大為降低。 根據以上所述之目的，本發明提供了一種減小元件線 寬的方法，至少包括：提供基材；於基材上形成材質層； 於材質層上定義出犧牲層（Sacrificial Layer);於犧牲層上 形成共形（Conformal)於犧牲層的空間層（Spacer Layer);於 空間層上形成罩幕層（Hard Mask Layer);平坦化罩幕層以 約曝露出空間層；以罩幕層作為罩幕，移除空間層和犧牲 5 (請先閱讀背面之沒意事項再填寫本頁)Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (1) In the above background of the invention, the line width of electronic components enters the field of sub-micron or even deep sub-micron, because the line width of the component needs to be significantly reduced, so The precision required by various semiconductor processes is getting higher and higher, so corresponding process methods must be developed. However, the cost of research and development of these corresponding processes, especially the development of various lithographic technologies, is considerable. Therefore, the problem of how to maintain the guiltiness, high accuracy, and low cost of semiconductor products in the semiconductor manufacturing process, and at the same time reduce the line width of electronic components is an urgent need to solve. The main purpose of the present invention is to provide a method for reducing the line width of a component 'to reduce the line width of a component in a semiconductor process, to increase the resolution of a pattern during wiring, and to reduce the difficulty of designing integrated circuits. It can increase output. At the same time, because the method for reducing the component line provided by the present invention can only be slightly improved in the process steps, the purpose of reducing the line width of the electronic component can be achieved, so the cost of the product can be greatly reduced. According to the above-mentioned purpose, the present invention provides a method for reducing the line width of an element, which at least includes: providing a substrate; forming a material layer on the substrate; defining a sacrificial layer on the material layer; Form a Conformal space layer on the sacrificial layer; Form a Hard Mask Layer on the space layer; Flatten the cover layer to expose the space layer approximately; Use the cover layer as Mask, remove space layer and sacrifice 5 (Please read the unintentional matter on the back before filling this page)
523804 經濟部智慧財產局員工消費合作社印製 Α7 Β7 五、發明說明（） 層直至約曝曬出材質層；以罩幕層作為罩幕，移除材質層， 直至約曝露出基材；以及移除罩幕層和空間層，以曝露出 材質層。由於本發明所提供之減小元件線寬的方法只需在 製程步驟上猶加改良，便可達到減小電子元件線寬的目 的’因此能在降低電子元件線寬的同時，又可保持產品的 高可靠度、高準確度和低成本，以及提升產出量。 圖式簡單說明： 本發明的較佳實施例將於往後之說明文字中辅以下列 圖形做更詳細的闡述，其中： 第1圖係繪示習知微影製程的過程之示意圖。 第2圖係繪示習知微影製程的過程之示意圖。 第3圖係繪示習知微影製程的過程之示意圖。 第4圖係繪示習知微影製程的過程之示意圖。 第5圖係繪示習知微影製程的過程之示意圖。 第ό圖係繪·示利用本發明之一實施例的過程之示意 圖。 第7圖係緣示利用本發明之一實施例的過程之示意 圖。 第8圖係繪示利用本發明之一實施例的過程之示意 圖。 本纸張又度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------丨丨-------I--訂·丨丨------ (請先閱讀背面之注意事項再填寫本頁) 523804 A7 _B7_ 五、發明說明（） 第 9圖係繪示利用本發明之一實施例的過程之示意 圖。 第1 0圖係繪示利用本發明之一實施例的過程之示意 圖。 第 1 1圖係繪示利用本發明之一實施例的過程之示意 圖。 第1 2圖係繪示利用本發明之一實施例的過程之示意 圖。 第1 3圖係繪示利用本發明之一實施例的過程之示意 圖。 圖號對照說明： (請先閱讀背面之注意事項再填寫本頁) -flu i i f e n flu an n n fla— el - 經濟部智慧財產局員工消費合作社印製 D 0N mw ο 4 明說細詳 明發 10 基材 20 材質層 30 光阻 40 線寬 100 基材 105 材質層 110 犧牲層 115 空間層 120 罩幕層 125 線寬 130 習知線寬 135 開口 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 523804 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（） 請參考第6圖，其所繪示為利用本發明之一實施例的 過程之不意圖。首先提供基材1〇〇和在基材上形成材質層 105，其中材質層1〇5的材質並不限制且可為導體、半導體 或非導體。 接著請參考第7圖’其所繪示為利用本發明之一實施 例的過程之示意圖。然後於材質層1〇5上形成並定義出犧 牲層110，使得此犧牲層110具有開口 135，且開口 135具 有習知線寬130。此外犧牲層11〇的材料需與材質層1〇5 的材料不同，例如可採用氧化物作為此犧牲層11〇的材 料，而此犧牲層110的厚度約為1〇〇〇A至5〇〇〇人。 然後請參考第8圖，其所繪示為利用本發明之一實施 例的過程之示意圖。在第8圖中，於被定義的犧牲層U0 上形成與犧牲層110共形的空間層115,使得第7圖之開 口 135成為開口 140,於是習知線寬13〇被減小為線寬 125。另外此空間層115的厚度約為5—至咖从，而立 此空間層115的材料也需與材質^ 1〇5的材料不同，例如 可採用氧化物作為此空間| 115的材料。此外，由於在本 發明所提供之減小元件線寬方法的後續步驟中，需要進行 選擇性移除的步驟（如選擇性蝕刻），因此空間層與犧 牲層UG需具有不同的#刻速率，以利於選擇除的少 驟進行。 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 χ 2町 ------------^^裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 523804 Λ7 B7 五、發明說明（） 經濟部智慧財產局員工消費合作社印製 請參考第9圖，其所繪示為利用本發明之一實施例的 過程之示意圖。如第9圖所示，於空間層丨丨5上形成罩幕 層120’同時亦因後續步驟中需要進行選擇性移除的步驟， 因此罩幕層1 20具有的蝕刻速率亦與空間層1 1 $和犧牲層 no的蝕刻速率不同。而為了跟空間層115和犧牲層110 的材料有所區別，則可採用氮化物作為此罩幕層丨2〇的材 料。 凊參考第10圖，其所繪示為利用本發明之一實施例的 過程之示意圖。如第10圖所示，對罩幕層i20進行平坦化 的步驟，以約曝露出空間層丨丨5。 接著請參考第11圖，其所繪示為利用本發明之一實施 例的過程之示意圖。對第1 〇圖中之結構進行選擇性移除步 驟，如進行選擇性蝕刻步驟。由於罩幕層12〇的材料（如氮 化物）與空間層1 15和犧牲層1 1〇的材料（如氧化物）不同， 因此可藉由選擇性蝕刻步驟，保留罩幕層12〇,同時將空 間層115和犧牲層110移除以曝露出材質層ι〇5，於是得 到如第1 1圖所示之結構。 然後請參考第1 2圖，其所繪示為利用本發明之一實施 例的過程之示意圖。接著亦由於罩幕層12〇的材料（如氣化 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)523804 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () layer until the material layer is exposed; using the cover layer as the cover, remove the material layer until the substrate is exposed; and remove Mask layer and space layer to expose the material layer. Because the method for reducing the line width of components provided by the present invention only needs to be improved in the process steps, the purpose of reducing the line width of electronic components can be achieved. Therefore, the line width of the electronic components can be reduced while maintaining the product. High reliability, high accuracy and low cost, as well as increased output. Brief description of the drawings: The preferred embodiment of the present invention will be described in more detail in the following explanatory text with the following figures, where: Figure 1 is a schematic diagram showing the process of the conventional lithography process. FIG. 2 is a schematic diagram showing a process of a conventional lithography process. FIG. 3 is a schematic diagram showing a process of a conventional lithography process. FIG. 4 is a schematic diagram showing a process of a conventional lithography process. FIG. 5 is a schematic diagram illustrating a process of a conventional lithography process. The sixth diagram is a schematic diagram showing a process using an embodiment of the present invention. Fig. 7 is a schematic diagram showing a process using one embodiment of the present invention. Fig. 8 is a schematic diagram showing a process using an embodiment of the present invention. This paper is again applicable to China National Standard (CNS) A4 specification (210 X 297 mm) -------- 丨 丨 ------- I--Order · 丨 丨 ----- -(Please read the precautions on the back before filling this page) 523804 A7 _B7_ V. Description of the Invention () Figure 9 is a schematic diagram showing the process of using one embodiment of the present invention. Fig. 10 is a schematic diagram showing a process using an embodiment of the present invention. FIG. 11 is a schematic diagram showing a process using an embodiment of the present invention. Fig. 12 is a schematic diagram showing a process using an embodiment of the present invention. Fig. 13 is a schematic diagram showing a process using an embodiment of the present invention. Illustration of comparison of drawing numbers: (Please read the notes on the back before filling this page) -flu iifen flu an nn fla— el-Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs D 0N mw ο 4 20 Material layer 30 Photoresistor 40 Line width 100 Base material 105 Material layer 110 Sacrifice layer 115 Space layer 120 Cover layer 125 Line width 130 Known line width 135 Opening This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) 523804 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () Please refer to FIG. 6, which shows the intention of using the process of one embodiment of the present invention. First, a substrate 100 is provided and a material layer 105 is formed on the substrate. The material of the material layer 105 is not limited and may be a conductor, a semiconductor, or a non-conductor. Please refer to FIG. 7 ', which illustrates a schematic diagram of a process using an embodiment of the present invention. A sacrificial layer 110 is then formed and defined on the material layer 105, so that the sacrificial layer 110 has an opening 135, and the opening 135 has a conventional line width 130. In addition, the material of the sacrificial layer 110 must be different from the material of the material layer 105. For example, an oxide can be used as the material of the sacrificial layer 110, and the thickness of the sacrificial layer 110 is about 1000 A to 500. 〇 person. Please refer to FIG. 8, which illustrates a schematic diagram of a process using an embodiment of the present invention. In FIG. 8, a space layer 115 conforming to the sacrificial layer 110 is formed on the defined sacrificial layer U0, so that the opening 135 in FIG. 7 becomes the opening 140, so the conventional line width 13 is reduced to the line width. 125. In addition, the thickness of this space layer 115 is about 5 to 100 cm, and the material of this space layer 115 also needs to be different from the material ^ 105. For example, an oxide can be used as the material of this space | 115. In addition, since in the subsequent steps of the method for reducing the line width of the device provided in the present invention, a selective removal step (such as selective etching) is required, the space layer and the sacrificial layer UG need to have different #etch rates, In order to facilitate the selection of fewer steps. This paper size applies to China National Standard (CNS) A4 specifications (21〇χ 2 町 ------------ ^^ 装 -------- Order -------- -(Please read the notes on the back before filling this page) 523804 Λ7 B7 V. Description of the invention () Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Please refer to Figure 9, which is shown as an implementation using one of the inventions Schematic diagram of the example process. As shown in FIG. 9, the mask layer 120 ′ is formed on the space layer 丨 5 and at the same time, because the selective removal step is required in the subsequent steps, the mask layer 120 has the etching The rate is also different from the etching rate of the space layer 1 1 $ and the sacrificial layer no. In order to be different from the materials of the space layer 115 and the sacrificial layer 110, nitride can be used as the material of this mask layer. 2 Referring to FIG. 10, which is a schematic diagram of a process using an embodiment of the present invention. As shown in FIG. 10, the step of planarizing the mask layer i20 is to expose the space layer 5 approximately. Please refer to FIG. 11, which illustrates a schematic diagram of a process using an embodiment of the present invention. For the knot in FIG. 10 A selective removal step is performed, such as a selective etching step. Since the material of the mask layer 120 (such as nitride) is different from the materials of the space layer 115 and the sacrificial layer 110 (such as oxide), Through the selective etching step, the mask layer 120 is retained, while the space layer 115 and the sacrificial layer 110 are removed to expose the material layer ι05, so that the structure shown in FIG. 11 is obtained. Figure 12 is a schematic diagram showing the process of using an embodiment of the present invention. Then, because of the material of the cover layer 120 (such as gasification 9), this paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) (Please read the notes on the back before filling this page)
▼ · ·ϋ I ·ϋ n n n m 一 I n n HI I ϋ ϋ* n I I 523804 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 物）與材質層105的材料 1才不同，因此可藉由選擇性移除步驟 (如選擇性蝕刻步驟），俘 %留罩幕層12〇，同時將材質層1〇5 移除以曝露出基材100 , π ^ 於疋得到如第1 2圖所示之結構。 又或可藉由鉍用適•的選擇性移除步驟，將第㈧圖所示之 π構中的工間| 115、犧牲層11()和材質層⑻同時移除 掉，而得到如第12圖所示之結構。 °月’考第1 3圖’其所緣示為利用本發明之-實施例的 過程之不意圖。最後藉由選擇性移除步驟（如選擇性姓刻步 驟）’將冑12圖中之罩幕層m和空間層i 15移除，就可 得到如第1 3圖所示之結構。 在本發明所提供之減小元件線寬的方法中，係藉由在 犧牲層110上再形成一層共形的空間層115，於是元件的 I知線見130(如第7圖所示）則被減小，再利用罩幕層12〇 作罩幕以疋義出比習知線寬13〇小的線寬125(如第13圖所 示），如此就可輕易達到減小元件線寬的目的。 本發明之優點為本發明提供了一種減小元件線寬之方 法，特別係應用在半導體製程中的。由於本發明之減小元 件線寬的方法，係利用多次沈積及選擇性移除的方法來達 到減小半導體元件線寬的目的，因此在製程上並不會增加 實施的困難度，且應用在目前的半導體製程中，可有效將 裝--------tr--------- (請先閱讀背面之注意事項再填寫本頁) 10 523804 Λ7 B7 ---------^------ 五、發明説明（） 電子元件之線寬進一步減小約0.02μιη至0 2μιη(視製程環 境而定），使得成本得以降低，同時亦能保持電子元件的可 靠度。 如熟悉此技術之人員所瞭解的，以上所述僅為本發明 之較佳實施例而已，並非用以限定本發明之申請專利範 圍；凡其它未脫離本發明所揭示之精神下所完成之等效改 變或修飾’均應包含在下述之申請專利範圍内。 ------------4|^裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公蜚）▼ · · ϋ I · ϋ nnnm-I nn HI I ϋ n * n II 523804 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. The description of the invention (object) and material 1 of the material layer 105 are different, so Through a selective removal step (such as a selective etching step), the capture layer remains at 120 °, and the material layer 105 is removed to expose the substrate 100, and π ^ is obtained as shown in FIG. 12 The structure shown. Or, by using a suitable selective removal step of bismuth, the workshop in the π structure shown in the second figure | 115, the sacrificial layer 11 () and the material layer ⑻ can be removed at the same time, so as to obtain Figure 12 shows the structure. The reason for "Monthly Fig. 13" is shown as an unintended use of the process of the embodiment of the present invention. Finally, through a selective removal step (such as a selective surname engraving step) ', the mask layer m and the space layer i 15 in Fig. 12 are removed, and the structure shown in Fig. 13 can be obtained. In the method for reducing the line width of the device provided by the present invention, a conformal space layer 115 is formed on the sacrificial layer 110, so the I-line of the device is 130 (as shown in FIG. 7). Is reduced, and then the mask layer 120 is used as a mask to define a line width 125 smaller than the conventional line width 13 (as shown in FIG. 13), so that the component line width can be easily reduced. purpose. The advantage of the present invention is to provide a method for reducing the line width of the device, which is especially applied to the semiconductor process. Because the method for reducing the line width of the device of the present invention uses the method of multiple deposition and selective removal to achieve the purpose of reducing the line width of the semiconductor device, the implementation process does not increase the difficulty of implementation, and the application In the current semiconductor manufacturing process, you can effectively load -------- tr --------- (Please read the precautions on the back before filling this page) 10 523804 Λ7 B7 ---- ----- ^ ------ 5. Description of the invention () The line width of electronic components is further reduced by about 0.02μιη to 0 2μιη (depending on the process environment), which reduces the cost and also maintains the electronics. Component reliability. As will be understood by those familiar with this technology, the above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application for the present invention; all others completed without departing from the spirit disclosed by the present invention, etc. "Effective changes or modifications" should be included in the scope of patent applications described below. ------------ 4 | ^ 装 -------- Order --------- (Please read the notes on the back before filling this page) Wisdom of the Ministry of Economic Affairs The paper size printed by the Property Cooperative's Consumer Cooperative is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 gong)