I 604twf.doc/Jimmy/002 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（i ) 本發明是有關於一種金氧半導體（Metal Oxide Semiconductor，MOS )元件的製造方法，且特別是有關 於一種形成MOS元件之閘氧化層（Gate Oxide )的方法。 隨著半導體技術的演進，一般皆朝向較大晶片的製 作，及較小線寬的MOS元件設計，如此才能使大小相同的 積體電路具有較強的功能與較低的成本。然而，相對於上 述的發展，則必須不斷克服製程上所產生的某些問題。例 如當元件尺寸不斷地的遞減，所形成操作電壓的降低。爲 了使上述操作電壓在降底的情況下，元件仍能得到足夠的 電流及操作的速度，其中，最有效的方法便是降低閘氧化 層形成的厚度。一般來說，以目前線寬達0.35〜0.5 // m ’ 3.3 V的操作條件下，閘氧化層厚度已降至約7〇A左右。未 來，因應線寬的縮小，在2.5V的操作條件下，.閛氧化層厚 度則須降至30〜50Α。 圖1Α〜ID繪示的便是一種傳統形成MOS元件中’ 閘氧化層及閘極的流程示意圖。 首先’請參照第1A圖，提供一半導體基底10，例如 爲矽基底，並在半導體基底10上形成一絕緣層12，例如 爲乾式氧化法所形成的一二氧化矽層，依MOS元件的操作 電壓所需的厚度，以作爲閘氧化層之用。 接著，請參照第1B圖，在半導體基底1〇上形成一導 電層I4，例如爲一複晶矽層與一矽化鎢（WSix )所組成 的一複晶砂化金屬層（Polycide )，以覆蓋絕緣層12 ’此 導電層14係作爲MOS元件的閘極之用。 3 本紙浪尺度適用中國國家檩準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) · ΐτ 1604twf.doc/Jimmy/002 A7 ^----_ 五、發明説明（^ ) 之後，請參照第1C圖，利用微影（Photolithography ) 製程在特定的位置上定義出一光阻層16。 最後，請參照第1D圖，利用上述形成的光阻層16爲 罩幕（Mask )，蝕刻導電層14，以形成一閘極14a，並 去除光阻層16。 然而，當上述形成的閘氧化層厚度愈來愈薄，例如厚 度已小於約7〇A以下，在蝕刻形成閘極14a時，可能受限 於蝕刻機台等因素，造成蝕刻時導電層14與絕緣層12的 蝕刻選擇性不佳，產生所形成的閘氧化層有凹陷（Pitted) 等問題。 因此，本發明的主要目的，便是在改善習知閘氧化餍 的製造程序，使形成較薄的閘氧化層厚度時，不再產生0 陷的現象。 根據本發明的主要目的，提供一種形成金氧半元件之 閘氧化層的方法，包括下列步驟： 提供一半導體基底，並在半導體底上形成一第一絕緣 層； 經濟部肀央標準局員工消費合作社印製 (請先閲讀背面之注意事項存填寫本貫) 定義第一絕緣層，以在特定的位置上蝕刻形成一暴露 出半導體基底的開口； 依序在第一絕緣層上及開口內，形成一第二絕緣層及 一導電層； 利用化學機械硏磨法去除第一絕緣層上的第二絕緣餍 及導電層，僅剩平坦化後於開口內的第二絕緣層及導電 層；以及 4 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） A7 B7 經濟部中央標準局員工消費合作社印製 1604twf.doc/Jimmy/〇〇2 五、發明説明（,） 去除導電層兩側的第二絕緣層，及部份第一絕緣層’ 以形成於半導體基底上的第一絕緣層爲一閘氧化層’閘氧 化層上的導電層爲一閘極，及未被触刻掉的部份第一絕緣 層爲一第三絕緣層。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式’作詳 細說明如下。 圖示之簡單說明： 第1A〜1D圖繪示習知一種形成MOS元件中，閘氧 化層及閘極的流程示意圖； 第2A〜2F圖繪示本發明之較佳實施例，一種形成 MOS元件之閘氧化層及閘極的流程示意圖。 實施例 首先，請參照第2A圖，提供一半導體基底20，例如 爲一矽基底，並在半導體基底20上形成一第一絕緣層22， 例如爲一二氧化砂層。 接著’請參照第2B圖，利用微影製程在特定的位置 上，蝕刻定義第一絕緣層22，以形成一暴露出半導體基底 20的開口 24。 後續’請參照第2C圖，在半導體基底20上形成一第 二絕緣層26，例如以熱氧化法所形成的一二氧化矽層，其 厚度則視MOS元件的需要，例如爲30〜50A，以覆蓋在 第一絕緣層22上及開口 24內。 之後’請參照第2D圖5沈積一導電層28，例如爲一 5 本紙張尺度適用中國國家標準（CNS M4規格（210X297公釐） (請先閎讀背面之注意事項再填寫本頁)I 604twf.doc / Jimmy / 002 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (i) The present invention relates to a method for manufacturing a metal oxide semiconductor (MOS) device, and is particularly The invention relates to a method for forming a gate oxide layer of a MOS device. With the evolution of semiconductor technology, generally the production of larger wafers and the design of MOS devices with smaller line widths can make integrated circuits of the same size have stronger functions and lower costs. However, relative to the above-mentioned developments, certain problems arising from the process must be continuously overcome. For example, as component sizes continue to decrease, the resulting operating voltage decreases. In order to make the above operating voltage lower, the device can still obtain sufficient current and operating speed. Among them, the most effective method is to reduce the thickness of the gate oxide layer. Generally speaking, under the current operating conditions of the line width of 0.35 ~ 0.5 // m ′ 3.3 V, the thickness of the gate oxide layer has been reduced to about 70A. In the future, to reduce the line width, under the 2.5V operating conditions, the thickness of the samarium oxide layer must be reduced to 30 ~ 50A. 1A to 1D are schematic diagrams of a conventional process for forming a gate oxide layer and a gate electrode in a MOS device. First, please refer to FIG. 1A, provide a semiconductor substrate 10, such as a silicon substrate, and form an insulating layer 12 on the semiconductor substrate 10, such as a silicon dioxide layer formed by a dry oxidation method, according to the operation of a MOS device The thickness required for the voltage to act as a gate oxide. Next, referring to FIG. 1B, a conductive layer I4 is formed on the semiconductor substrate 10, for example, a polycrystalline sanded metal layer (Polycide) composed of a polycrystalline silicon layer and a tungsten silicide (WSix) to cover. Insulating layer 12 ′ The conductive layer 14 is used as a gate of a MOS device. 3 This paper scale is applicable to China National Standards (CNS) A4 (210X297 mm) (Please read the notes on the back before filling this page) · ΐτ 1604twf.doc / Jimmy / 002 A7 ^ ----_ V. After explaining the invention (^), please refer to FIG. 1C, and use a photolithography process to define a photoresist layer 16 at a specific position. Finally, referring to FIG. 1D, using the photoresist layer 16 formed as a mask, the conductive layer 14 is etched to form a gate electrode 14a, and the photoresist layer 16 is removed. However, when the thickness of the gate oxide layer formed above is getting thinner, for example, the thickness is less than about 70 A, the gate electrode 14a may be formed by etching, which may be limited by factors such as an etching machine, and the conductive layer 14 and The etching selectivity of the insulating layer 12 is not good, and the formed gate oxide layer has problems such as being pitted. Therefore, the main object of the present invention is to improve the manufacturing process of the conventional gate holmium oxide, so that when the thickness of the thin gate oxide layer is formed, the phenomenon of zero depression is no longer generated. According to the main purpose of the present invention, a method for forming a gate oxide layer of a metal-oxide half-element is provided, which includes the following steps: providing a semiconductor substrate and forming a first insulating layer on the semiconductor substrate; consumption by employees of the Central Standards Bureau of the Ministry of Economic Affairs Printed by the cooperative (please read the precautions on the back and fill in the original text) Define the first insulating layer to etch to form an opening exposing the semiconductor substrate at a specific position; sequentially on the first insulating layer and inside the opening, Forming a second insulating layer and a conductive layer; removing the second insulating layer and the conductive layer on the first insulating layer by a chemical mechanical honing method, leaving only the second insulating layer and the conductive layer in the opening after planarization; and 4 This paper size applies to Chinese National Standards (CNS) A4 specifications (210X297 mm) A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 1604twf.doc / Jimmy / 〇〇2 5. Description of the invention (,) A second insulating layer on the side, and a portion of the first insulating layer 'with the first insulating layer formed on the semiconductor substrate as a gate oxide layer and the conductive layer on the gate oxide layer as a The gate and a portion of the first insulation layer that is not touched away is a third insulation layer. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below and described in detail with reference to the accompanying drawings' as follows. Brief description of the diagrams: Figures 1A to 1D are schematic diagrams showing a conventional process for forming a gate oxide layer and a gate electrode in a MOS device; Figures 2A to 2F illustrate a preferred embodiment of the present invention, a method for forming a MOS device The schematic diagram of the gate oxide layer and gate process. Embodiment First, referring to FIG. 2A, a semiconductor substrate 20, such as a silicon substrate, is provided, and a first insulating layer 22, such as a sand dioxide layer, is formed on the semiconductor substrate 20. Next, referring to FIG. 2B, the first insulating layer 22 is defined by etching using a lithography process at a specific position to form an opening 24 that exposes the semiconductor substrate 20. In the following, please refer to FIG. 2C, a second insulating layer 26 is formed on the semiconductor substrate 20, such as a silicon dioxide layer formed by a thermal oxidation method, and its thickness depends on the needs of the MOS device, for example, 30 ~ 50A, So as to cover the first insulating layer 22 and the opening 24. After that, please refer to FIG. 2D and FIG. 5 to deposit a conductive layer 28, such as a 5 paper size applicable to the Chinese national standard (CNS M4 specification (210X297 mm) (Please read the precautions on the back before filling in this page)
1604twf.doc/Jimmy/002 A 7 _B7 五、發明説明（Y) 複晶砂層與一砂化鎢層所組成的一複晶砂化金屬層，以覆 蓋在第二絕緣層26上並塡滿開口 24。 然後，請參照第2E圖，利用化學機械硏磨法 (Chemical Mechanical Polishing > CMP )去除第一絕緣 層22上的第二絕緣層26及該導電層28，僅剩平坦化後於 開口 24內的第二絕緣層26a及導電層28a。 最後，請參照第2F圖，去除導電層28a兩側的第二絕 緣層26a，以形成一閘氧化層26b，及去除部份第一絕緣 層22 ’例如以RCA的濕鈾刻法，將第一絕緣層22餓刻形 成第三絕緣層2〗a，而第三絕緣層22a的厚度稍厚於所形 成的閘氧化層26a ’例如所形成的閘氧化層厚度爲3〇φΑ時， 形成的第三閘氧化層22a的厚度約爲100Α。如此可避免在 蝕刻第一絕緣層22時，造成側向底切（Undercut )，使 閘氧化層26b產生凹陷現象。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閲讀背面之注意事項再填寫本頁)1604twf.doc / Jimmy / 002 A 7 _B7 V. Description of the Invention (Y) A composite crystallized sand metal layer composed of a composite crystal sand layer and a sanded tungsten layer to cover the second insulating layer 26 and fill the opening. twenty four. Then, referring to FIG. 2E, the second insulating layer 26 and the conductive layer 28 on the first insulating layer 22 are removed by chemical mechanical polishing (CMP). Only the planarization is left in the opening 24. The second insulating layer 26a and the conductive layer 28a. Finally, referring to FIG. 2F, the second insulating layer 26a on both sides of the conductive layer 28a is removed to form a gate oxide layer 26b, and a portion of the first insulating layer 22 'is removed, for example, by RCA wet uranium etching method An insulating layer 22 is formed to form a third insulating layer 2a, and the thickness of the third insulating layer 22a is slightly thicker than the formed gate oxide layer 26a '. For example, when the formed gate oxide layer has a thickness of 30? A, The thickness of the third gate oxide layer 22a is about 100A. In this way, when the first insulating layer 22 is etched, a side undercut is caused, so that the gate oxide layer 26b is depressed. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the notes on the back before filling this page)
經濟部中央標準局員工消費合作社印製 6 本紙張尺度適用中國國家榡準（CNS ) A4規格（210X297公釐）Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 6 This paper size is applicable to China National Standard (CNS) A4 (210X297 mm)