554471 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（） 發明領域： 本發明係有關於一種浮置閘極（Floating Gate)之製造 方法’特別是有關於一種縮小兩相鄰浮置閘極之間的距離 並增加浮置閘極面積之方法。 發明背景： 隨著積體電路製程技術的快速發展，電子元件的尺寸也 不斷地縮小。在製作這些電子元件的技術中，用以進行電路 佈局圖案之轉移的微影（Photolithography)技術，對電子元件 之微縮化發展具有關鍵性的影響。 在半導體積體電路之積集度快速增加以因應電子元件 輕薄短小之需求的同時，對微影技術所能達到之線幅寬度 的要求也日益嚴苛。然而，目前由於微影技術所能提供之 解析能力，受到曝光光源的限制，而使得電子元件的微縮 化發展面臨瓶頸。因此，如何再進一步地將現今高積集产 之電子元件的體積予以縮小，已是相當困難的挑戰，而成 為眾所努力的目標。 目前，在例如分離式閘極快閃記憶晶胞（Split Gate F*iash554471 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Field of the Invention: The present invention relates to a method of manufacturing a floating gate (especially to a method for reducing two adjacent floating gates). The method of setting the distance between the gates and increasing the area of the floating gates. Background of the Invention: With the rapid development of integrated circuit manufacturing technology, the size of electronic components has also been continuously reduced. Among the technologies for making these electronic components, the photolithography technology used to transfer circuit layout patterns has a critical impact on the miniaturization of electronic components. While the accumulation of semiconductor integrated circuits is rapidly increasing to meet the requirements of light, thin, and short electronic components, the requirements for the line width that lithography technology can achieve are becoming increasingly stringent. However, at present, the resolution capabilities provided by lithography technology are limited by the exposure light source, which makes the development of electronic components face a bottleneck. Therefore, how to further reduce the volume of today's high-volume electronic components has become a very difficult challenge, and it has become a goal for everyone. Currently, for example, Split Gate F * iash
Cell)的製作過程中，其浮置閘極之圖案定義的進行都係採用 微影技術。然而’如同以上所述，由於曝光光源的限制，/ 影技術所能達到之線寬尺寸也因此而受到限制。如此— 來，也就無法輕易地藉由微影技術來縮小兩相鄰之！ 〜/t罝閘 極間的距離，更無法藉此來達到縮小分離式閘極快閃記憶 晶胞的目的。 2 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公楚) ' -- ......................、可.........Φ (請先~閲讀背面之注意事項再填寫本頁) 554471During the production process of the cell, the pattern definition of the floating gate is performed by lithography technology. However, as mentioned above, due to the limitation of the exposure light source, the line width size that can be achieved by the shadow technology is also limited. That's it — it's not easy to shrink two adjacent ones by lithography! The distance between the gates of ~ / t 罝 can not be used to achieve the purpose of reducing the size of the discrete gate flash memory cell. 2 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297). .... Φ (Please read the notes on the back before filling in this page) 554471
五、發明説明（） 此外，目前所採用之自我對準（Self_aligned)浮置閘極的 製程技術，不僅製作過程較為複雜，而且常會在溝渠隔離結 構與半導體基材之間產生凹槽’或產生'複晶梦材料殘留。因 而，不但元件之電性品質受到嚴重影響，且製程可靠度與產 品良率皆因此而下降。 發明目的及概述： 鑒於上述之發明背景中，受到微影製程的限制，浮置 閘極之間的距離無法獲得有效縮小，而無法縮減晶胞的尺 寸。再者，目前所採用之自我對準浮置閘極的製程不僅過 於複雜，且製程可靠度不佳。 因此，本發明的主要目的之一就是在提供一種縮減浮 置閘極間之距離的方法，其係利用複晶矽（polysilicon)層上 之覆蓋層（Cap Layer)以及覆蓋層中之開口上的間隙壁 (Spacer)作為定義閘極複晶矽層的蝕刻罩幕。因此，可有效 縮減兩相鄰閘極間之距離。 本發明之另一目的就是因為藉由複晶矽層上炙覆蓋層 及覆蓋層之開口上的間隙壁即可縮小浮置閘極間之距離， 而不會受限於微影製程，亦較自我對準製程簡單而易於進 行。 經濟部智慧財產局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 本發明之再一目的就是因為以複晶矽層上之覆蓋層及 覆蓋層中之開口上的間隙壁作為蝕刻罩幕來定義閘極複晶 梦時’可有效縮小兩相鄰閘極間之距離。因此，可擴展浮 置閉極區的面積。 3 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐) 經濟部智慧財產局員工消費合作社印製 554471 A7 ____ B7 五、發明説明（） 根據以上所述之目的，本發明更提供了一種縮減浮置 閘極間之距離的方法，至少包括：提供一基材，其中此基 材中至少包括複數個隔離結構，且這些隔離結構將此基材 分隔出複數個主動區；形成一閘極氧化層覆蓋在上述之基 材的主動區上；形成一複晶矽層覆蓋在上述之閘極氧化層 以及隔離結構上；形成一覆蓋層於上述之複晶矽層上，其 中此覆蓋層中至少包括複數個開口而暴露出部分之複晶矽 層；形成複數個間隙壁位於上述之開口的側壁以及所暴露 出之複晶矽層的一部分上，其中上述之覆蓋層與間隙壁涵 蓋住主動區以及部分之隔離結構；以上述之覆蓋層與間隙 壁作為蝕刻罩幕，去除所暴露出之複晶矽層的另一部分， 而暴露出每一個隔離結構的一部分；以及去除上述之間隙 壁與覆蓋層，而暴露出其餘之複晶矽層，且所剩下之複晶 矽層為閘極複晶矽層。 其中，上述之覆蓋層可完全涵蓋主動區，或可涵蓋在 部分之主動區以及部分之隔離結構上。藉由覆蓋層中之開 口側壁上的間隙壁，可使覆蓋層與間隙壁之所構成之結構 完全涵蓋住主動區以及隔離結構的一部分。因此，可以覆 蓋層與間隙壁為蝕刻罩幕，而使所形成之閘極複晶矽層往 隔離結構上擴展。 發明詳麯說明： 本發明揭露一種縮減兩相鄰浮製閘極間之距離的方 法，利用氮化矽所構成之覆蓋層與間隙壁，可將閘極複晶 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) .............0^.........、可.........Φ (請先閲讀背面之注意事項再填寫本頁) 554471 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（） 矽層擴展到隔離結構上，而達到縮減浮製閘極間之距離的 目的。為了使本發明之敘述更加詳盡與完備，可參照下列 描述並配合第1圖至第8圖之圖示。 請參照第1圖至第8圖，其係繪示本發明之一較佳實 施例之縮減浮製閘極間之距離的製造流程圖。首先，在例 如矽等半導體材料所組成之基材1 〇〇上以例如熱氧化之方 式形成薄薄的氧化層102，再以例如化學氣相沉積 (Chemical Vapor Deposition ·，CVD)的方式形成氮化層 ι〇4 覆蓋在氧化層102上。其中’氧化層1〇2又可稱為塾氧化 層（Pad Oxide)，可用以提升氮化層104對基材1〇〇的附著 能力。接著，利用例如微影與蝕刻製程進行定義，去除部 分之氮化層104、部分之氧化層102、以及部分之基材1〇〇, 而在氮化層104、氧化層1〇2、以及基材丨〇〇中形成多個溝 渠106，所形成之結構如第1圖所示。其中，溝渠1〇6之 區域為元件之隔離區，而溝渠1〇6之間尚為氧化層1〇2與 氮化層104所覆蓋的基材1〇〇區域則為元件之主動區。 請參照第2圖，溝渠1 〇6形成後，以例如熱氧化的方 式於溝渠106所暴露出之基材1〇〇的表面上形成氧化層 1〇8。再以例如高密度電蒙化學氣相沉積（High Denshy Plasma CVD ; HDP CVD)的方式沉積氧化矽層（僅繪示其中 之氧化層110)覆蓋在氣化層104、溝渠ι〇6所暴露出之氧 化層102、與氧化層108上，並填滿溝渠ι〇6。其中，氧化 層108又可稱為襯氧化層（Lining Oxide),可用以在高密产 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) .............0^.........、玎.........Φ (請先閲讀背面之注意事項再填寫本頁) 554471 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（） 電漿化學氣相沉積步驟中防止電漿傷害溝渠i 06所暴露出 之基材100。之後，以例如化學機械研磨（ChemicalV. Description of the invention () In addition, the currently used self-aligned floating gate process technology not only has a complicated manufacturing process, but also often creates a groove between the trench isolation structure and the semiconductor substrate. 'The polycrystalline dream material remains. Therefore, not only the electrical quality of the components is seriously affected, but also the process reliability and product yield are reduced. Object and summary of the invention: In view of the above background of the invention, due to the limitation of the lithography process, the distance between the floating gates cannot be effectively reduced, and the size of the cell cannot be reduced. Furthermore, the self-aligned floating gate process currently used is not only too complicated, but also has poor process reliability. Therefore, one of the main objects of the present invention is to provide a method for reducing the distance between floating gates, which uses a cap layer on a polysilicon layer and the openings in the cap layer. The spacer (Spacer) serves as an etch mask defining the gate polycrystalline silicon layer. Therefore, the distance between two adjacent gates can be effectively reduced. Another object of the present invention is that the distance between the floating gates can be reduced by using the cladding layer on the polycrystalline silicon layer and the gap wall on the opening of the cladding layer without being restricted by the lithography process, The self-alignment process is simple and easy to perform. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy Defining the gate complex crystal dream as an etch mask can effectively reduce the distance between two adjacent gates. Therefore, the area of the floating closed-pole region can be expanded. 3 This paper size applies to China National Standard (CNS) A4 specifications (210X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 554471 A7 ____ B7 V. Description of the invention () According to the above-mentioned purpose, the present invention provides A method for reducing the distance between floating gate electrodes includes at least: providing a substrate, wherein the substrate includes at least a plurality of isolation structures, and the isolation structures separate the substrate from a plurality of active regions; forming a The gate oxide layer covers the active area of the above substrate; a polycrystalline silicon layer is formed to cover the gate oxide layer and the isolation structure; and a cover layer is formed on the above polycrystalline silicon layer, wherein the covering The layer includes at least a plurality of openings to expose a portion of the polycrystalline silicon layer; forming a plurality of gap walls is located on the side wall of the opening and a portion of the exposed polycrystalline silicon layer, wherein the covering layer and the gap wall cover The active area and a part of the isolation structure; using the above-mentioned cover layer and the gap wall as an etching mask to remove another part of the exposed polycrystalline silicon layer, and Exposing a portion of each spacer structure; and removing the cover and the spacer layer, exposing the rest of the polycrystalline silicon layer, and the rest of the polycrystalline silicon layer is a polycrystalline silicon gate layer. Among them, the above-mentioned cover layer may completely cover the active area, or may cover part of the active area and part of the isolation structure. With the gap wall on the opening side wall in the covering layer, the structure formed by the covering layer and the gap wall can completely cover the active area and a part of the isolation structure. Therefore, the cover layer and the spacer wall can be an etching mask, and the formed gate polycrystalline silicon layer can be extended to the isolation structure. Detailed description of the invention: The present invention discloses a method for reducing the distance between two adjacent floating gates. By using a covering layer and a spacer formed by silicon nitride, the gate can be recrystallized. The paper size can be adapted to Chinese national standards ( CNS) A4 specification (210X297 mm) ............. 0 ^ ........., available ......... Φ (Please read the back first Note: Please fill in this page again.) 554471 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of Invention () The silicon layer is extended to the isolation structure to reduce the distance between floating gates. In order to make the description of the present invention more detailed and complete, reference may be made to the following descriptions in conjunction with the diagrams in FIGS. 1 to 8. Please refer to FIG. 1 to FIG. 8, which are manufacturing flowcharts illustrating a reduction in the distance between floating gates according to a preferred embodiment of the present invention. First, a thin oxide layer 102 is formed on a substrate 100 made of a semiconductor material such as silicon by thermal oxidation, and then nitrogen is formed by, for example, Chemical Vapor Deposition (CVD). The chemical layer ι04 is covered on the oxide layer 102. Among them, the 'oxide layer 102 can also be referred to as a pad oxide layer (Pad Oxide), which can be used to improve the adhesion of the nitride layer 104 to the substrate 100. Next, define it using, for example, lithography and etching processes, removing part of the nitride layer 104, part of the oxide layer 102, and part of the substrate 100, and the nitride layer 104, the oxide layer 102, and the substrate are removed. A plurality of trenches 106 are formed in the material, and the structure formed is shown in FIG. 1. Among them, the area of the trench 10 is the isolation area of the device, and the area of the substrate 100 covered by the oxide layer 102 and the nitride layer 104 between the trenches 10 is the active area of the device. Referring to FIG. 2, after the trench 10 is formed, an oxide layer 108 is formed on the surface of the substrate 100 exposed by the trench 106 by, for example, thermal oxidation. A silicon oxide layer (only the oxide layer 110 shown therein) is deposited by a method such as High Denshy Plasma CVD (HDP CVD) to cover the gasification layer 104 and the trenches and exposed. An oxide layer 102 and an oxide layer 108 are formed on the oxide layer 102, and the trenches are filled. Among them, the oxide layer 108 can also be referred to as a lining oxide layer (Lining Oxide), which can be used to apply the Chinese National Standard (CNS) A4 specification (210X297 mm) in the high-density paper size ... ..0 ^ ........., 玎 ......... Φ (Please read the precautions on the back before filling out this page) 554471 Printed by A7, Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs B7 V. Description of the invention () Plasma chemical vapor deposition step prevents the plasma from damaging the substrate 100 exposed by the trench i 06. After that, for example, chemical mechanical polishing
Mechanical Polishing ; CMP)的方式去除氮化層1〇4上之氧 化層’而在溝渠106中形成氧化層110。由於化學機械研 磨之製程因素的影響，而使得所生成之氧化層n〇暴露出 部分之溝渠106。 在溝渠1 06中形成氧化層1 1 〇後，以例如蝕刻的方式 去除氮化層104與氧化層102，而暴露出基材丨〇〇與部分 之氧化層108。其中，在去除氮化層1〇4與氧化層1〇2的 同時，也會移除部分之氧化層110，而在溝渠1〇6中形成 由氧化層108與氧化層110所構成之隔離結構112,所形 成之結構如第3圖所示。其中，根據製作方式，隔離結構 112 又可稱為淺溝渠隔離（Shall〇w Trench Is〇lati〇n; STI) 結構。 完成隔離結構1 1 2並定義出位於隔離結構丨丨2間元件 之主動區後，以例如熱氧化的方式於基材1〇〇之主動區上 形成氧化層114。其中，氧化層114又可稱為閘極氧化層。 接著，以例如化學氣相沉積的方式形成導電層，例如複晶 矽層1 1 6，覆蓋在氧化層丨丨4與隔離結構丨丨2上。再以例 如化學氣相沉積的方式形成覆蓋層1 1 8覆蓋在複晶矽層 116上’其中覆蓋層118之材料較佳為氛化碎。覆蓋層 形成後，以例如塗佈的方式形成一層光阻材料（僅繪示其中 之光阻層120)覆蓋在覆蓋層Π8上，再利用例如微影製程 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) --------------------π--------- (請先♦閲讀背面之注意事項再填寫本頁) 554471 A7Mechanical Polishing; CMP). The oxide layer 110 on the nitride layer 104 is removed to form an oxide layer 110 in the trench 106. Due to the influence of CMP process factors, the formed oxide layer n0 exposes part of the trenches 106. After the oxide layer 110 is formed in the trench 106, the nitride layer 104 and the oxide layer 102 are removed by, for example, etching, and the substrate 100 and a part of the oxide layer 108 are exposed. Among them, when the nitride layer 104 and the oxide layer 102 are removed, part of the oxide layer 110 is also removed, and an isolation structure composed of the oxide layer 108 and the oxide layer 110 is formed in the trench 106. 112. The structure formed is shown in Figure 3. Among them, according to the manufacturing method, the isolation structure 112 may also be referred to as a Shallow Trench Isolation (STI) structure. After the isolation structure 1 12 is completed and the active areas of the two components are defined, an oxide layer 114 is formed on the active area of the substrate 100 by, for example, thermal oxidation. Among them, the oxide layer 114 may also be called a gate oxide layer. Next, a conductive layer, such as a polycrystalline silicon layer 1 1 6, is formed by, for example, chemical vapor deposition, covering the oxide layer 丨 4 and the isolation structure 丨 2. Then, a cover layer 1 1 8 is formed on the polycrystalline silicon layer 116 by, for example, chemical vapor deposition. The material of the cover layer 118 is preferably fragile. After the cover layer is formed, a layer of photoresist material (only the photoresist layer 120 shown therein) is formed by coating, for example, and covered on the cover layer Π8, and then used, for example, in the lithography process. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297mm) -------------------- π --------- (Please read the precautions on the back before filling in this page ) 554471 A7
五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 去除部分之光阻材料，而暴露出部分之覆蓋層118，藉以 在覆蓋層118上形成具有主動區圖案之光阻層12〇。當微 影製程相當準確時，光阻層12〇位於隔離結構ιΐ2之間的 主動區正上方，而使得光阻層12〇完全涵蓋住主動區。然 而，在本發明之一較佳實施例中，亦可容許微影製程產生 些許誤差，也就是說，光阻層120可不完全涵蓋住位於隔 離釔構1 1 2之間的主動區，而可位於部分之隔離結構1 ^ 2 以及部分之主動區上，如第4圖所示。 接著，利用例如蝕刻的方式，並以光阻層12〇為蝕刻 罩幕，去除部分之覆蓋層118,而在覆蓋層118中形成多 個開口 1 22，並暴露出部分之複晶矽層u 6。由於，蝕刻覆 蓋層11 8係以光阻層120為蝕刻罩幕，因此所留下之覆蓋 層1 1 8位於部分之隔離結構丨丨2與部分之主動區上。覆蓋 層118之蚀刻步驟完成後，去除剩餘之光阻層而暴 露出覆蓋層1 1 8之表面。再以例如化學氣相沉積的方式形 成介電層124覆蓋在覆蓋層118與複晶矽層116所暴露出 的部分上’並填滿開口 1 22，而形成如第5圖所示之結構。 其中，介電層124之材料較佳為氮化矽。 經濟部智慧財產局員工消費合作社印製 元成介電層1 2 4之沉積後’利用例如回姓刻的方式， 去除部分之介電層124,而暴露出覆蓋層118之表面以及 複晶碎層116的一部分，藉以在開口 122之覆蓋層118的 側壁上形成間隙壁12 6，而形成如第6圖所示之結構。藉 由覆蓋層1 1 8與其側壁上的間隙壁丨26所組成之結構，不 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐) 7 44 5 5 五 經濟部智慧財產局員工消費合作社印製 A7 B7 發明説明（ 僅可完全涵蓋住隔離結構112之間的主動區，更如同先前 所述亦涵蓋住部分之隔離結構丨丨2。 於開口 122之側壁上形成間隙壁126後，以例如蝕刻 的方式，並利用覆蓋層丨丨8與其侧壁上之間隙壁丨26的組 合結構作為蝕刻罩幕，去除所暴露出之複晶矽層丨丨6，而 使開口 122的深度變大而暴露出部分之隔離結構ιΐ2，所 形成之結構如第7圖所示。其中，經蝕刻後所留下之複晶 矽層116又可稱為閘極複晶矽層，屬浮置閘極區域。 去除部分之複晶矽層11 6後，以例如蝕刻的方式去除 覆蓋層118與間隙壁126,而暴露出複晶矽層116之表面， 所形成之結構如第8圖所示。由於，覆蓋層丨丨8及間隙壁 1 26之組合結構的範圍涵蓋了全部之主動區與部分之隔離 結構112’因此所餘之複晶矽層Π6不僅完全覆蓋住隔離 結構11 2之間的主動區，也擴展到隔離結構丨丨2上。如此 一來’不僅可將複晶矽層1 1 6所在之浮置閘極區域的尺寸 予以擴大，更可輕易地將兩相鄰之浮置閘極之間的距離縮 小。因此，可達到縮小記憶晶胞，例如分離式閘極快閃記 憶晶胞之尺寸的目的。 綜合以上之較佳實施例的說明，本發明之一優點就是 在提供一種縮減浮置閘極間之距離的方法，利用覆蓋層及 其側壁上之間隙壁所組成之結構作為定義閘極複晶矽層的 蝕刻罩幕。因此，可相當輕易地將浮置閘極區的尺寸擴展 到隔離區上。 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 、可 (請先★閲讀背面之注意事項再填寫本頁) 554471 A7 B7 五、發明説明（ 本發明之另一優點就是因為以覆蓋層與間隙壁之組合 結構作為蝕刻罩幕可將浮置閘極區擴展到隔離區上，進而 可有效縮小兩相鄰閘極間之距離。因此，記憶晶胞之尺寸 可獲得縮減。 本發明之再一優點就是因為本發明係利用覆蓋層與間 隙壁之組合結構，即可達到縮小浮置閘極間之距離的功 效。因此，並不受限於微影製程，亦較自我對準製程簡單 而易於實施，應用性極佳。 如熟悉此技術之人員所瞭解的，以上所述僅為本發明 之較佳實施例而已，並非用以限定本發明之申請專利範 圍；凡其它未脫離本發明所揭示之精神下所完成之等效改 變或修飾，均應包含在下述之申請專利範圍内。 圈式簡單說明： 本發明的較佳實施例已於前述之說明文字中輔以下列 圖形做更詳細的闡述，其中： 第1圖至第8圖係繪示本發明之一較佳實施例之縮減 浮製閘極間之距離的製造流程圖。 圈猇對照說明： 、一叮 ^9 秦 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 100 基材 102 氧化層 104 氮化層 106 溝渠 108 氧化層 110 氧化層 112 隔離結構 114 氧化層 116 複晶矽層 118 覆蓋層 本紙張尺度適用中國國家標準(cNS)A4規格(210x297公釐) 554471 A7 B7 五、發明説明（） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 10 120 光阻層 122 開口 124 介電層 126 間隙壁 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐)V. Description of the invention () (Please read the precautions on the back before filling this page) Remove part of the photoresist material and expose part of the cover layer 118, so as to form a photoresist layer with an active area pattern on the cover layer 118 12〇. When the lithography process is quite accurate, the photoresist layer 120 is located directly above the active area between the isolation structures ιΐ2, so that the photoresist layer 120 completely covers the active area. However, in a preferred embodiment of the present invention, a slight error may be allowed in the lithography process, that is, the photoresist layer 120 may not completely cover the active region between the isolated yttrium structures 1 12, but may It is located on part of the isolation structure 1 ^ 2 and part of the active area, as shown in Figure 4. Next, by using, for example, etching and using the photoresist layer 120 as an etching mask, a part of the cover layer 118 is removed, and a plurality of openings 12 are formed in the cover layer 118, and a part of the polycrystalline silicon layer u is exposed. 6. Since the etching cover layer 118 uses the photoresist layer 120 as an etching mask, the remaining cover layer 1 1 8 is located on part of the isolation structure 2 and part of the active area. After the etching step of the cover layer 118 is completed, the remaining photoresist layer is removed and the surface of the cover layer 118 is exposed. Then, a dielectric layer 124 is formed, for example, by chemical vapor deposition to cover the exposed portions of the cover layer 118 and the polycrystalline silicon layer 116 'and fill the openings 1 22 to form a structure as shown in FIG. Among them, the material of the dielectric layer 124 is preferably silicon nitride. After the deposition of the Yuancheng dielectric layer 1 2 4 by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the part of the dielectric layer 124 is removed by using, for example, the method of engraving the surname, and the surface of the cover layer 118 and the polycrystalline chip are exposed A part of the layer 116 forms a gap wall 12 6 on the side wall of the cover layer 118 of the opening 122 to form a structure as shown in FIG. 6. With the structure composed of the cover layer 1 1 8 and the partition wall 26 on the side wall, the size of this paper is not applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) 7 44 5 5 Consumer Cooperative printed A7 B7 invention description (can only completely cover the active area between the isolation structures 112, more like the previous description, and also covers part of the isolation structure 丨 2). After forming the partition wall 126 on the side wall of the opening 122 In the manner of, for example, etching, and using the combined structure of the cover layer 8 and the spacer wall 26 on the side wall as an etching mask, the exposed polycrystalline silicon layer 6 is removed to make the depth of the opening 122 The large isolation structure is exposed, and the structure is shown in Figure 7. Among them, the polycrystalline silicon layer 116 left after etching can also be called the gate polycrystalline silicon layer, which is floating. Gate region After removing a part of the polycrystalline silicon layer 116, the cover layer 118 and the spacer 126 are removed by, for example, etching to expose the surface of the polycrystalline silicon layer 116. The structure formed is shown in FIG. 8 .Because of the cover layer 丨 丨 8 and the partition wall The range of the combination structure of 1 26 covers all the active areas and part of the isolation structure 112 '. Therefore, the remaining polycrystalline silicon layer Π6 not only completely covers the active area between the isolation structures 11 2 but also extends to the isolation structure. 2. On top of this, not only can the size of the floating gate region where the polycrystalline silicon layer 1 16 is located be increased, but also the distance between two adjacent floating gates can be easily reduced. Therefore, It can achieve the purpose of reducing the size of a memory cell, such as a separate gate flash memory cell. Based on the above description of the preferred embodiment, one advantage of the present invention is to provide a method for reducing the distance between floating gates. Method, the structure composed of the cover layer and the spacer on the side wall is used as an etching mask to define the gate polycrystalline silicon layer. Therefore, the size of the floating gate region can be easily extended to the isolation region. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm). Yes (please read the notes on the back before filling out this page) 554471 A7 B7 V. Description of the invention (Another advantage of the invention is that The combined structure of the cap layer and the gap wall can be used as an etching mask to extend the floating gate region to the isolation region, thereby effectively reducing the distance between two adjacent gates. Therefore, the size of the memory cell can be reduced. Another advantage of the invention is that the invention can achieve the effect of reducing the distance between the floating gate electrodes by using the combined structure of the cover layer and the partition wall. Therefore, it is not limited to the lithography process and is more self-aligned. The manufacturing process is simple and easy to implement, and has excellent applicability. As will be understood by those familiar with this technology, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention; Equivalent changes or modifications made under the spirit disclosed in the present invention should all be included in the scope of patent application described below. Brief description of the circle: The preferred embodiment of the present invention has been described in more detail in the preceding explanatory text with the following figures, wherein: Figures 1 to 8 are drawings showing a preferred embodiment of the present invention Manufacturing flow chart for reducing the distance between floating gates. Circle control comparison instructions: Yiding ^ 9 Qin (please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 100 Substrate 102 Oxidation layer 104 Nitride layer 106 Trench 108 Oxidation layer 110 Oxidation layer 112 Isolation structure 114 Oxidation layer 116 Polycrystalline silicon layer 118 Cover layer The paper size is applicable to China National Standard (cNS) A4 (210x297 mm) 554471 A7 B7 V. Description of the invention () (Please read the precautions on the back first (Fill in this page again) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 10 120 Photoresist layer 122 Opening 124 Dielectric layer 126 Spacer This paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm)