TW522370B - Multi-format active matrix displays - Google Patents

Abstract

Multi-format sampling registers, digital to analogue converters, data drivers and active matrix displays are provided which provide power saving in lower resolution formats by disabling circuitry which is not required in those formats.

Description

522370

BACKGROUND OF THE INVENTION 1. Field of the Invention and the Multiples It Uses The present invention relates to a multi-format active matrix display format device. 2. Description of related technology The present invention provides a multi-format data driver for controlling active matrix display. The driver circuit can be completed by using a discrete driver integrated circuit, and connected to the money matrix by direct bonding or by a flexible circuit connection method. In this courtesy; most of the way I am made of Jingzhen. Alternatively, the circuits are integrated on the same substrate using the same processing steps to form an active matrix device. This type of device includes thin-film transistors (TFTs), especially low- and high-temperature complex crystal power-generating crystals. The present invention directly meets the requirements of the portable display device. The display data supply can be for various different formats and the display rate consumption must be reduced. Figure 1 Buccal TIT 'quasi-active matrix liquid crystal (LC) display composition. The squares around the active matrix represent display driver electronics. Combining the functions of the digital data line driver 4 and the scanning line driver 6 provides analog data voltage to the pixel electrode 8 of the digital image data source. The digital drive mode 4 generally receives image data (not shown) from an integrated circuit of a controller. In addition to the image data, the driver 4 also receives control and timing signals such as -clock signal, and the synchronization of the silk riding is reduced. The image data is normally transmitted to the digital data driver 4 one line at a time, and each line corresponds to the display state required by one horizontal pixel line of the display. The digital data driver 4 includes an input register 10 array, as shown in FIG. 1. Because an image data scale is suitable for financial and domestic use (CNS) M specification (⑽x 297 public love) 4: --- 522370 A7 B7 V. Description of the invention (The line is transmitted to drive 4, each data element is read and stored Enter an input register 1 G. The sampling signal for starting the input register 丨 〇 is generated by the timing generator 12. Once the entire line of image data has been sampled by the input register 1 〇, the data is transferred to a storage Array of registers 16. When the next line of image data is transmitted to drive 4, the data stored in storage register 16 is supplied to the digital pair-like converter circuit 18. The digital pair-like conversion operation is non-linear The liquid crystal voltage / light transmission characteristics are compensated. This conversion is called r-correction. Alternatively, the lc controller (not shown) supports 7-correction. In this way, the digital pairs within the digital data driver 4 are converted to linear operation. Conversion The output of the charger 18 charges the source line 20 (such as the data line) of the active matrix, and the scanning driver 6 controls the pixels of that row to be charged from the source line 20 via the pixel TFTs 22. Figure 2 shows the light transmission of standard winding LCD pixels. To electrode voltage Curve. The correction of the LCD active matrix display includes the compensation of the pixel non-linear input voltage / light adjustment characteristics. In order to cancel the non-linearity and cause the digital input with the same change to correspond to the light transmission with the same change, a conversion circuit must accurately complete the figure The inverse function of the function. This inverse function is indicated by a dashed line in the graph of Figure 3. The digital input is along the X axis (6 bits in this example), and the y axis represents the analog voltage required by the digital pair for this conversion operation output. There are two main strategies for completing T correction. First, as shown in Figure 4 (a), including a pure digital conversion. A RAM or ROM circuit 24 receives a digital input with (n + m) bits and generates an output. The output has more bits than the input to maintain accuracy. These bits reflect the ideal inverse function such that when these bits are supplied to a connected linear digital to analog converter 26, the analog output is -5- this paper The scale is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 522370 A7 ___ _B7 V. Description of the invention (3) Has ideal input response. The first strategy includes 7 correction and a non-linear 2 segment digital To analog converter 28, as shown in Figure 4 (b). This τ correction device will be discussed in more detail below. In Figure 4 (b), the digital to analog converter (DAC) 2 8 consists of 2 segments. The first-stage DAC30 receives the most significant bits (MSBs) of the fixed input, and a second DAC 32 receives !! the least significant bits (LSBs). Corresponding to the reference voltage VR for each digital input from 0 to 2 Ώ To the first section of DAC30. In Figure 4 (b) these reference voltages are represented by VR (0: 2m). ^^ Out in the first section is decoded by m-bit to 2 m-line decoder and its result is used to select two The 2m + lr correction reference voltage, vR (0: 2 m), supplied to the second DAC 32 of the converter 28. The two reference voltages VR supplied to the second DAC 32 are the VL and VH voltages shown in Fig. 4 (b). Within the second DAC32, the nLSB is used to perform a one-line digital-to-analog conversion within the range defined by VL & VH. The second digital-to-analog converter 32 standard consists of a capacitor or resistor, and a switch. Because the video capacitor or source line load is usually high, a buffer circuit 34 is usually used for the circuit output. The conversion rate and settling time of the buffer define the minimum conversion time required to obtain an ideal bit accuracy. The conversion rate is the maximum rate of change of the output voltage of a buffer, and has V / s units. In the graph of Fig. 3, an example in which a 6-bit conversion is supplied by a converter circuit is shown. In this particular example, n = 3 and ㈤ ^: 3. The solid line shows a piece-by-piece straight line approximation (dotted line) where the actual output is the ideal output. Use r to correct the reference voltage to define the end point of the linear element. -6- f522370 A7 B7

Figure 5 shows a known improved 2-segment non-linear digital-to-analog converter 3 6 ′ using a smaller conversion time operation (see British Patent Application No. 0011 (^ 5.5). Compare Figure 4 (h this modified circuit contains 2 This switch is used to operate the non-repetitive clock phase, φ, and φ 2 (shown in Figure 6). The first switch 38 is called a pre-charge switch and allows the selected reference voltage. VL to directly charge the output load 40 in phase. The second switch 42 is called an isolating switch, which is turned on during the period of φ to cause the buffer output to isolate the load 40. Because VL is a reference power source, the load is charged quickly to its final ideal value of η. Definition of charge switch resistance and load capacitance. In ①2, the precharge switch 38 is turned on, and the buffer 34 applies the (m + n) bit analog result of the digital to analog converter 36 to the load 40. At this time, the load has been Charge to within 11 bits of its final ideal value, so the buffer output can reach this goal very quickly. A comparison of the transition time between this circuit and a circuit in Figure 4 (b) is shown in Figure 6, The top and bottom curves are shown separately The voltage output of the 4 (b) and 5 circuits. The design of the sampling circuit in the input register 10 and the storage register 16 of FIG. 1 can be appropriately changed according to the integration processing technology. This is because the source voltage of the sampling circuit As a processing method is variable, it is ideal. The digital input and control signals for power consumption should be low voltage logic. For example, a logic low is Ό · 〇V and a logic high is between 1.0 V and 5.0 V. In the case of crystalline silicon integrated circuit drivers, because the power supply voltage is the same as the logic input level, the design of the sampling circuit is simpler, such as using standard D-type latches or flip-flops. As for the polycrystalline silicon (or other) integrated circuit driver The condition of the higher device threshold voltage guarantees that a power supply is often more effective than a logical input. This paper size is applicable to China National Standard (CNS) A4 specifications (210x 297 mm)

Install tf 4 k 22370 A7 B7 V. Description of the invention (5) Enter the level, for example, vdd is any value between 5.0V and 15.0V. The voltage inconsistency between the input and the power supply indicates that the voltage level in the sampling circuit needs to be shifted. FIG. 7 shows that a prior art sampling circuit 42 (see British Patent Application No. 0005985.7) is suitable for sampling an input logic signal (symbol INPUT in the diagram) which is effectively lower than the power supply voltage vdd. If the SAMPLE control signal is high (vdd), the output (symbol OUTPUT) is an equal logic offset level of the input signal. If the SAMPLE control signal is low (vss), the output is locked. The circuit is divided into two sub-circuits; a level shift sub-circuit is composed of devices M 3 to M 7 and a latch sub-circuit is composed of M 8 to M 1 3. When SAMPLE is high, the level shift sub-circuit is activated. P-type devices M4 and M6 are opened and N-type device M3 is closed. Transistors M4 and M5 are connected in series between vdd and a reference voltage vref (may be vss), and together generate a bias voltage to the gate of transistor M7. The structure of the device M7 is a common-gate amplifier in which a source terminal is an input and a drain terminal thereof is connected to a load device M6 as an output. Be careful with the device classification and selection of vref. The output is an equal amount of logic offset to the input, which is almost swinging around the power rail. When SAMPLE is low, the latch circuit is activated (devices M 8 and M 1 1 are turned on), and the logic states of the outputs are stored by the cross-coupled converters M9 / M10 and M12 / M13. In operation, the circuit starts and controls the output sticky state only once, and the other circuits stop. When the offset level circuit is activated, that is, SAMPLE is high, it must be noted that the power consumption of the circuit is the highest. This is due to the current flowing between vdcl · and vref (M 4 to M 5) and vdd and INPUT (via M 6 and M 7). The screen display function is generally used to cover simple text or graphic data. _____ This paper size applies to China National Standard (CNS) Α4 specification (210 X 297 mm).

r22370 V. Video description of the invention (such as the display brightness setting of a digital camera. When selected, you can see the overlap on the camera image provided by the CCD. This functionality is generally provided by an LC control integrated circuit, such as the picture The general type shown in Figure 8. This chip can input video data into bright or color format or RGB format, and supply analog or digital tau correction RGB to Lc data driven by an active matrix display. Data displayed on any screen is driven by SRAM memory 44 is provided for overwriting the video data shown in the display mixer circuit 46. The present invention allows this function to be moved to the LC data driver circuit. SUMMARY OF THE INVENTION A multi-format sampling register is provided according to the present invention. Digital-to-analog converters, data drivers and active matrix displays are described in the scope of patent applications. The L-type signal is used to ensure that only the components required by the known format are activated, thus reducing power consumption. The diagram is simply explained now The specific embodiments of the present invention are described in detail by way of examples and with reference to the following drawings, in which: FIG. 1 shows a first Traditional digital data driver and active matrix display technology; Figure 2 shows the voltage transmission curve of a standard LCD pixel; Figure 3 shows a piece-by-piece straight line approximation to the inverse voltage transfer curve of Figure 2, which can use the previous technology's 2-segment digital-to-analog conversion Figure 4 (a) shows a prior art 7 correction circuit containing a digital input conversion and a straight n + m-bit digital to analog converter; the binding of this paper size is applicable in the S family fresh (CNS) A4 specification ( 2l〇x 297 public love) -9- 522370

V. Description of the invention (7) A7 B7

Figure 4 (b) shows a prior art τ correction circuit containing a non-linear two-segment n + m-bit digital to analog converter; Figure 5 shows a prior art non-linear two-segment n + m-bit digital-to-analog converter having Improved conversion speed; Figure 6 shows a comparison of the conversion time required by the digital-to-analog converters of Figures 4 (b) and 5; Figure 7 shows the prior art beer bit low voltage sampling circuit; Figure 8 shows a prior art standard LC controller The integrated circuit includes: the capability is displayed on the screen; FIG. 9 shows a specific embodiment of the present invention, which is a multi-format digital data driver and controls the signal operation according to the format; FIG. Capacity, indicating the balance between display quality and power consumption; Figure 11 (a) An example of the display format control signal and the corresponding multi-format driver operating mode; Figure 1 1 (b) Display the format control signal and the corresponding multi-format driver operating mode Another example is shown in Figure 12. Figure 12 shows how the power consumption of the sampling circuit is controlled by the format control signal. Figure 1 3 shows the bias current of the sampling circuit in Figure 7. How the rate consumption can be controlled by the two format control signals; Figure 14 shows the prior art digital-to-analog converter shown in Figure 5 such as synthesizing and multi-format digital data driver operation; and Fig. 15 shows the time when the digital -10- Switch in analog converter This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm)

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Line phase. DESCRIPTION OF THE PREFERRED EMBODIMENT Fig. 9 7F A simplified block diagram of a specific embodiment of the present invention. In this example, the display is not monochrome, and the color expands to portrait. The multi-format digital data driver 50 is composed of 4 king components: a certain time generator 52, an input register array 54, a storage register array 56, and a digital-to-analog converter array. The digital soil ratio conversion state is a two-segment type, as described above, and the msb and LSB conversion service arrays 58 and 60 are derived from Figure 9, respectively. The multi-format driver 50 uses a standard clock and control signal, and two images' men's input, a gray scale input, and a 2-bit input. Gray scale input, represented by D (1: n + m) because it is composed of 1 to (11 + 111) (eg, 1 to 6 bits) bits, which is a parallel input of n + m bits width, where m corresponds to the maximum number of valid data bits of the gray scale and η corresponds to the minimum number of valid data bits of the gray scale. This input supplies grayscale pixel image data with one of two resolutions: all n + m bits are read by driver 50 at high resolutions, and only m MSBs are read by driver 50 at low resolutions. D means binary input. It is a 1-bit input that supplies independent black / white pixel image data. The 2-segment feature of the digital-to-analog converter allows for non-linear conversions and accommodates many multi-format drivers with 50 to 7 correction functions. The required reference voltage is supplied externally as shown in Figure 9, although, in fact, it can be generated inside the driver 50 itself. The operation mode of the multi-format driver 50, i.e., the drive format, is controlled by the format control signal and is also shown in the diagram. As shown in this example, three format control signals are provided, SB, MB, & NB. These signals are based on 522370

The 5 G components of the heavy-duty driver need to be allocated to enable a special driver format with the lowest power consumption. The drive format is explained in the next paragraph. Even the heavy drive mode 50 can be operated in various display formats. The choice of drive format is based on any one of many system factors. For example, what kind of image data can be displayed or has been selected—the system function requires graphic data to be displayed superimposed on the video image? Or, even, what is the status of the power supply that supplies the system power? _ The most important factor of the Terabetsu system, setting the state of the format control signal results in the best display effect. Figure 10 shows five different display formats supported by the multi-format driver 50: (1) 1 bit per π color: The driver 50 reads the image data from the unit D input stream, and writes one of the two reference levels to the source line of the indicator 2. Therefore, the pixel can be set to one of two states, generally black and white. The reference level generally changes the polarity on a frame-by-frame basis so that the liquid crystal material in each pixel unit is out of date DC balance. (η) m bits per color: the driver 50 only reads the image data from m MSBs of the d (1: n + m) input stream, and writes the analog data to the display 2 after an m-bit digital-to-analog conversion process Source line. The pixels can then be set to one of the 2 m gray levels. (iii) Each color m bit contains 1 bit coverage. The driver 50 reads the image data from the m MSBs of the 0 (1: n + m) input stream and the unit cell D input stream. After the m-bit digital-to-analog conversion process, the driver writes the analog data into the source line of the display 2 and overwrites the input data with d if necessary. The pixels can then be set to one of the 2mK levels. _22 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 522370 A7 B7 Five invention instructions ((1 V) n + m bits per color: driver 5 0 from D (1 · · Π + m) The input stream 'takes image data. After an n + m-bit digital-to-analog conversion process, the driver 50 knows the source line of the display 2 into the display 2. If necessary, it is overwritten with 0 input data. Can be set to one of 2n + m gray levels. (V) Each color n + m bit contains 1 bit coverage: driver 50 reads from D (1: n + m) input stream and unit cell 0 input stream Take the image data. After the ^ + m-bit digital-to-analog conversion process, the driver 50 writes the data to the source line of the display 2 'If necessary, overwrite the input data with D. The pixels can be set to 2 n + m grayscale One of the levels. The above display formats are listed in order of increasing display performance. The final format displays a second 1-bit image covering an n + m-bit resolution image. The multi-format driver 50 ensures the power of lower-performance display formats. Consumption is really low. This is achieved by a format control signal which selectively stops the drive circuit without The main components are explained in the specific embodiment explaining the principle as follows. Figure 1 1 (a) The table shows how to use the three format control signals SB, MB, NB to select the above five possible drive format modes. Each format control signal Responsible for starting the special circuit in the multi-format driver 50. S b starts the circuit related to the single input data stream, D, which is used in the 1-bit display mode and the application overlay function. MB starts the related gray scale input. The most significant bit is represented by D (n + 1: n + m), and a circuit consisting of (η + ι) to (n + m) (such as 4 to 6 bits). NB MB starts the connection gray The circuit of the least significant bit of the scale input, represented by D (1: n) (such as i to 3 bits). In addition to the input signal combinations shown in the table, if all the format control signals are 0, the multi-format driver Must be closed. ___- 13 -___ This paper size is suitable for SS transfer (CNS) A4 size (210 X 297 public love) " 522370 Α7

V. Description of the invention (π Β7 Figure 1 1 (b) The table shows the format control signals of another group, MN and s. The two signals have the advantage of fewer driver signals, but it can be expected that only 22 == 4 display formats can Encoding. However, the d input bit itself is used to determine whether to enable the overlay mode. If S = 1 (and MN = 0), select 1 bit per color mode and the display is overwritten with data supplied by the D input stream. In the other 4 In this case, S = 0, and MN decides whether to display the input of high or low resolution data from D (1: n + m): MN = 0 selects low resolution (m-bit grayscale); MN = 1 selects high resolution Degrees (n + m-bit grayscale). In these modes, any positive data from the D input will overwrite the grayscale data. If you do n’t need to cover it, the input must be kept low. Format control signal control. The same circuit can be controlled by 2 format control signals with additional control logic. Figure 12 shows an example of a circuit of a single input register 61 in the input register array 54. The register is worthy of sampling From gray scale input, D (1: n + m) 'and 2-bit input D digital data. There is a unit cell sampling circuit of the type shown in FIG. 7 within the unit cell sampling box 6 2. There are m unit cell sampling circuits within the MSB sampling box 64. Each is the type shown in Figure 7. There are n unit cell sampling circuits within the LSB sampling block 66, each of which is the type shown in Figure 7. Therefore, the power supply and the power consumption of each sampling block are controlled by corresponding format control signals. SB, MB and NB format control signal control switches 6 8, 70 and 72. These switches supply power to unit cells, MSB and LSB sampling blocks respectively. Therefore, sampling blocks 6 2, 6 4, 6 6 are only required Power is consumed only when one of the display formats is supported. Active matrix display-14- This paper size applies to China National Standard (CNS) A4 (210X 297 mm) 522370 A7 B7 V. Each column of the description of the invention (12) requires one each Figure 12 shows the type of input register, or requires less input than the number of columns to be prepared. 'If the input registers between columns are multiplexed (eg, shared overtime). Figure 1 3 shows the unit of Figure 7. Meta-sampling circuit controls power consumption A simple method. The format control machine number is logical AND with the SAMPLE * signal, so that the unit cell sampling circuit only receives one SAMPLE pulse, if the format control signal is direction. As mentioned above, In order to achieve low voltage sampling, this special circuit is M4 / The M5 and M6 / M7 transistors consume effective power. If the g ample input is high. Therefore, the format control signal prevents unnecessary bits from dissipating power in the ^ unit cell sampling circuit. Digital to analog converters 7 8 series are used in Figure 1 4 shows the multi-format drive 50. This circuit is a modification of the prior art circuit of FIG. For example, the converter can support gamma correction, as mentioned above, with an appropriate VR reference voltage. To support the above five display formats, the capacitive load 40 (for a video line or a source line) can be changed to a 3-degree resolution: n + m bits, ^ bits, or 1 bit. This is discussed in detail below. In the South Resolution (n + m bit) mode, the n B and MB format control signals are activated. Assume that S B is low (no coverage). This signal ensures that the MSB decoder circuit 80, the LSB digital-to-analog converter 82, and the buffer circuit 84 are activated. Because of the bias current within the buffer circuit 84, the circuit is in a state of maximum power consumption. Two non-overlapping time periods φ 1 and φ 2 are used, as shown in Figure 15. At Φ 1 'in response to the MSBs, the MSB decoder circuit selects Vl and VH voltages and supplies the LSB digits to the analog converter 8 2. The pre-charging switch 86 also ensures that the load 40 is charged to VL ′ relatively quickly, that is, within the ideal target voltage ^ bit. In paper size application® National Standard (CNS) Α4 size (21G X 297 mm) " '— 522370 A7 B7

V. Description of the invention (13 Φ2, the LSB digital-to-analog converter 82 performs the least significant bit conversion (between vL and VH) and the buffer circuit 8 4 The voltage supplied by the conversion is passed through the isolation switch 8 8 to the load 40. The load 40 thus Can charge 2n + m one of different voltage levels.

Installed in low-resolution mode (m-bit), the μ B and NB format control signals are high and low, respectively. Assume that S B is low (no coverage). As a result, the MSB decoder circuit 80 is started, but the LSB digital-to-analog converter § 2 and the buffer circuit 84 are stopped. Because the buffer circuit 84 is biased, the circuit consumes less power in this configuration. During the conversion, the isolation switch 88 permanently separates the buffer output from the load 40. On the other hand, the precharge switch 86 selects the reference voltage VL from the MSB decoder circuit 80 to charge the load 40. In this way, the load 40 can be changed to one of the two voltage levels. The off-period of the precharge switch can be extended during the conversion cycle to ensure that the load 40 is fully charged up to the VL reference value VL. This is because no Φ2 (buffer operation) cycle is required. Figure 15 shows the longer Φ 1 # signal to activate the precharge switch in this particular mode. k In 1-bit resolution mode, the MB and NB format control signals are both low and the SB signal is high. Only the MSB decoder circuit 80 is activated, and the converter 7 8 consumes very little power. The operation of the MSB decoder circuit 80 is changed to accommodate 2-bit operations. Ignore the MSB input and supply the output to VL according to the state of D. For example, if D is high, supply the lowest reference voltage from the ruler to the output Vi and thus to the load 40. This ensures that a pixel driven by the load 40 switches to white (or becomes fully transparent, assuming the pixel has an L c response to the curve in Figure 2). Conversely, if D is low, the highest VR reference voltage is supplied to the output VL and thus to the load 40 °. This ensures that a pixel driven by the load 40 is switched to black (or completely opaque). Because the load 40 is only charged by the precharge switch 86,

522370 A7 B7 V. Description of the invention (14 Using the above φ 1 * signal, the switch 86 can be turned off for a longer time. The coverage mode is used for the above (n + m) bit and m bit mode. If the sb format control signal is high If this is the case and D is low, the converter circuit Η operates exactly as described above for the (n + m) bit and time mode, ie if the SB signal is low. When D is high, but '_ decoder The operation of the circuit ㈣ has been modified. The minimum MR reference voltage is supplied to the output VL, and thus via the pre-charge switch 86 to the load 40. Regardless of the gray scale image data, D (i: n + m), this ensures that the load is 40%. The charged pixels are switched to white (or become completely transparent). White (or full color RBG) coverage can reach 0 on top of the grayscale image for n + m bit operations. When D is high, buffer path 84 is No. Therefore, the circuit 78 can add logic to prevent the load 40 from being connected and / or completely stop the buffer 84. It is conceivable that the specific embodiment described above provides a digital data driver structure for an active matrix display where the driver circuit Operating mode (and The power consumption of the actuator and the driver) is controlled by the additional format control signal that is simply supplied to the driver. The different modes are monochrome, color (bit plane) with each resolution value, and 1 bit for any other mode Cover function. The format control signal can be used to adjust the operating mode of the driver to optimize the image quality and power consumption of the display. This is particularly related to the level shift circuit of the complex chip driver, the bias generating circuit, and the buffer. The tail current of the device can be stopped to save power. In addition, the document data overlay image data does not require any data processing in the display controller. It can be thought of 'though the specific embodiment described divides the (n + m) bits into two − 17- This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm)

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Line 522370 A7 B7 V. Description of the invention (15) to provide two different resolutions. Another specific embodiment may divide the input into 3 or more to provide 3 or more resolutions. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -18-

Claims (1)

522370 Scope of patent application: A multi-format sampling register for driving a data line of an active matrix display. The sampling register is configured to operate in high or low resolution mode and includes: (a) a sampler input device Configured to receive a digital input containing at least (n + m) bits and a switching level representing one pixel of the display, where n and m are integers; (b) — the first sampler includes m sampling circuits, each configured to sample One of the m bits of the digital input; (c) a second sampler includes a sampling circuit, each configured to sample one of the n bits of the digital input, wherein the m bit is more effective than the n bit; And (d) —the second sampler switch is configured to switch on in the high-resolution mode and switch off the second sampler in the low-high-resolution mode to ensure that when the sampling register is in the low-resolution The second sampler consumes little or at least less power when operating in degree mode. 2. If the multi-format sampling register in item i of the patent application scope, wherein the second sampler switch is controlled in response to a separate n-bit format control signal, when the n-bit input of the digital input is required, that is, Activate the control signal. 3. The multi-format sampling register according to item 1 of the patent application scope, further comprising: a unit cell sampling circuit configured to sample a unit cell input; and a unit cell switch configured to switch the unit cell sampling circuit on or off . -19- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 522370 4. If the multi-format sampling register in item 3 of the patent application scope, the temporary storage = can operate in the coverage mode where the coverage I machine represented by the unit input is displayed in a single color on the display, and the unit The switch is configured to switch the unit cell sampling circuit to be turned on in the overlay mode and closed at other times to ensure that the unit cell sampling circuit consumes little or at least less power when the sampling register is not operating in the overlay mode. 5. If the multi-format sampling register of item 4 of the patent application scope, which controls the unit cell switch in response to a separate unit cell format control signal, when the unit cell is needed, the control signal is activated. 6 · If the multi-format sampling register in item 3 of the patent application scope, the register can be in a unit display mode. The pixels of all displays are set to two different switching levels by the unit. The input representative, and further comprising a first sampler switch configured to switch the first sampler off in the unit cell display mode, and wherein the second sampler switch is also configured to switch the second sampler to the unit cell display It is turned off in the mode to ensure that the first and second sampler circuits consume little or at least less power in the unit cell display mode. 7. If the old sample sampling register of the 6th in the scope of patent application, the first sampler switch is controlled to respond to a separate unit element format control signal 'when the m unit element of the digital input is needed, The control signal is activated. 8 · —A multi-format digital-to-analog converter is a data driver for driving the data line of an active matrix display, the digital-to-analog converter is configured to operate in high or low resolution mode, and includes: -20- This paper size applies to China National Standard (CNS) A4 (210 X 297 public directors) 9 \ k 522370 A8 B8 C8 U) The converter input device is configured to receive and receive—the digital input includes switching levels to V (n + m) units and one pixel representing the display, where η and m are integers; (b) —the decoder is configured to receive The claw bit of the digital input and the (2m + 1) reference voltage received simultaneously correspond to a different value of the ㈤ bit, and have higher and lower decoded output voltages, which is a continuous pair of the reference 黾(0-η-bit digital-to-analog converter is configured to receive the η-bit of the digital input, where the 更 -bit is more than the η-bit Valid, and having a converter output to provide a converter output voltage corresponding to (n + m) bit digital inputs for supplying the pixel to the display; and (d) — an n-bit converter switch for switching the η The bit-to-analog converter is turned on in the high-resolution mode and turned off in the low-resolution mode to ensure that the n-bit digital-to-analog conversion device in the low-resolution mode consumes little or at least Less power 9. Such as the scope of patent application The multi-format digital-to-analog converter of item 8, wherein the n-bit conversion switch is controlled to respond to a separate ^ -bit format control random number, and when the ^ -bit inputted by the digital is required, the control is activated 10. The multi-format digital-to-analog converter according to item 8 of the patent application scope, further comprising a buffer configured to receive the converter output voltage and supply a converter output to a data line corresponding to a pixel. 11 For example, the multi-format digital-to-analog converter of item 10 of the patent application scope further includes a buffer switch configured to switch the buffer at the high -21-This paper standard is applicable to China National Standard (CNS) Α4 specifications ( 210 X 297 mm) 70 3 2 2 5 8 8 8 8 AB c D 、 Open in patent range resolution mode and close in this low resolution mode to ensure that the buffer is almost in this low resolution mode Does not consume or at least consumes less power. 12. If the multi-mode digital-to-analog converter of item 11 of the patent application scope, wherein the remote buffer switch is controlled in response to a separate η-bit format control signal. When the η-bit input of the digital input is needed, the control signal will be activated. 13. If the multi-format digital-to-analog converter of item 8 of the patent application scope, further includes: a precharge A switch is located between the output of the low decoder and the data line corresponding to the pixel, and an isolation switch is located between the output of the low decoder and the data line corresponding to the pixel. 14. Multiple format digits such as item 13 of the scope of patent application To analog converter, which further includes a certain time circuit for providing first and second non-overlapping time periods, and in the high-resolution mode, the precharge switch is turned off only during the first time period and the isolating switch is turned on only This second time period is closed. 15. The multiple-type digital fragrance-to-analog converter according to item 4 of the patent application scope, wherein the isolation switch is kept open in the low-resolution mode, and the precharge switch extends the off time longer than the first time. The cycle is long. 16. If the multi-format digital-to-analog converter in item 8 of the scope of patent application, the converter can operate in the overlay mode in which the overlay information represented by the _ unit element input is displayed in a single color on the display, where in the overlay mode -22, 522370 A8 B8 C8 The decoder is configured to receive the unit cell input and provide a decoder output voltage ' when the color is specified by the unit cell input person to cause the pixel to switch the color. € k Π. If the multi-mode digital-to-analog conversion of the patent application No. 6 is used, the converter can operate in the unit display mode, where all pixels of the display are set to only two different switching levels. The unit cell input representative, wherein in the unit cell display mode, the decoder is configured to receive the unit cell input and provide a -decoder output voltage, the f voltage according to the unit π input value is two levels (-, and The n-bit converter switch is configured to turn off the n-bit digital-to-analog conversion in the unit display mode. The converter can operate in the overlay mode where the pixels of the display device are only set to two different switching levels represented by the unit cell input, where the decoder is configured to receive the unit cell display mode in the unit cell display mode. Unit input and provide a decoder output voltage, the voltage is based on the unit input value ^ one of two levels, and the n-bit converter switch is configured to turn off the n-bit digits to analog in the unit 疋 display mode A converter, in which 泫,. 爰, and 爰 are set to close the buffer in the unit element display mode. 19. A multi-format data driver for driving a data line of an active matrix display, including: a re-format sampling register for driving a data line of an active matrix display, the sampling register being configured to Low Solution-23- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 522370 AB c D 6. Operation in the patent application resolution mode, and the multi-format sampling register includes: (a) The sampler input device is configured to receive a digital input containing at least (n + m) bits and a switching level of one pixel representing the display, where ^ and m are integers; (b) — the first sampler includes m Sampling circuits each configured to sample one of the in bits of the digital input; (C) A second sampler includes an n sampling circuit configured to sample one of the n bits of the digital input, where the m bit ratio The n bit is more efficient; and (d)-the second sampler switch is configured to switch on in the high-resolution mode and switch off the second sampler in the low-high-resolution mode to ensure that when the sampling When the register operates in this low-resolution mode, the first sampler consumes little or at least less power, and a data driver of a multi-format digital-to-analog converter for driving the data line of an active matrix display. The data driver is configured to operate in a south or low resolution mode, and the multi-format digital-to-analog converter includes, (e) the converter input device is configured to receive a digital input containing at least (n + m) bits and Represents the switching level of one pixel of the display, where η and m are integers; (f) a decoder is configured to receive m bits of the digital input, and simultaneously receive (2 + 1) the reference voltage corresponding to m bits A different value of, and negative and higher decoding output voltage, that is, the reference voltage of a continuous pair, which has a value corresponding to one bit in the continuous pair corresponding to m bits; -24-scale of this paper Applicable to China National Standard (CNS) A4 specification (210 X 297 male 522370 A BCD) 6. Patent application scope (g)-η-bit digital-to-analog converter is configured to receive η-bit of the digital input, where 泫 m Bits are more efficient than the 11 bits and have a converter output to provide a converter output voltage corresponding to the (n + m) bit digital input for the pixel supplied to the display, and (h) — n bit conversion Switch to switch the n-bit digital-to-analog converter on in the high-resolution mode and off in the low-resolution mode to ensure the n-bit digital-to-analog converter in the low-resolution mode Almost no power consumption or at least less power consumption. 20.-A multi-format active moment indicator includes a multi-format data driver as described in the patent scope item. 21. A multi-format active matrix such as the scope of patent application item 20 A display, in which the multi-format data driver is integrated in a single piece on a substrate such as an active matrix thin film transistor. 22. The multi-format active matrix display as claimed in item 21 of the patent application, wherein the thin film transistor is polycrystalline silicon. 〃 -25- This paper size applies to China National Standard (CNS) A4 (210X297 mm)