TW521509B - Data integrity verification in a switching network - Google Patents

Abstract

A data transmission device (50) includes input circuitry (52), configured to receive a block of data over a network, the block containing an error-checking code, the input circuitry including input error-checking logic (30), which is adapted to detect a discrepancy between the data and the error-checking code and to generate a first error signal indicating whether the discrepancy was detected in the input circuitry. The device also includes output circuitry (56), configured to transmit the block of data, received by the input circuitry, over the network, and including output error-checking logic (60), which is adapted to detect the discrepancy between the data and the error-checking code and to generate a second error signal indicating whether the discrepancy was detected in the output circuitry. A comparator (66) is coupled to receive and compare the first and second error signals, so as to identify a source of the discrepancy.

Description

521509

The present invention relates to a system and method for high-speed data transmission, and more particularly to a method and device for verifying data integrity and detecting data errors in this system. Background of the invention: Error checking is an indispensable part of high-reliability data transmission systems-in order to ensure guilty operations, all data and control paths must be checked = Yuan t6 Wu 'which is caused by interference, cosmic radiation or Caused by other factors. One of the most common standard methods of error checking is to use cyclic redundancy code (ic, Redundancy code, CRC) check, which is inferred by applying a fixed polynomial to each data block transmitted. Typically, before a data packet is transmitted by a network or other communication connection, it is transmitted to the source node of the packet to calculate the CRC of the bits in the packet and append it to the packet. On the received packet, the receiving device calculates the CRC and compares it with the transmitted CRC ^. The difference in ^ indicates that an error has occurred. In ancestors or other complex networks, it is often required not only to detect errors, but also to determine the point at which a packet error occurs, as a measure. Since packets typically go from the source to the destination via the network, how many are on the network? During the journey, households need multiple CRC checks. Therefore, every time Pei Zhi's mother checks the CRC, one of this type of lllir is used in the infinite frequency band " network architecture, which is led by an industry Including Intel, Sun Microsystems, Hewlett-Packard, International Business Machines, Kangyi and Secret) to lead the development. And this method does not provide the error bit

521509 V. Description of the invention (2) The complete solution to the problem of the master, +, helmet difference occurred in the π seal J, the CDc check in the device input is; ϊ incorrectly between the two ::; the device that includes the path The network connection error and the element ΓΛΤ :, said, Α the solution to the problem of the wrong position # ^ w Including complex ;: input line 22 and output line 26 = :; change; set green: ί the input line includes -CRC The checker 30 is usually: a line that calculates ^ = of a bit in each received packet = a logical f packet path transmitted by a previous device i; iiRC has re == is in the same bit and will It is added to 70 via this setter 32. This data and its related parity are then stored for each order of material waiting to be processed by the exchange core 24: buffer storage 34, middle 26, may include additional data buffer storage: known in the device technology, the output line is checked with the bit The device 40 then calculates the parity of each data unit of the burial unit 6: the conversion in the data storage or the device 2 transmitted to the output device 疋. : The difference indicates that the header of the data packet is usually used for pointer, branch logic, and destination. A CRC calculator 44 calculates the change in the header of the shot packet for this next-trip journey, after which the new crc of ten daggers, but the separation of the functions of the outer two 70 makes device 2. A to B-= Error in external information. However, it is not enough to distinguish the internal and external data lines and storage capacity. ”When the equipment needs to be inspected, it is often a burden. Tian Beizhen ... The size is-bytes 521509 V. Description of the invention (3) Summary of the invention: Some differences of the present invention in the data transmission system of the present invention The internal device is often misunderstood. The line and output are transmitted by this device so the CRC is checked twice before it leaves. Entered and created in this device. No The error can be confirmed by the parity check amount on the error or other devices. Preferably, when the header information is reported to the management, and the internal error of the error is reported only by foreign law. Module management takes the path ’in order to find a better implementation of a special exchange device, but for improving the device and method to verify the integrity of the -Beckham. The point of view is to provide a device and a method to reduce errors between connections, in order to reduce the number of related embodiments. In one embodiment, a switch is exchanged in a network and a CRC check logic is included in both. 1 The block of the nursery material is typically a data packet type: once when it enters the device and once when it is: go to the difference between CS points out-the error is the rule, § CRCs for entering and leaving All of them are ignorant, the packet has already been picked up on the network before it reaches this setting. So there is no extra burden on the difference between internal and external errors. When a CRC error is detected in a packet, the packet table is confirmed by the network management entity, such as an infinite band module, whether it is internal or external. Another option is that only some errors, or no internal and external errors, are used in this way to use the header information to confirm the errors made by the packet through the network and take appropriate corrective measures. The example is to illustrate the construction of a packet exchange module. The principle of the present invention is obviously applicable to other types.

5019-3606-PF.ptd Page 7 521509 V. Description of the invention (4) ___ type data transmission device and system. Furthermore, CRCs, but i = are known in the art, but these embodiments are used. Bainafa's error checking can also make it possible to send a device according to one of the preferred embodiments of the present invention, including: I ^ Example, provides a data transmission in line, set to contain an error via a network of European branch- Check code, the input channel receives a data block, and the logic device is suitable for detecting the input error-check difference and generated in the data and z-the first error signal is -Detected in the road;: Impotence should be different from the input line

The output line is set to be transmitted through: the data block, the output line includes the check-in line, and the output line is used to detect Cui the data and the error_check code between ... and generate—the second error signal starts with Detected in the finger difference; with λ: a comparator different from the output line, coupled to receive and compare the first and number _ to confirm one of the sources of the difference. Preferably, the error-check code includes a cyclic redundancy code (C l

Redundancy Code (CRC).

It is preferable that when the error signal indicates that the difference is in the output line and ^ is detected in the input line, the comparator confirms that the difference is within the shock set. Preferably, when the error signal indicates that the difference is detected in both the output line and the input line, the comparator 2 is the source of the difference outside the device. ° ^

521509 V. Description of the invention (5) Preferably, the data block includes one person ^ The device includes a buffer memory, and the second is a packet of path information, and the path information is converted to a processing machine to receive the path Information and in the preferred embodiment = one or more error signals. Input and output ports, and the round-in and ^^ f-out lines each include multiple false checkers connected to the multi- ", and the check logic includes wrong output and one of the designated round ports and one of the input ports to the According to the present invention, the data block is converted. An input device and an output device are faulty; two or two, and a method for receiving the input device with one in the device is provided. The method includes: False-check code;,; block 'The block contains a wrong check of the block in order to detect a difference between the debt codes; the data entered by the rain and the error-check produce a first error signal to find out ; 疋 Whether shai is different from the turn in being detected via the device transmission, owe, information and check the block in the round of the device in order to presume that the check was generated-the second error letter ;: 'say, ~ Check the difference between the codes; find it; use *. Before saying whether the difference is in the round out and the first and second sources are compared horizontally. It is better to confirm one of the differences, the information The method includes extracting a packet of the path information = path information, and ___ or an error signal. Best 5 019-3606-PF.ptd Page 9 V. Description of the invention (6) The response is' the device belongs to a network and t responds to these — or multiple wrong methods include placing a defect to the network below the matching pattern and extracting The path information is only an example to illustrate the present invention. A simple explanation of the drawings: In order to make the present invention obvious, the attached chart descriptions such as the other purpose, special features, and advantages can be illustrated in the figure. Xi. ―Block diagram of the power exchange device. Known in it-with error detection. The second figure illustrates one of the exchange devices of the invention, error, and detection capabilities-in a preferred embodiment-with the third The figure is a block diagram illustrating an example of the meaning of the present invention. A flow chart of a method for checking and judging. A description of error symbols in a preferred embodiment 2 0 ′ 50 0 ~ exchange device 2 2 5 2 ~ Input line; 24 ~ switching core; 1 2 6, 5 6 ~ output line; 30, 60 ~ CRC checker; 32 ~ parity generator "34 ~ buffer memory; 40 ~ parity checker; 42 ~ path Logic; 5019-3606-PF.ptd 10th 521509

44 ~ CRC calculator; 54,64 ~ header memory; 58 ~ FIFO temporary register; 6 6 ~ comparator. Preferred embodiment: FIG. 2 illustrates an example of a crossover in a preferred embodiment of the present invention.

Block diagram of components. The device 50 includes an input line and a transmission line 56, which are connected by the switching core 24 as shown in FIG. 1. Preferably, the device 50 is a switch in a network, and more preferably in a switching module. 'As in an infinite band (Inf ini Band, IB) module. Therefore, the typical installation 50 includes a plurality of inputs and outputs, such as the device 20 in the first figure, but for the sake of simplicity, there is only one input line 52 and one output line 56 as shown in the second figure. By% ^^ Cyclic Redundancy Check (CRC) check

The device 30 checks the packets received through the input line 52 of the device 50, and generates an error signal for each packet 'CRC checker, preferably adding an error bit to the packet. This function is equivalent to putting an appropriate error bit in a first-in-first-out (FIF0) register 58 as shown in FIG. 2. The value of the error bit indicates whether the CRC code matches the data in the packet. For example, the value "quotes" indicates that an inconsistency was detected. The packet is placed in the buffer memory 34 to wait for transmission to the output line by the switching core 24, and the packet The header is controlled in the header memory 54 for future query. Preferably, the device 50 is set for high-speed operation, where the switching core can start transmitting packets to the CRC even before the CRC check is completed.

5019-3606-PF.ptd

521509

Output line 5 6. The CRC calculates that the packet received on the $ 4f line is transmitted to the path line 4 2 and this packet is borrowed 4 and produced by 60_ for CRC: error checking. The checker line 52 ΐϋ 传送 is transmitted to a comparator 66, which compares and checks each packet transmitted from the input element pair: store Ϊ, 56. The error bit of the 60 in the FIF register 0 is the error bit. . When booking. The comparator 66 preferably generates a central processing unit (CPU) 68 when the CRC checker 60 detects one of the errors in the packet, which is detected by the device 30. The output line 56 also includes a packet header memory 64, which is read by ㈣ to find the wrong packet. Although, the comparator shown in Figure 2 is a component separated from the cpu, the function of comparison = can also be implemented by a software program running on the CPU, according to the design convenience and program speed required to implement this function Consider. Additionally or alternatively, one of the sources of error (external or internal) is confirmed to be in a state register (not shown), which can be accessed by the CPU 68 or an external processor or both To the device 50. Fig. 3 is a flowchart illustrating a method for error detection and judgment in the device 50 in a preferred embodiment of the present invention. This method is initiated when the CRC checker 60 reports the comparator 66 that an error has been detected in a packet in the output line 56 in an error detection step 70. The comparator then checks the corresponding error bits generated by the CRC checker 30 in an error check step 72. In a decision step 74, the error bit from the checker 30 indicates whether the defect that caused the CRC error occurred in the device 50 or arrived at the device

521509

= m or other network) along the path of the packet. If this error bit 76 is before the packet arrives at the device 50, the packet is in the previous error step. The error bit indicates that the CRC checker 30 has found this device 5. The comparator informs the CPU that a possible error occurred in the device 50. A few steps in an internal error. When you find it in “50”, it is better for the CPU to stop ^ * p to hang around and collect diagnostic information and decide how to do it. When the drop = stop, the CPU self-buffer memory 54 ::: j Master information 'in the-head reading step side. (Because / wrong ^ packet processing procedures are based on jealousy 罟 fire 日, Japanese & detection and error processing may have been changed from :: 储存 Stored Qin 2 5 The operations are performed in parallel, so the header data is included. The other side or only exists in the buffer memory 64

Check the log 丨 Before the father's father changed to the direct output line 56 CRC: When the deputy detects an error, this packet is generally: discarded, so the header information turn line 52 loses all the required error information and reaches the buffer storage. 64. ) In the receiving-reporting step 82, the CPU is preferably notified to continue the operation. On-premise, such as-infinite band module management, f4 processor or-network management in real time, also notify the module H step 76 detected before the device 5 °-error based on the report from the CPU is being approved 4- error group Manage diagnostic error day pq ==, in-corrective action step 84. Reported by the CPU: and started * The server group management can determine the header information of the report order to pass through the device ^ The route taken through the network, and the device, 50, and the household to make the bureau k , And wrongs can be found. Module management

Fifth, this positive-wound report can be actually checked for its development. Description of the invention (10) Device errors can be distinguished and the taste is too good. The measures typically include the error of closing an i =: 1 network connection. Continued This calcium mouth divider is incorrectly connected or a wrong device and changes the ring or the second line. Preferably, this module manages to generate one-time notifications to the network, and the author has made an error. Although the preferred embodiment is complex? A special transaction is constructed in the module, which is described in -packet exchange. It is applied to other types of data transmission. The principle of this preparation is obvious. The embodiment uses CRCs, but it is familiar. Furthermore, this check can also be used. Although the errors of the other methods of the present invention are not used to limit the present invention, as described above, within the spirit and scope of Ranming, two; this artist, without departing from the scope of protection of the present invention, shall attach the attached application: 2: 5 5 5 Yurun, therefore, the scope of the patent application of Honcho is defined as

Claims (1)

Six, the scope of patent application 1 · An input line block contains a logic device, which is different and generates the editor which is received by the 查 Chacha output line in the way, which is different and generates a comparison number that is detected. In order to confirm 2. If the check code includes CRC). The data transmission device includes: a path configured to pass an error check code, the path to receive a block of data, which is suitable for investigating a rough entry line including an input error-checking a first error signal to = The error-check one of the codes arrives; find out if the difference is different from the input line, set to send ^ ^ data block, this round; the network uses the input line for debt check in the data = bracket Output error-check logic for the second error signal; check the 'difference between codes' to see if the difference is in the output line, the slave device is tapped to receive and compare the first and second error signals One source of difference. Please refer to the device described in item 1 of the patent scope, wherein the error is a cyclic redundancy code (Cyclic Redundancy CQde, 3) The device described in claim 1 of the patent scope, wherein when the error signal indicates the difference When it is detected in the turn-out line instead of the input line, the comparator confirms that the source of the difference is in the device. 4 · The device according to item 1 of the scope of patent application, wherein when the error The signal indicates that when the difference is detected in both the output line and the input line, the comparator confirms that the source of the difference is outside the device. 5 · The device as described in any one of the scope of the above-mentioned patent applications , Wherein the data block includes a packet containing path information, and wherein the device 5019-3606-PF.ptd Page 15 521509 6. The scope of the patent application includes a buffer storage path information to one place 6. · If applying for a special school, the input and input of the input and turn out to connect to the multiple ports, and receive One of the blocks specifies the output 7 · A method including: error detection code on the side device; checking a difference between the check codes of the block to generate a first check; after loading the data And a second check is generated on the device; and = it is lightly received ^ receives the information of the road # and the processor responds to one or more error signals. The device described in any one of item 4 of the present invention includes a plurality of input and output ports on its outgoing line, and 1 error-check logic device includes an error checker. The device in f includes a switching core. Coupled to convert the data block from one of the input ports to the output port.输入 The input for error detection in a device with an input and an output receives a block of data, the block contains an error to detect the data at the input and the error—check the error signal to indicate whether the difference is from the input After being intercepted, the block is checked to detect the difference between the error-check code of the output; the error signal indicates whether the difference is greater than the first and second of the output source Error signal in order to confirm one of the differences to benefit the method described in item 7, wherein the error loop is a redundant stone horse (Cyclic Redundancy Code, 8) Page 16 521509 VI. Scope of Patent Application (CRC). 9. The method according to item 7 of the scope of patent application, wherein comparing the first and second error signals includes confirming the difference when the error signal indicates that the difference is at the output rather than the input. The source is inside the device. 10. The method as described in item 7 of the scope of patent application, wherein comparing the first and second error signals includes confirming that when the error signal indicates that the difference is between the output and the input The source of the difference is outside the device. 11. The method according to any of claims 7-10, wherein the data block includes a packet containing path information, and wherein the method includes extracting the path information in response to one or more error signals. 1 2. The method according to item 11 of the scope of patent application, wherein the device belongs to a network, and wherein the method includes placing a fault in the network in response to the one or more error signals and extracting the path Information. 13. The method according to any one of claims 7-10 of the scope of patent application, wherein the input and output of the device include multiple inputs and outputs, and wherein transmitting the data via the device includes including from the inputs One of the inputs to one of the outputs specifies the output to exchange the data block. 5019-3606-PF.ptd Page 17