CN102571195A - Statistical circuit for fiber channel link state - Google Patents
Statistical circuit for fiber channel link state Download PDFInfo
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- CN102571195A CN102571195A CN2010106187954A CN201010618795A CN102571195A CN 102571195 A CN102571195 A CN 102571195A CN 2010106187954 A CN2010106187954 A CN 2010106187954A CN 201010618795 A CN201010618795 A CN 201010618795A CN 102571195 A CN102571195 A CN 102571195A
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Abstract
The invention provides a statistical circuit for a fiber channel link state, which comprises a register. The register is a register capable of receiving link error count, and trigger conditions of the register capable of receiving link error count include that an NOS primitive is received at an OL1 state; an NOS primitive is received at an OL2 state; an NOS primitive is received at a AC state; an NOS primitive is received at an LR1 state; an NOS primitive is received at an LR2 state; an NOS primitive is received at an LR3 state; and the register is in a LF1 state. The statistical circuit for the fiber channel link state can achieve information of the link state in the fiber channel link transmission process, provide a group of registers for a host machine to read, provide reliable statistical information for a system designer to debug and solve link error problems, provide an effective method for detecting the link state for system application and provides effective means for system reliability design.
Description
Technical field
The present invention relates to a kind of circuit that is used for adding up fibre channel links transmission data procedures Link State.
Background technology
At present; In the existing fibre channel links transmission course; Do not have the monitoring of relevant link-state information, integrity problems such as link down or link error in the link transmission process, occur, but the source that system designer can not be gone wrong by direct data analysis in debugging and the process safeguarded; Need investigation one by one, in the process of safeguarding and debugging, great inconvenience is just arranged.
Summary of the invention
In order to solve prior art problems, the invention provides a kind of information that can realize Link State in the fibre channel links transmission course, have the statistical circuit of the fibre channel links state that can supply the register that main frame reads.
Technical scheme of the present invention is: a kind of statistical circuit that is used for the fibre channel links state comprises register; Its special character is: said register is to receive link error counter register FC_RxLinkFailureCnt, and the said trigger condition that receives link error counter register FC_RxLinkFailureCnt is: receive a NOS primitive at the OL1 state; Receive a NOS primitive at the OL2 state; Receive a NOS primitive at the AC state; Receive a NOS primitive at the LR1 state; Receive a NOS primitive at the LR2 state; Receive a NOS primitive at the LR3 state; At the LF1 state.
Foregoing circuit also comprises reception lock-out counter register FC_RxLossSynCnt; The trigger condition of said reception lock-out counter register FC_RxLossSynCnt is: in port status machine lock-out or accepting state machine lock-out.
Foregoing circuit also comprises reception lossing signal counter register FC_RxLossSigCnt; The trigger condition of said reception lossing signal counter register FC_RxLossSigCnt is: in the dropout condition that except OL2 and two states of LF2, detects from input.
Foregoing circuit also comprises reception decoding error counter register FC_Rx10bErrCnt; The trigger condition of said reception decoding error counter register FC_Rx10bErrCnt is: when the data process that receives is confirmed not in 8B/10B coding schedule the inside.
Foregoing circuit also comprises reception alignment errors counter register FC_RxAlignErrCnt; The trigger condition of said reception alignment errors counter register FC_RxAlignErrCnt is: detect the signal that need align again.
Foregoing circuit also comprises reception ordered set incorrect polarity counter register FC_Rx0sdErrCnt; The trigger condition of said reception ordered set incorrect polarity counter register FC_Rx0sdErrCnt is: the 8B/10B decoder is checked through the incorrect polarity of outside 10B sign indicating number type.
Foregoing circuit also comprises reception EOF Abort counter register FC_RxEOFaCnt; The trigger condition of said reception EOFAbort counter register FC_RxEOFaCnt is: detect an EoFa sign indicating number type.
Foregoing circuit also comprises reception EOF error count register FC_RxEOFErrCnt; The trigger condition of said reception EOF error count register FC_RxEOFErrCnt is: in the process of receiving frame, receive LR, LRR, OLS, NOS primitive, and the effective ClientRxFrameValid signal of client received frame is effective.
Foregoing circuit also comprises reception crc error counter register FC_RxCRCErrCnt; The trigger condition of said reception crc error counter register FC_RxCRCErrCnt is: detect 32 bit data of the data of receiving, and use the CRC32 algorithm to calculate, see whether CRC is correct.
The circuit also includes sending EOF? Abort count register FC_TxEOFaCnt or send polarity error count register FC_TxParityErrorCnt or receive error count register FC_RxPSMErrCnt PSM or send K error count register FC_TxKErrCnt or send EOFni count register FC_TxEOFniCnt or receive frame count register FC_RxFrameCnt or receive word count register FC_RxWordCnt or transmit frame count register FC_TxFrameCnt word count register FC_TxWordCnt or send or receive RRDY count register FC_RxRRDYCnt or send RRDY count register FC_TxRRDYCnt; said sending EOF? Abort count register trigger conditions are: Client Buffer Overflow; said sending polarity Error Count Register trigger conditions are: detection of transmitted data polarity and coding table inside the polar inconsistent; said receiving error count register PSM trigger condition is: in the OL3 State receives LR, LRR primitives; receiving the AC status to LRR primitives; said transmission error count registers K trigger conditions are: detection of transmitted data does not meet the requirements of 8B/10B encoding; said sending EOFni count register trigger conditions are: polarity errors or incorrect CRC; said Receive Frame Count register trigger condition: detecting the frame; said received word count register trigger conditions are: detection of the SOF and EOF addition to frames other than the number of words; the transmission frame count register trigger condition : Detection of the correct transmission of the number of frames; transmit word count register of the trigger conditions are: the transmission is detected in addition to the SOF and EOF than the number of words in the frame; said reception counter register RRDY trigger condition : Detection received R_RDY primitives; said sending RRDY count register trigger conditions are: detection of transmitted R_RDY primitives.
The statistical circuit that is used for the fibre channel links state of the present invention can be realized the information of fibre channel links transmission course Link State; One group of register that can supply main frame to read is provided; For system designer provides reliable statistical information as debugging and solution link error problem; For system applies provides the method for effective detection Link State, for system reliability design provides effective means.
Description of drawings
Fig. 1 is a structural representation of the present invention.
Among the figure: 1-can receive the link error counter register, and 2-receives the lock-out counter register, and 3-receives the lossing signal counter register.
Embodiment
Referring to Fig. 1; Related a kind of statistical circuit that is used for the fibre channel links state of the present invention; Comprise the register that host CPU and the supplied host CPU that is connected with host CPU read; The present invention has realized the information gathering of Link State in the fibre channel links transmission course, can the statistical information in link of collecting and the data transmit-receive process be stored in the register, and these information can supply system designer to be used as debugging and solve the foundation of link error problem.
Register of the present invention is to receive link error counter register FC_RxLinkFailureCnt 1, and this trigger condition that can receive link error counter register FC_RxLinkFailureCnt 1 is: receive a NOS primitive or receive a NOS primitive or receive a NOS primitive or receive a NOS primitive or receive a NOS primitive or receive a NOS primitive or at the LF1 state at the LR3 state at the LR2 state at the LR1 state at the AC state at the OL2 state at the OL1 state.These triggering signals all can triggering for generating FC_RxLinkFailureCnt counting, each count cycle is if these triggering signals are all effectively then counter adds 1; The reading unit of the main frame that is attached thereto begins to read this register, and then the value of its counter can zero clearing.
The present invention also can be provided with and receive lock-out counter register FC_RxLossSynCnt 2, and its trigger condition is: port status machine lock-out and accepting state machine lock-out.These conditions all can triggering for generating FC_RxLossSynCnt counting, each count cycle, if these triggering signals are effective, then counter adds 1; Read this register, the value of counter can zero clearing.
The present invention also can be provided with and receive lossing signal counter register FC_RxLossSigCnt 3, and its trigger condition is: in the dropout condition that except OL2 and two states of LF2, detects from input.Above-mentioned these trigger conditions all can triggering for generating FC_RxLossSigCnt counting, each count cycle is if these signals are effectively then counter adds 1; Then read this register, the value of counter can zero clearing.
The present invention also can be provided with and receive decoding error counter register FC_Rx10bErrCnt; Its trigger condition is to confirm not in 8B/10B coding schedule the inside when the data process that receives; The counting of flip-flop number then, each count cycle is if these signals are effectively then counter adds 1; Read this register, the value of counter can zero clearing.
The present invention can also be provided with and receive alignment errors counter register FC_RxAlignErrCnt, and its trigger condition is: detect the condition (if outside input then realizes in the PCS module) that need align again; This trigger condition is effective, the counting of flip-flop number then, and each count cycle, if these triggering signals effectively then counter adds 1, then can be read this register by the reading unit of main frame, the value of counter can zero clearing.
The present invention also can be provided with and receive ordered set incorrect polarity counter register FC_Rx0sdErrCnt, and its trigger condition is: the 8B/10B decoder is checked through the incorrect polarity of outside 10B sign indicating number type; This trigger condition effectively then triggers the counting of its counter, and each count cycle is if these triggering signals effectively then counter adds 1; Then can be read this register by the reading unit of main frame, the value of counter can zero clearing.
Also can be provided with reception EOF Abort counter register FC_RxEOFaCnt trigger condition on the main frame of the present invention is: detect an EoFa sign indicating number type; This trigger condition effectively then triggers the counting of its counter, and each count cycle is if these triggering signals effectively then counter adds 1; Read this register, the value of counter can zero clearing.
Can also be provided with on the main frame of the present invention and receive EOF error count register FC_RxEOFErrCnt; Its trigger condition is: in the process of receiving frame, receive LR, LRR, OLS, NOS primitive, and the signal of the effective ClientRxFrameValid of client received frame is effective; Above-mentioned condition is set up and is represented that then the EOF that receives is invalid, and this received frame need abandon; In each count cycle, if above-mentioned triggering signal effectively then its counter adds 1; Read this register, the value of counter can zero clearing.
Can also receive crc error counter register FC_RxCRCErrCnt on the main frame of the present invention, can receive crc error information, its trigger condition is: detect 32 bit data of the data of receiving, and use the CRC32 algorithm to calculate, see whether CRC is correct.Each count cycle, if this trigger condition effectively then counter adds 1, the reading unit of main frame reads this register, and the value of counter can zero clearing.
Main frame of the present invention can also be provided with and send EOF Abort counter register FC_TxEOFaCnt, and its trigger condition is: if overflow in the client buffer district.In each count cycle, if this trigger condition effectively then counter adds 1.The same, read this register, the value of counter can zero clearing.
The present invention can also be provided with and send incorrect polarity counter register FC_TxParityErrorCnt, and its trigger condition is: if it is inconsistent to detect the data polarity and the polarity inside the coding schedule of sending.Each count cycle is if this trigger condition effectively then counter adds 1; Read this register, the value of counter can zero clearing.
The present invention can also be provided with and send EOFni counter register FC_TxEOFniCnt, and its trigger condition is: if incorrect polarity or wrong CRC.Each count cycle is if trigger condition effectively then counter adds 1; Read this register, the value of counter can zero clearing.
The present invention can also be provided with received frame counter register FC_RxFrameCnt, and its trigger condition is: detect frame.Each count cycle, if this trigger condition effectively then counter adds 1, then reads this register, the value of counter can zero clearing.
The present invention can also be provided with and receive word count register FC_RxWordCnt, and its trigger condition is: the number of the word of detected frame except SOF and EOF.In each count cycle, if this trigger condition effectively then counter adds 1; Read this register, the value of counter can zero clearing.
The present invention also includes and receives PSM error count register FC_RxPSMErrCnt, and the trigger condition of this register is: receive LR, LRR primitive at the OL3 state; Receive LRR primitive at the AC state.Each count cycle, if above-mentioned trigger condition effectively then its counter adds 1, the reading unit of main frame reads this register, and then the value of its counter can zero clearing.
The present invention can also comprise transmit frame counter register FC_TxFrameCnt, and the trigger condition of this register is: the number of the correct frame of detected transmission.Each count cycle is if this trigger condition effectively then counter adds 1; The reading unit of main frame reads this register, and then the value of its counter can zero clearing.
The present invention can also be provided with and send word count register FC_TxWordCnt, and the trigger condition of this register is: the number of word in the frame except SOF and EOF of detected transmission.In each count cycle, if this trigger condition effectively then its counter adds 1; The reading unit of main frame has read this register, and then the value of its counter can zero clearing.
The present invention can also be provided with and send K error count register FC_TxKErrCnt, and the trigger condition of this register is to detect the data of sending not meet the 8B/10B coding requirement.Each count cycle is if this trigger condition effectively then its counter adds 1; Main frame read this register, then the value of its counter can zero clearing.
The present invention can also be provided with and receive RRDY counter register FC_RxRRDYCnt, and the trigger condition of this register is: detect the R_RDY primitive that receives.In each count cycle, if this trigger condition effectively then counter adds 1; Then read this register, the value of its counter can zero clearing.
The present invention can also be provided with and send RRDY counter register FC_TxRRDYCnt, and the trigger condition of this register is: detect the R_RDY primitive that sends.In each count cycle, if this trigger condition effectively then counter adds 1; Read this register, then the value of its counter can zero clearing.
Above-mentioned various types of registers; Wherein any register can be set or the one group of register that is formed of registers also can be set according to main frame or other applied environment; Promptly confirm that with the function of register it is connected number and type according to actual needs; The method of effective detection Link State can be provided for system applies, and effective means be provided for system reliability design.
Claims (10)
1. a statistical circuit that is used for the fibre channel links state comprises register; It is characterized in that: said register is to receive link error counter register FC_RxLinkFailureCnt, and the said trigger condition that receives link error counter register FC_RxLinkFailureCnt is: receive a NOS primitive at the OL1 state; Receive a NOS primitive at the OL2 state; Receive a NOS primitive at the AC state; Receive a NOS primitive at the LR1 state; Receive a NOS primitive at the LR2 state; Receive a NOS primitive at the LR3 state; At the LF1 state.
2. the statistical circuit that is used for the fibre channel links state according to claim 1 is characterized in that: said circuit also comprises reception lock-out counter register FC_RxLossSynCnt; The trigger condition of said reception lock-out counter register FC_RxLossSynCnt is: in port status machine lock-out or accepting state machine lock-out.
3. the statistical circuit that is used for the fibre channel links state according to claim 2 is characterized in that: said circuit also comprises reception lossing signal counter register FC_RxLossSigCnt; The trigger condition of said reception lossing signal counter register FC_RxLossSigCnt is: in the dropout condition that except OL2 and two states of LF2, detects from input.
4. the statistical circuit that is used for the fibre channel links state according to claim 3 is characterized in that: said circuit also comprises reception decoding error counter register FC_Rx10bErrCnt; The trigger condition of said reception decoding error counter register FC_Rx10bErrCnt is: when the data process that receives is confirmed not in 8B/10B coding schedule the inside.
5. the statistical circuit that is used for the fibre channel links state according to claim 4 is characterized in that: said circuit also comprises reception alignment errors counter register FC_RxAlignErrCnt; The trigger condition of said reception alignment errors counter register FC_RxAlignErrCnt is: detect the signal that need align again.
6. the statistical circuit that is used for the fibre channel links state according to claim 5 is characterized in that: said circuit also comprises reception ordered set incorrect polarity counter register FC_Rx0sdErrCnt; The trigger condition of said reception ordered set incorrect polarity counter register FC_Rx0sdErrCnt is: the 8B/10B decoder is checked through the incorrect polarity of outside 10B sign indicating number type.
7. the statistical circuit that is used for the fibre channel links state according to claim 6 is characterized in that: said circuit also comprises reception EOF_Abort counter register FC_RxEOFaCnt; The trigger condition of said reception EOFAbort counter register FC_RxEOFaCnt is: detect an EoFa sign indicating number type.
8. the statistical circuit that is used for the fibre channel links state according to claim 7 is characterized in that: said circuit also comprises reception EOF error count register FC_RxEOFErrCnt; The trigger condition of said reception EOF error count register FC_RxEOFErrCnt is: in the process of receiving frame, receive LR, LRR, OLS, NOS primitive, and the effective ClientRxFrameValid signal of client received frame is effective.
9. the statistical circuit that is used for the fibre channel links state according to claim 8 is characterized in that: said circuit also comprises reception crc error counter register FC_RxCRCErrCnt; The trigger condition of said reception crc error counter register FC_RxCRCErrCnt is: detect 32 bit data of the data of receiving, and use the CRC32 algorithm to calculate, see whether CRC is correct.
10. according to claim 1 or 2 or 3 or 4 or 5 or 6 or 7 or the 8 or 9 described statistical circuits that are used for the fibre channel links state, it is characterized in that: said circuit also comprises transmission EOF Abort counter register FC_TxEOFaCnt or transmission incorrect polarity counter register FC_TxParityErrorCnt or reception PSM error count register FC_RxPSMErrCnt or transmission K error count register FC_TxKErrCnt or sends EOFni counter register FC_TxEOFniCnt or received frame counter register FC_RxFrameCnt or reception word count register FC_RxWordCnt or transmit frame counter register FC_TxFrameCnt or transmission word count register FC_TxWordCnt or reception RRDY counter register FC_RxRRDYCnt or transmission RRDY counter register FC_TxRRDYCnt; The trigger condition of said transmission EOF_Abort counter register is: overflow in the client buffer district; The trigger condition of said transmission incorrect polarity counter register is: it is inconsistent to detect the data polarity and the polarity inside the coding schedule of sending; The trigger condition of said reception PSM error count register is: receive LR, LRR primitive at the OL3 state; Receive LRR primitive at the AC state; The trigger condition of said transmission K error count register is: detect the data of sending and do not meet the 8B/10B coding requirement; The trigger condition of said transmission EOFni counter register is: incorrect polarity or wrong CRC; The trigger condition of said received frame counter register is: detect frame; The trigger condition of said reception word count register is: the number of the word of detected frame except SOF and EOF; The trigger condition of said transmit frame counter register is: the number of the correct frame of detected transmission; The trigger condition of said transmission word count register is: the number of word in the frame except SOF and EOF of detected transmission; The trigger condition of said reception RRDY counter register is: detect the R_RDY primitive that receives; The trigger condition of said transmission RRDY counter register is: detect the R_RDY primitive that sends.
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| CN201010618795.4A CN102571195B (en) | 2010-12-31 | 2010-12-31 | Statistical circuit for fiber channel link state |
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| CN201010618795.4A CN102571195B (en) | 2010-12-31 | 2010-12-31 | Statistical circuit for fiber channel link state |
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| CN102571195A true CN102571195A (en) | 2012-07-11 |
| CN102571195B CN102571195B (en) | 2015-04-15 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114039882A (en) * | 2021-11-11 | 2022-02-11 | 北京润科通用技术有限公司 | Bus port state analysis method and device and electronic equipment |
| CN117527061A (en) * | 2023-09-28 | 2024-02-06 | 笔特科技(深圳)有限公司 | Optical link performance detection device and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| EP1593213B1 (en) * | 2003-02-14 | 2007-08-08 | Ericsson AB | Optical transmission system |
| CN101908929A (en) * | 2010-07-12 | 2010-12-08 | 中电普瑞科技有限公司 | Method and device for real-time detection and handling of open circuit fault of fiber channel of industrial Ethernet |
| CN201966918U (en) * | 2010-12-31 | 2011-09-07 | 中国航空工业集团公司第六三一研究所 | Statistical circuit used for fiber channel link state |
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2010
- 2010-12-31 CN CN201010618795.4A patent/CN102571195B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1593213B1 (en) * | 2003-02-14 | 2007-08-08 | Ericsson AB | Optical transmission system |
| CN101908929A (en) * | 2010-07-12 | 2010-12-08 | 中电普瑞科技有限公司 | Method and device for real-time detection and handling of open circuit fault of fiber channel of industrial Ethernet |
| CN201966918U (en) * | 2010-12-31 | 2011-09-07 | 中国航空工业集团公司第六三一研究所 | Statistical circuit used for fiber channel link state |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114039882A (en) * | 2021-11-11 | 2022-02-11 | 北京润科通用技术有限公司 | Bus port state analysis method and device and electronic equipment |
| CN114039882B (en) * | 2021-11-11 | 2023-12-01 | 北京润科通用技术有限公司 | Bus port state analysis method and device and electronic equipment |
| CN117527061A (en) * | 2023-09-28 | 2024-02-06 | 笔特科技(深圳)有限公司 | Optical link performance detection device and method |
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Effective date of registration: 20221207 Address after: Room S303, Innovation Building, No. 25, Gaoxin 1st Road, Xi'an, Shaanxi 710075 Patentee after: XI'AN XIANGTENG MICROELECTRONICS TECHNOLOGY Co.,Ltd. Address before: 710068 No. 156 Taibai North Road, Shaanxi, Xi'an Patentee before: 631ST Research Institute OF AVIC |