經濟部智慧財產局員工消費合作社印製 521503 6010twf/002 A7 B7 五、發明說明（I ) 本發明是有關於一種寬頻之壓控振盪器’且特別是 有關於一種應用於數位電路與通訊系統中，可以提供高 效能及低功率操作的寬頻省電之壓控振盪器。 壓控振盪器不論是在數位電路或通訊系統裡皆扮演 極重要的角色。在數位電路中，壓控振盪器提供所需的 時脈訊號；在通訊系統中，壓控振盪器輸出的振盪頻率 可以作爲調變時的載波，或是解調時的本地振盪器之 用。同時，壓控振盪器也是鎖相迴路及頻率合成器的核 心元件。 一般而言，振盪器的設計是利用電感器L與電容 器C所組成的LC充放電電路，而LC充放電電路所產 生的振盪頻率是提供給上述電路之用。然而。近年來積 體電路的蓬勃發展，爲了提高電路的整合性，積體電路 使用電感元件就顯得不適用。 另外，在輸出頻率穩定度的部分，以在晶片上之振 盪器的設計，由於電感元件的特性不易掌握，且需要較 大的晶片面積，於是，大多採用串接式振盪器（Ring Oscillator)應用在積體電路上。 第1圖繪示寬頻鎖相迴路之方塊圖。人/表示參考 頻率。九,表示輸出頻率。乂與&表示選擇信號。C表示 控制電壓。系統提供一個參考頻率人/至相位偵測器（Phase DetectoOlOO，此參考頻率“經過相位偵測器100、充電 栗浦(Charge Pump)102 與迴路濾波器（Loop Filter)l〇4 而 轉換爲一個控制電壓K，此控制電壓及選擇信號\與& 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I-----—-------- 裝--------訂---------線 I (請先閱讀背面之注意事項再填寫本頁) 521503 601〇twf/002 A7 B7 五、發明說明（1) (請先閱讀背面之注意事項再填寫本頁) 輸入至寬頻之壓控振盪器106。此時，寬頻之壓控振盪 器106輸出一個輸出振盪頻率九，至所需的電路使用。除 法器（DWider)108接收由寬頻之壓控振盪器1〇6所輸出 的輸出頻率九，，並除以一個倍數得到一頻率與參考頻率 /<做比較，判斷輸出振盪頻率人,是否爲所需之頻率。 在第1圖中的寬頻之壓控振盪器106以第2圖繪示 習知之串接式壓控振盪器的電路圖做說明。串接式壓控 振盪器200是將奇數個反相器（lnvertei*)202串接起來形 成一個迴路。在此架構中，每一級反相器202的輸出端 接至下一級反相器202的輸入端，依此類推，再將最後 一級反相器202的輸出端接至第一級反相器202的輸入 端以形成一個閉迴路。利用每個反相增益級間轉態時所 產生的時間延遲，以造成振盪頻率輸出，而振盪頻率的 週期與反相增益串列的整體時間延遲有關。 經濟部智慧財產局員工消費合作社印製 在每一級反相器202的輸出端與接地之間連接壓控 負載，此壓控負載是由壓控電阻VCR204與電容器C206 串接而成。藉由調整壓控電阻VCR204上的控制電壓， 以改變相鄰反相增益級之間的充放電時間，以調整振盪 頻率。在每一級反相增益級之間的時間延遲可近似成RC 充放電常數，其中，C爲充放電時的負載電容，R爲充 放電時的等效電阻，其等效電阻値與反相器202中電晶 體的尺寸大小有關。 由於輸出的振盪頻率週期是與RC充放電常數成正 比，即表示振盪頻率與RC充放電常數成反比，則串接 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 521503 6〇10twf/〇〇2 A7 B7 五、發明說明（j) 式壓控振盪器200的功率消耗爲： P = C*F2 */ 其中，C爲輸出負載電容、V爲供應電壓與/爲振 盪頻率。將RC充放電常數取代振盪頻率/可以得到：Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 521503 6010twf / 002 A7 B7 V. Description of the Invention (I) The present invention relates to a wideband voltage-controlled oscillator ', and in particular to an application in digital circuits and communication systems , Can provide high-efficiency and low-power operation of a wide-band power-saving voltage-controlled oscillator. Voltage controlled oscillators play an extremely important role in both digital circuits and communication systems. In digital circuits, the voltage-controlled oscillator provides the required clock signal; in communication systems, the oscillation frequency output by the voltage-controlled oscillator can be used as a carrier during modulation or as a local oscillator during demodulation. At the same time, the voltage controlled oscillator is also the core component of the phase locked loop and frequency synthesizer. Generally speaking, the design of the oscillator uses an LC charge and discharge circuit composed of an inductor L and a capacitor C, and the oscillation frequency generated by the LC charge and discharge circuit is provided to the above circuit. however. In recent years, the development of integrated circuits has been booming. In order to improve the integration of the circuit, it is not suitable to use inductive components in integrated circuits. In addition, in the part of the output frequency stability, the design of the oscillator on the chip is not easy to grasp due to the characteristics of the inductive element and requires a large chip area. Therefore, most of them use Ring Oscillator applications. On integrated circuits. Figure 1 shows a block diagram of a wideband phase-locked loop. Person / indicates the reference frequency. Nine, indicating the output frequency.乂 and & indicate selection signals. C represents the control voltage. The system provides a reference frequency phase detector (Phase DetectoOlOO, this reference frequency "through the phase detector 100, charging Pump 102, and Loop Filter 104 and converted to a Control voltage K, this control voltage and selection signal \ && 3 This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) I -----—-------- equipment -------- Order --------- Line I (Please read the notes on the back before filling this page) 521503 601〇twf / 002 A7 B7 V. Description of the invention (1) (Please Read the notes on the back before filling this page) Input to the wideband voltage-controlled oscillator 106. At this time, the wideband voltage-controlled oscillator 106 outputs an output oscillation frequency of nine to the required circuit. Divider (DWider) 108 receives the output frequency nine output from the wideband voltage-controlled oscillator 106, and divides it by a multiple to obtain a frequency and compares it with the reference frequency / < to determine whether the output oscillation frequency is the desired frequency. The wide-band voltage-controlled oscillator 106 in FIG. 1 shows the electrical characteristics of the conventional series-connected voltage-controlled oscillator in FIG. 2. The circuit diagram is for illustration. The cascaded voltage controlled oscillator 200 is a series circuit of an odd number of inverters (lnvertei *) 202. In this architecture, the output of each stage of the inverter 202 is connected to the next stage. The input terminal of the inverter 202, and so on, and then the output terminal of the inverter 202 of the last stage is connected to the input terminal of the inverter 202 of the first stage to form a closed loop. Each inverting gain stage is used to interleave The time delay generated in the state is to cause the output of the oscillation frequency, and the period of the oscillation frequency is related to the overall time delay of the inversion gain string. A voltage-controlled load is connected between the terminal and the ground. This voltage-controlled load is made by connecting the voltage-controlled resistor VCR204 and the capacitor C206 in series. By adjusting the control voltage on the voltage-controlled resistor VCR204, the voltage between adjacent inverting gain stages can be changed. Charge and discharge time to adjust the oscillation frequency. The time delay between the inverting gain stages of each stage can be approximated as the RC charge and discharge constant, where C is the load capacitance during charge and discharge and R is the equivalent resistance during charge and discharge. Its equivalent resistance 値 is related to the size of the transistor in the inverter 202. Since the period of the oscillation frequency of the output is proportional to the RC charge and discharge constant, which means that the oscillation frequency is inversely proportional to the RC charge and discharge constant, 4 series Paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 521503 6〇10twf / 〇〇2 A7 B7 V. Description of the invention (j) type voltage controlled oscillator The power consumption of 200 is: P = C * F2 * / where C is the output load capacitance, V is the supply voltage, and / is the oscillation frequency. Substituting the RC charge and discharge constant for the oscillation frequency / can be obtained:
P = Kp*(C*V2y(l/RC) = KP*V2/R A爲常數，表示串接式壓控振盪器200中反相器202的 級數。由上述之數學式得知串接式壓控振盪器200的功 率消耗在電晶體的尺寸決定後就成爲定値，與振盪頻率 並無關係。 一般串接式振盪器的設計，爲了加大振盪器的輸出 頻率範圍，都是將振盪器產生最高頻率的時脈訊號，經 過頻率合成單元調整控制訊號，使頻率合成單元產生各 種不同輸出的頻率時脈，亦或改變串接增益級的數目以 達成寬頻輸出的目的。如此，可以增加振盪器的輸出頻 率範圍，但是外加的頻率合成單元與串接增益級的數目 增加，將使得串接式振盪器消耗更多的功率。 並且，在輸出頻率穩定度的部分，串接式振盪器是 利用電路轉態區域的時間變化以調整振盪頻率，容易受 到雜訊與溫度的影響，以致於輸出訊號的穩定度較差。 因此本發明係提供一種並聯式架構的寬頻省電之壓 控振盪器，是並聯數個小的串列反相增益級、壓控電阻、 電容與控制單元所組成。在相同的輸出負載下，利用控 制單元來選擇並聯串列的數目，以調整反相增益級的驅 動能力，藉由改變各輸出級的充放電時間常數，進而輸 5 (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---------線 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 521503 601〇twf/002 A7 B7 五、發明說明（f ) 出所需的振盪頻率。 (請先閲讀背面之注意事項再填寫本頁) 本發明係提供一種寬頻省電之壓控振盪器，其不必 經過頻率合成器電路或增加反相器的串接級數，可以有 效地增加振盪器的輸出頻率範圍。不但減少電路的複雜 度，同時也可達到降低功率消耗的目的。 本發明提出一種寬頻省電之壓控振盪器包括：邏輯 控制電路是由數個邏輯閘組合成。由外部裝置輸入選擇 信號至邏輯控制電路，並從邏輯控制電路輸出高準位與 低準位以作爲控制信號之用。並聯串列可控制反相器組 是由數個可控制反相器先串接成閉迴路形式的數個串列 可控制反相器組，並將這些串列可控制反相器組並聯成 並聯串列可控制反相器組。這些串列可控制反相器組的 輸出端並聯連接，以輸出所需的振盪頻率。由邏輯控制 電路輸出控制信號至並聯串列可控制反相器組的輸入 端，以控制並聯串列可控制反相器組的並聯數目。以及， 壓控負載耦接於並聯串列可控制反相器組與接地，以作 爲並聯串列可控制反相器組的負載。 經濟部智慧財產局員工消費合作社印製 本發明提出一種寬頻省電之壓控振盪器，其包括並 聯串列可控制反相器組是由數個可控制反相器先串接成 閉迴路形式的數個串列可控制反相器組，並將這些串列 可控制反相器組並聯成並聯串列可控制反相器組。這些 串列可控制反相器組的輸出端並聯連接，以輸出所需的 振盪頻率。由邏輯控制電路輸出控制信號至並聯串列可 控制反相器組的輸入端，以控制並聯串列可控制反相器 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 521503 6010twf/002 A7 B7 五、發明說明（I) 組的並聯數目。其中這些可控制反相器組包括： 輸出端切換可控制反相器包括供應電壓耦接至P型 金氧半導體的源極，P型金氧半導體的汲極耦接至負相 邏輯開關的電源端，負相邏輯開關的負載端耦接至正相 邏輯開關的電源端，以作爲此輸出端切換可控制反相器 的輸出端，正相邏輯開關的負載端耦接至N型金氧半導 體的汲極，N型金氧半導體的源極耦接至接地。此P型 金氧半導體的閘極與此N型金氧半導體的閘極相連接， 以作爲此輸出端切換可控制反相器之控制信號的輸入 端。以及，電源切換可控制反相器包括供應電壓耦接至 負相邏輯開關的電源端，負相邏輯開關的負載端耦接至 P型金氧半導體的源極，此P型金氧半導體的汲極耦接 至N型金氧半導體的汲極，以作爲此電源切換可控制反 相器的輸出端，此N型金氧半導體的源極耦接至正相邏 輯開關的電源端，此正相邏輯開關的負載端耦接至接 地。此P型金氧半導體的閘極與此N型金氧半導體的閘 極相連接，以作爲此電源切換可控制反相器之控制信號 的輸入端。 爲讓本發明之上述目的、特徵、和優點能更明顯易 懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下= 圖式之簡單說明： 第1圖繪示寬頻鎖相迴路之方塊圖； 第2圖繪示習知之串接式壓控振盪器的電路圖； 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----1 Ί------- ^--------訂---------線 1 (請先閱讀背面之注意事項再填寫本頁) 521503 6〇10twf/002 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（(） 第3圖繪示本發明之寬頻省電之壓控振盪器的方塊 圖； 第4圖繪示本發明之寬頻省電之壓控振盪器的電路 圖； 第5A圖繪示本發明之輸出端切換可控制反相器的 電路圖； 第5B圖繪示本發明之電源切換可控制反相器的電 路圖； 第6圖繪示本發明之邏輯控制電路的電路圖； 第7A圖爲輸出端切換可控制反相器架構的寬頻省 電之壓控振盪器於不同頻率時的功率消耗； 第7B圖爲電源切換可控制反相器架構的寬頻省電 之壓控振盪器於不同頻率時的功率消耗；以及 第1表爲邏輯控制電路的真値表。 標號說明= 100 :相位偵測器（Phase Detector) 102 :充電栗浦（Charge Pump) 104 :迴路濾波器（Loop Filter) 106，300，412 :寬頻之壓控振盪器（wide-range Voltage Control Oscillator) 108 :除法器(Divider) 200 ·串接式壓控振盪器（Series Voltage ControlP = Kp * (C * V2y (l / RC) = KP * V2 / RA is a constant, which indicates the number of stages of the inverter 202 in the series-connected voltage-controlled oscillator 200. The series-connected formula is obtained from the above mathematical formula. The power consumption of the voltage-controlled oscillator 200 becomes fixed after the size of the transistor is determined, and has nothing to do with the oscillation frequency. Generally, in order to increase the output frequency range of the oscillator, the oscillator is designed to increase the output frequency range of the oscillator. Generate the highest frequency clock signal, and adjust the control signal through the frequency synthesis unit to make the frequency synthesis unit produce various output frequency clocks, or change the number of cascaded gain stages to achieve the purpose of wideband output. In this way, the oscillation can be increased The output frequency range of the amplifier, but the increase in the number of additional frequency synthesis units and the series gain stage will cause the series oscillator to consume more power. And, in the part of the output frequency stability, the series oscillator is The time change of the circuit transition area is used to adjust the oscillation frequency, which is easily affected by noise and temperature, so that the stability of the output signal is poor. Therefore, the present invention provides a parallel type The structured wide-band power-saving voltage-controlled oscillator is composed of several small serial inverting gain stages, voltage-controlled resistors, capacitors, and a control unit in parallel. Under the same output load, the control unit is used to select the parallel series To adjust the driving capacity of the inverting gain stage, and by changing the charge and discharge time constants of each output stage, and then enter 5 (please read the precautions on the back before filling this page). Order --------- The size of the paper is applicable to China National Standard (CNS) A4 (210 X 297 mm) 521503 601twf / 002 A7 B7 V. Description of the invention (f) The required oscillation Frequency (Please read the notes on the back before filling this page) The present invention is to provide a wideband power-saving voltage controlled oscillator, which does not need to pass through the frequency synthesizer circuit or increase the number of inverters in series, which can effectively Increase the output frequency range of the oscillator. Not only reduces the complexity of the circuit, but also can achieve the purpose of reducing power consumption. The present invention proposes a wide-band power-saving voltage-controlled oscillator including: a logic control circuit is composed of a number of logic gates By external Set the input selection signal to the logic control circuit, and output the high level and low level from the logic control circuit as the control signal. Parallel controllable inverter groups are connected in series by several controllable inverters. Several strings in the form of a closed loop can control the inverter group, and these series controllable inverter groups are connected in parallel to form a parallel series controllable inverter group. These strings can control the output of the inverter group The terminals are connected in parallel to output the required oscillation frequency. The control signal is output from the logic control circuit to the input of the parallel series control inverter group to control the parallel series to control the number of inverter groups in parallel. The voltage-controlled load is coupled to the parallel series controllable inverter group and ground to serve as the load of the parallel series controllable inverter group. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics The present invention proposes a wideband power-saving voltage-controlled oscillator. The voltage-controlled oscillator includes a series of controllable inverters connected in parallel. The controllable inverters are connected in series to form a closed loop. Several serially controllable inverter groups are connected in parallel, and these serially controllable inverter groups are connected in parallel to form a parallel serially controllable inverter group. These strings control the output of the inverter bank in parallel to output the required oscillation frequency. The logic control circuit outputs the control signal to the input of the parallel series controllable inverter group to control the parallel series controllable inverter. 6 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 521503 6010twf / 002 A7 B7 V. Description of the Invention (I) Number of parallel connections of the group. The controllable inverter groups include: the output terminal switching controllable inverter includes a supply voltage coupled to the source of the P-type metal-oxide semiconductor, and the drain of the P-type metal-oxide semiconductor is coupled to the power source of the negative-phase logic switch Terminal, the load terminal of the negative-phase logic switch is coupled to the power terminal of the positive-phase logic switch as the output terminal for controlling the inverter output, and the load terminal of the positive-phase logic switch is coupled to the N-type metal-oxide semiconductor. The source of the N-type metal-oxide semiconductor is coupled to ground. The gate of the P-type metal-oxide semiconductor is connected to the gate of the N-type metal-oxide semiconductor, and is used as an input terminal for controlling the output of the inverter by switching the output terminal. And, the power-switchable controllable inverter includes a supply voltage coupled to a power terminal of a negative-phase logic switch, and a load terminal of the negative-phase logic switch is coupled to a source of a P-type metal-oxide semiconductor. The N-type metal-oxide semiconductor is coupled to the drain of the N-type metal-oxide-semiconductor to control the output of the inverter. The source of the N-type metal-oxide semiconductor is coupled to the power terminal of the positive-phase logic switch. The load terminal of the logic switch is coupled to ground. The gate of the P-type metal-oxide semiconductor is connected to the gate of the N-type metal-oxide semiconductor, and is used as an input terminal of the control signal for controlling the inverter when the power source is switched. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments in detail with the accompanying drawings as follows: = Brief description of the drawings: Figure 1 shows the broadband Block diagram of phase-locked loop; Figure 2 shows the circuit diagram of the conventional series-connected voltage-controlled oscillator; 7 This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) ----- 1 Ί ------- ^ -------- Order --------- Line 1 (Please read the precautions on the back before filling this page) 521503 6〇10twf / 002 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Description of the invention (() Figure 3 shows a block diagram of the broadband power-saving voltage-controlled oscillator of the present invention; Figure 4 shows the broadband power-saving voltage of the present invention The circuit diagram of the controlled oscillator; Fig. 5A shows the circuit diagram of the inverter which can control the output terminal of the present invention; Fig. 5B shows the circuit diagram of the inverter which can be controlled by the power switch of the present invention; Circuit diagram of the logic control circuit; Figure 7A is a wide-band power-saving voltage-controlled oscillator with output switching to control the inverter architecture Power consumption at different frequencies; Figure 7B is the power consumption of a wide-band power-saving voltage-controlled oscillator with inverter architecture that can control the inverter at different frequencies; and Table 1 is the true table of the logic control circuit. Explanation = 100: Phase Detector 102: Charge Pump 104: Loop Filter 106, 300, 412: Wide-range Voltage Control Oscillator 108: Divider 200 · Series Voltage Control
Oscillator) 202 :反相器（Inverter) 8 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公爱） (請先閱讀背面之注音？事項再填寫本頁) 裝.----- 訂 — I —----線 經濟部智慧財產局員工消費合作社印製 521503 6010twf/002 A7 B7 五、發明說明（q ) 204 :壓控電阻（Voltage Control Resistor) 206，410 :電容（Capacitor) 3 02,400,600:邏輯控制電路（Logic Control Circuit) 304，402 :並聯串列可控制反相器組（Parallel Series Controllable Inverter Bank) 306，404 :壓控負載（Voltage Control Load) 406 :可控制反相器（Controllable Inverter) 408 :電晶體（Transistor) 500, 502, 508, 510: P型金氧半導體電晶體（P Type Metal Oxide Semiconductor Transistor) 504, 506, 512, 514: N型金氧半導體電晶體(N Type Metal Oxide Semiconductor Transistor) 602，604，608，610，612，616 :反閘（NOT Gate) 606 :反或閘（NOR Gate) 614 :反及閘（NAND Gate) 實施例 在第1圖中的寬頻之壓控振盪器106以第3圖繪示 本發明之寬頻省電之壓控振盪器的方塊圖做說明。由外 部的控制裝置輸入5。與^的選擇信號至寬頻之壓控振盪 器300中的邏輯控制電路302。而邏輯控制電路302是 由數個邏輯閘所組合成的。邏輯控制電路302接收選擇 信號&與，並經邏輯閘的運算而得到一組高準位與低 準位的控制信號，此控制信號由邏輯控制電路302的輸 出端輸出至並聯串列可控制反相器組304。 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---------線 521503 6010twf/002 A7 B7 五、發明說明（F) (請先閱讀背面之注意事項再填寫本頁) 並聯串列可控制反相器組304是由數個可控制反相 器先串接成閉迴路形式的數個串列可控制反相器組，並 將這些串列可控制反相器組並聯成並聯串列可控制反相 器組304。這些串列可控制反相器組的輸出端並聯連接， 當並聯串列可控制反相器組304的輸入端接收來自邏輯 控制電路302所輸出的控制信號，以控制並聯串列可控 制反相器組304的並聯數目，並在並聯串列可控制反相 器組304的輸出端輸出所需的輸出振盪頻率九，。 以及，壓控負載306連接於並聯串列可控制反相器 組304，以作爲並聯串列可控制反相器組的負載。控制 電壓K由迴路率波器1〇4(參考第1圖）輸入至壓控負載 306，藉由改變控制電壓匕以達到改變並聯串列可控制反 相器組304所輸出的輸出振盪頻率九，。 經濟部智慧財產局員工消費合作社印製 第4圖繪示本發明之寬頻省電之壓控振盪器的電路 圖。實施例是以4條並聯串列可控制反相器組402爲例， 每條並聯串列可控制反相器組402是由3個可控制反相 器406串聯成閉迴路的形式，並且每條並聯串列可控制 反相器組402的輸入端與輸出端是互相連接，所連接的 輸出端是輸出寬頻之壓控振盪器412的輸出振盪頻率 /⑽。 邏輯控制電路400接收選擇信號S。與&，並經邏輯 閘的運算後，由8條控制線輸出4組控制信號，此4組 控制信號是控制4條並聯串列可控制反相器組402。藉 由改變並聯串列可控制反相器組402的並聯數目，以達 10 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 521503 601〇twf/〇〇2 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（y) 成不同輸出得頻率區段。 3組壓控負載404是連接在每個並聯串列可控制反 相器組402的輸出端與接地之間。每組壓控負載4〇4是 利用電晶體408作爲壓控電阻，再串接電容410作爲負 載電容，藉由改變電晶體408上的控制電壓Fc，以達到 改變並聯串列可控制反相器組4〇2所輸出的輸出振盪頻 率九，。 在積體電路相同面積的條件下，將習知之串接迴路 之反相器的串接式壓控振盪器，變成串接迴路之可控制 反相器406之多條並聯的串接式壓控振盪器，即原本單 一串列的反相器改成4條小串列的可控制反相器406。 利用邏輯控制電路400來控制並聯的數目以選擇寬頻之 壓控振盪器412的輸出頻區段。 在此，並聯串列可控制反相器組中的可控制反相器 4〇6電晶體尺寸的總合是等於習知之串接式壓控振盪器 中反相器電晶體的尺寸，亦即可控制反相器406充放電 時之等效電阻爲習知之反相器的4倍。在面對相同的負 載電容時，只要調整並聯串列可控制反相器組402的並 聯數目，即可調整並聯串列可控制反相器組402每一組 輸出端的驅動能力。改變充放電時間常數，進而達到改 變輸出的振盪頻率。 若系統需要較高頻率區段的振盪訊號時，將4條並 聯串列可控制反相器組402全部並聯起來，此時，並聯 串列可控制反相器組402的驅動能力是等於所有反相增 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公® ) ---------------- 裝 i I I I I I I 訂·！ I I ! 線 I (請先閱讀背面之注意事項再填寫本頁) 521503 6010twf/〇〇2 A7 B7 五、發明說明（R ) (請先閱讀背面之注意事項再填寫本頁) 益級的驅動能力，與習知之串接式反相器的驅動能力是 相同的。而且，寬頻之壓控振盪器412將產生最高頻率 區段的振盪訊號；反之，若系統需要較低頻率區段的振 盪訊號時，只要減少並聯串列可控制反相器組402的並 聯數目，則充放電時間常數變大，寬頻之壓控振盪器412 所產生的振盪頻率自然就降低，並且並聯串列可控制反 相器組402的驅動能力也隨之降低。 第5A圖繪示本發明之輸出端切換可控制反相器的 電路圖，在第5A圖中以N型金氧半導體電晶體與P型 金氧半導體電晶體做爲開關的例子。以下簡稱爲電晶體 MP500(P型金氧半導體電晶體）與MN506(N型金氧半導 體電晶體），以及控制用電晶體Ml 502(P型金氧半導體 電晶體）與M2 504(N型金氧半導體電晶體）。 經濟部智慧財產局員工消費合作社印製 輸出端切換可控制反相器是由電晶體MP500與MN 506所組成的反相器，其電晶體ΜΡ5〇0與MN506的兩 端分別連接電源Gd與接地GND，在電晶體MP500與 MN506之間串連兩個控制用電晶體Ml 502與M2 504。 Control_p 與 Control_n 分別爲電晶體 Ml 502 與 M2 504 的控制訊號，當Control_p爲低準位與Control—n爲高準 位時，電晶體Ml 502與M2 504均導通，反相器對下一 級電路進行充放電的動作；當Control_p爲高準位與 Control—η爲低準位時，電晶體Ml 502與M2 504均不 導通，反相器的輸出端是浮接狀態，此時反相器沒有動 作。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 經濟部智慧財產局員工消費合作社印製 521503 601〇twf/002 A7 B7 五、發明說明（丨ί) 第5Β圖繪示本發明之電源切換可控制反相器的電 路圖，同上述之方法。電源切換可控制反相器是由電晶 體ΜΡ510與ΜΝ512所組成的反相器，其電晶體ΜΡ500 與ΜΝ506的兩端分別連接控制用電晶體Ml 508與Μ2 514，而控制用電晶體Ml 508與M2 514分別連接電源 與接地GND。Control_p與Control_n分別爲電晶體 Ml 508與M2 514的控制訊號，當Control_p爲低準位 與Control_n爲高準位時，電晶體Ml 508與M2 514均 導通，反相器對下一級電路進行充放電的動作；當 Control_p爲高準位與Control_n爲低準位時，電晶體Ml 508與M2 514均不導通，反相器沒有電源供應，此時反 相器沒有動作。 第6圖繪示本發明之邏輯控制電路的電路圖。輸入 於邏輯控制電路600的Logicl與選擇信號&與A是作爲 選擇並聯串列可控制反相器組的並聯數目，其中Logicl 表示高準位且由供應電源所提供的。由反閘、反或閘與 反及閘所組成的邏輯控制電路600,所佔的面積不到振 盪電路的1%，在穩態操作時幾乎不消耗功率，此邏輯 控制電路600對整體的壓控振盪器是不會造成影響的。 控制訊號 Control—nl 與 Control_pl 是由 Logicl 輸 入於串聯的反閘602與反閘604而得到的。控制訊號 Control—n2與Control_p2是由選擇信號5；與&輸入於串 聯的反或閘606與反閘608而得到的。控制訊號 Control—n3與Control_p3是由選擇信號&與&輸入於串 13 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） ----l· Ί-------、裝--------訂---------線 (請先閱讀背面之注音？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 521503 五、發明說明（d) 聯的反閘610與反閘612而得到的。控制訊號Ccmtr〇l_n4 與C〇ntr〇l_P4是由選擇信號&與&輸入於串聯的反及閘 614與反閘616而得到的。 第1表爲邏輯控制電路的真値表。在第1表中，分 別輸入選擇信號S。與5\爲00、01、10與11時，所輸出 的四組控制訊號Control_n分別爲1000、1100、1110與 11ί1，以及控制訊號 Control_p 分別爲 0111、0011、0001 與0000，即分別代表並聯串列可控制反相器組的並聯數 目爲1、2、3與4 〇 本實施例以利用TSMC 0.6//m 1P3M CMOS製程完 成一個可操作在3.3V的寬頻振盪器。第7A圖爲輸出端 切換可控制反相器架構的寬頻省電之壓控振盪器於不同 頻率時的功率消耗，以輸出端切換可控制反相器所組成 的壓控振盪器（以第4圖爲例），其頻率輸出範圍可從 178MHz至792MHz，K爲並聯串列可控制反相器組的並 聯數目，壓控振盪器的功率消耗約與並聯串列可控制反 相器組的並聯數目成正比關係，從13.6Mw至62.6mW。 第7B圖爲電源切換可控制反相器架構的寬頻省電 之壓控振盪器於不同頻率時的功率消耗，以電源切換可 控制反相器所組成的壓控振盪器（以第4圖爲例），其頻 率輸出範圍可從184MHz至10.4GHz，K爲並聯串列可 控制反相器組的並聯數目，壓控振盪器的功率消耗約與 並聯串列可控制反相器組的並聯數目成正比關係，從 11.7MW至47.8mW。此架構除了具有寬頻與低功率的特 14 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------^-------^--------訂---------線 I (請先閱讀背面之注音？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 521503 6010twf/002 A7 B7 五、發明說明（$) 性之外，也將因加入控制電晶體所造成對最高輸出振盪 頻率的影響大幅減少，使得電源切換可控制反相器架構 之最高輸出振盪頻率較高於輸出端切換可控制反相器架 構之最高輸出振盪頻率。 因此，本發明的優點係應用於鎖相迴路中是先選擇 頻率區段，再加以控制電壓調整出所需之振盪頻率。而 寬頻省電之壓控振盪器不會因爲寬頻輸出使得單位控制 電壓變化對頻率變化的比値變大，讓寬頻省電之壓控振 盪器不會因控制電壓稍一改變就產生極大的頻率變化， 使鎖相迴路較穩定，相位雜訊與跳動(jitter)的表現較佳。 本發明的另一優點係由數組並聯串列反相增益級、 壓控電阻、電容與邏輯控制電路所組成，在相同的輸出 負載下，利用邏輯控制電路來選擇並聯串列反相增益級 的並聯數目，調整反相增益級的驅動能力，改變反相增 益級的各輸出級之充放電常數，進而輸出所需要的振盪 頻率。 本發明的再一優點係使用寬頻省電之壓控振盪器， 不必經過頻率合成器電路或增加反相器的串接級數，即 可有效地增加寬頻省電之壓控振盪器的輸出頻率範圍， 不但減少電路的複雜度，同時可達到降低寬頻省電之壓 控振盪器之功率消耗的目的。 綜上所述，雖然本發明已以較佳實施例揭露如上， 然其並非用以限定本發明，任何熟習此技藝者，在不脫 離本發明之精神和範圍內，當可作各種之更動與潤飾， 15 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I ----l· I-------- · I I I I---訂----— II--. (請先閱讀背面之注意事項再填寫本頁) 521503 6010twf/002 A7 _B7_ 五、發明說明（if) 因此本發明之保護範圍當視後附之申請專利範圍所界定 者爲準。 經濟部智慧財產局員工消費合作社印製 6 I---— — — — — — I· - I I I (請先閱讀背面之注意事項再填寫本頁) 訂---------線 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Oscillator) 202: Inverter 8 This paper size applies to China National Standard (CNS) A4 (21〇X 297 public love) (Please read the note on the back? Matters before filling this page) -Order — I —---- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 521503 6010twf / 002 A7 B7 V. Description of Invention (q) 204: Voltage Control Resistor 206, 410: Capacitor ( Capacitor) 3 02,400,600: Logic Control Circuit 304, 402: Parallel Series Controllable Inverter Bank 306, 404: Voltage Control Load 406: Controllable Inverter Controllable Inverter 408: Transistor 500, 502, 508, 510: P Type Metal Oxide Semiconductor Transistor 504, 506, 512, 514: N Type Metal Oxide Semiconductor Transistor Crystal (N Type Metal Oxide Semiconductor Transistor) 602, 604, 608, 610, 612, 616: NOT Gate 606: NOR Gate 614: NAND Gate Wideband voltage controlled vibration in the picture The oscillator 106 is illustrated in FIG. 3 as a block diagram of the wideband power-saving voltage-controlled oscillator of the present invention for illustration. Input 5 by external control device. The selection signal of AND is passed to the logic control circuit 302 in the wide-band voltage-controlled oscillator 300. The logic control circuit 302 is composed of a plurality of logic gates. The logic control circuit 302 receives the selection signal & amp, and obtains a set of high-level and low-level control signals through the operation of the logic gate. This control signal is output from the output terminal of the logic control circuit 302 to the parallel series and can be controlled. Inverter group 304. 9 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page). -------- Order ------- --Line 521503 6010twf / 002 A7 B7 V. Description of the invention (F) (Please read the notes on the back before filling this page) Parallel controllable inverter group 304 is composed of several controllable inverters. Several series connected in a closed loop form can control the inverter groups, and these series controllable inverter groups are connected in parallel to form a parallel series controllable inverter group 304. The outputs of these series controllable inverter groups are connected in parallel. When the input of the series controllable inverter group 304 receives a control signal output from the logic control circuit 302 to control the parallel series controllable inversion The number of parallel connections of the inverter group 304, and the output oscillation frequency required for the output terminal of the inverter group 304 can be controlled in the parallel series. And, the voltage-controlled load 306 is connected to the parallel series controllable inverter group 304 as a load of the parallel series controllable inverter group. The control voltage K is input to the voltage-controlled load 306 by the loop rate wave filter 104 (refer to FIG. 1), and the output oscillation frequency of the output of the inverter group 304 controlled by changing the control voltage d is changed by the control voltage dagger. . Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 4 shows the circuit diagram of the wideband power-saving voltage-controlled oscillator of the present invention. The embodiment is based on the example of four parallel series controllable inverter groups 402. Each parallel series controllable inverter group 402 is a series of three controllable inverters 406 connected in a closed loop, and each The parallel series can control the input and output of the inverter group 402 to be connected to each other, and the connected output is the output oscillation frequency of the voltage-controlled oscillator 412 which outputs a wide frequency / ⑽. The logic control circuit 400 receives a selection signal S. And & and after the operation of the logic gate, four sets of control signals are output by eight control lines. The four sets of control signals are used to control four parallel series controllable inverter groups 402. The number of inverters 402 can be controlled in parallel by changing the parallel series to reach 10 paper sizes. Applicable to China National Standard (CNS) A4 (210 X 297 mm) 521503 601〇twf / 〇〇2 A7 B7 Economy Printed by the Consumer Cooperatives of the Ministry of Intellectual Property Bureau V. Invention Description (y) Into different frequency bands. Three sets of voltage-controlled loads 404 are connected between the output terminal of each parallel-series controllable inverter group 402 and ground. Each group of voltage-controlled load 400 uses a transistor 408 as a voltage-controlled resistor, and then a capacitor 410 is connected in series as a load capacitor. By changing the control voltage Fc on the transistor 408, the inverter can be controlled by changing the parallel series. The output oscillation frequency output by group 402 is nine. Under the condition of the same area of the integrated circuit, the conventional series-connected voltage-controlled oscillator of the inverter connected in series is turned into a series-connected series-connected voltage-controlled oscillator that can control the inverter 406 in the series circuit. The oscillator, that is, the inverter with a single string is changed into a controllable inverter 406 with 4 small strings. The logic control circuit 400 is used to control the number of parallel connections to select the output frequency section of the wideband voltage controlled oscillator 412. Here, the sum of the size of the controllable inverter 406 transistors in the series-parallel controllable inverter group is equal to the size of the inverter transistors in the conventional series-connected voltage-controlled oscillator, that is, The controllable equivalent resistance of the inverter 406 during charging and discharging is four times that of the conventional inverter. When facing the same load capacitance, as long as the parallel series can control the number of inverter groups 402 connected in parallel, the parallel series can control the drive capability of each output terminal of the inverter group 402. Change the charge and discharge time constant, and then change the output oscillation frequency. If the system needs the oscillation signal in the higher frequency section, all four parallel series controllable inverter groups 402 are connected in parallel. At this time, the parallel series controllable inverter group 402's driving capacity is equal to all the Incrementally, the paper size is applicable to the Chinese National Standard (CNS) A4 (210 X 297 male®) ---------------- Install i IIIIII Order! II! Line I (Please read the precautions on the back before filling out this page) 521503 6010twf / 〇〇2 A7 B7 V. Description of the invention (R) (Please read the precautions on the back before filling out this page) Premium-level drive capability The driving ability is the same as the conventional serial inverter. In addition, the wideband voltage-controlled oscillator 412 will generate the oscillation signal in the highest frequency section. Conversely, if the system needs the oscillation signal in the lower frequency section, as long as the parallel series is reduced, the number of parallel connections of the inverter group 402 can be controlled. Then the charging and discharging time constant becomes larger, and the oscillation frequency generated by the wide-band voltage-controlled oscillator 412 naturally decreases, and the driving capability of the parallel-series controllable inverter group 402 also decreases. Fig. 5A shows a circuit diagram of an output-switchable controllable inverter according to the present invention. In Fig. 5A, an N-type metal-oxide semiconductor transistor and a P-type metal-oxide semiconductor transistor are used as examples of switches. Hereinafter referred to as the transistor MP500 (P-type metal-oxide-semiconductor transistor) and MN506 (N-type metal-oxide-semiconductor transistor), and the control transistor Ml 502 (P-type metal-oxide semiconductor transistor) and M2 504 (N-type gold Oxygen semiconductor transistor). Printed output switching of the printed output terminal of the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is an inverter composed of transistors MP500 and MN 506. The two ends of the transistors MP500 and MN506 are respectively connected to the power source Gd and ground GND. Two control transistors Ml 502 and M2 504 are connected in series between the transistors MP500 and MN506. Control_p and Control_n are the control signals of the transistors Ml 502 and M2 504, respectively. When Control_p is the low level and Control_n is the high level, the transistors Ml 502 and M2 504 are both turned on, and the inverter performs the next stage circuit. Charging and discharging action; when Control_p is high and Control_η is low, the transistors Ml 502 and M2 504 are not conducting, and the output of the inverter is floating, and the inverter is not operating at this time. . This paper size applies to China National Standard (CNS) A4 (210 X 297 public love) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 521503 601twf / 002 A7 B7 V. Description of the invention (丨 ί) Drawing 5B The circuit diagram of the inverter controllable inverter according to the present invention is the same as that described above. The power-switchable controllable inverter is an inverter composed of transistors MP510 and MN512. The two ends of the transistors MP500 and MN506 are respectively connected to the control transistors Ml 508 and M2 514, and the control transistor Ml 508 and M2 514 is connected to power and ground. Control_p and Control_n are control signals of transistors Ml 508 and M2 514, respectively. When Control_p is low and Control_n is high, transistors Ml 508 and M2 514 are both turned on, and the inverter charges and discharges the next stage circuit. When Control_p is at the high level and Control_n is at the low level, the transistors Ml 508 and M2 514 are not turned on, and the inverter has no power supply, and the inverter does not operate at this time. FIG. 6 is a circuit diagram of a logic control circuit of the present invention. Logicl and selection signals & and A input to the logic control circuit 600 are used as selection parallel series to control the number of parallel connection of the inverter group, where Logicl represents a high level and is provided by the power supply. The logic control circuit 600 composed of anti-gate, anti-or gate and anti-and-gate gates occupies less than 1% of the area of the oscillating circuit, and consumes almost no power during steady-state operation. Controlling the oscillator has no effect. The control signals Control_nl and Control_pl are obtained by inputting Logicl in series anti-gate 602 and anti-gate 604. The control signals Control_n2 and Control_p2 are obtained by selecting the signal 5; and & inputs in the inverse OR gate 606 and the reverse gate 608 in series. The control signals Control_n3 and Control_p3 are input by the selection signals & and & 13 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public love) ---- l · Ί ---- ---, install -------- order --------- line (please read the note on the back? Matters before filling out this page) Printed by the Employee Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 521503 2. Description of the invention (d) The combined anti-gate 610 and anti-gate 612 are obtained. The control signals Ccmtr01_n4 and Contr0_P4 are obtained by selecting signals & and & The first table is the truth table of the logic control circuit. In the first table, the selection signal S is input respectively. When 5 and 00 are 00, 01, 10, and 11, the four sets of control signals Control_n output are 1000, 1100, 1110, and 11ί1, and the control signals Control_p are 0111, 0011, 0001, and 0000, respectively. The number of parallel controllable inverter groups is 1, 2, 3, and 4. In this embodiment, a TSMC 0.6 // m 1P3M CMOS process is used to complete a 3.3V wide-band oscillator. Figure 7A shows the power consumption of a wide-band power-saving voltage-controlled oscillator controlled by the inverter at different frequencies when the output is switched, and the voltage-controlled oscillator composed of the inverter is controlled by the output switching. The figure shows an example), whose frequency output range can be from 178MHz to 792MHz, K is the number of parallel series controllable inverter groups, and the power consumption of the voltage controlled oscillator is about the same as that of the parallel series controllable inverter groups. The number is directly proportional, from 13.6Mw to 62.6mW. Figure 7B shows the power consumption of a wide-band power-saving voltage-controlled oscillator that can control the inverter architecture at different frequencies. Power switching can control the voltage-controlled oscillator composed of inverters. Example), its frequency output range can be from 184MHz to 10.4GHz, K is the number of inverters connected in parallel in series, and the power consumption of the voltage controlled oscillator is about the number of inverters connected in parallel in series. It is directly proportional, from 11.7MW to 47.8mW. In addition to the special 14 paper with wideband and low power, this architecture is applicable to China National Standard (CNS) A4 (210 X 297 mm) ------ ^ ------- ^ ----- --- Order --------- Line I (Please read the note on the back? Matters before filling out this page) Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 521503 6010twf / 002 A7 B7 V. Description of the invention ( In addition, the influence on the maximum output oscillation frequency caused by the control transistor is greatly reduced, so that the maximum output oscillation frequency of the inverter architecture that can be controlled by power switching is higher than the inverter that can be controlled by output switching. The highest output oscillation frequency of the architecture. Therefore, the advantage of the present invention is that in the application of the phase locked loop, the frequency range is selected first, and then the control voltage is used to adjust the required oscillation frequency. The wide-band power-saving voltage-controlled oscillator does not make the ratio of unit control voltage change to frequency change larger because of the wide-band output, so that the wide-band power-saving voltage-controlled oscillator does not generate a great frequency due to a slight change in the control voltage. The change makes the phase-locked loop more stable, and the performance of phase noise and jitter is better. Another advantage of the present invention is that it consists of an array of parallel inverting gain stages in parallel, a voltage-controlled resistor, a capacitor, and a logic control circuit. Under the same output load, a logic control circuit is used to select the parallel inverting gain stage in parallel. The number of parallel connection, adjust the driving ability of the inverting gain stage, change the charge and discharge constant of each output stage of the inverting gain stage, and then output the required oscillation frequency. Another advantage of the present invention is the use of a wide-band power-saving voltage-controlled oscillator. The output frequency of the wide-band power-saving voltage-controlled oscillator can be effectively increased without going through a frequency synthesizer circuit or increasing the number of inverters in series. The range not only reduces the complexity of the circuit, but also reduces the power consumption of the wideband power-saving voltage-controlled oscillator. In summary, although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Retouching, 15 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) I ---- l · I -------- · III I --- Order ----— II--. (Please read the notes on the back before filling this page) 521503 6010twf / 002 A7 _B7_ V. Description of the invention (if) Therefore, the scope of protection of the present invention shall be defined by the scope of the attached patent application. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6 I ---—— — — — — — I ·-III (Please read the precautions on the back before filling this page) Order --------- line book Paper size applies to China National Standard (CNS) A4 (210 X 297 mm)