TW519722B - Method for producing metal plug - Google Patents
Method for producing metal plug Download PDFInfo
- Publication number
- TW519722B TW519722B TW088105505A TW88105505A TW519722B TW 519722 B TW519722 B TW 519722B TW 088105505 A TW088105505 A TW 088105505A TW 88105505 A TW88105505 A TW 88105505A TW 519722 B TW519722 B TW 519722B
- Authority
- TW
- Taiwan
- Prior art keywords
- metal
- layer
- plug
- barrier layer
- insulating layer
- Prior art date
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 66
- 239000002184 metal Substances 0.000 title claims abstract description 66
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 230000004888 barrier function Effects 0.000 claims abstract description 30
- 239000000126 substance Substances 0.000 claims abstract description 7
- 238000009413 insulation Methods 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 82
- 238000000034 method Methods 0.000 claims description 35
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 15
- 229910052721 tungsten Inorganic materials 0.000 claims description 15
- 239000010937 tungsten Substances 0.000 claims description 15
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 6
- 239000011229 interlayer Substances 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 4
- 230000002079 cooperative effect Effects 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 238000004544 sputter deposition Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 3
- 238000005498 polishing Methods 0.000 abstract description 3
- 239000000463 material Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- WIGAYVXYNSVZAV-UHFFFAOYSA-N ac1lavbc Chemical compound [W].[W] WIGAYVXYNSVZAV-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
519722 45 5 5twf.doc/002 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（丨） 本發明是有關於一種半導體元件的製造方法’且特別 是有關於一種金屬插塞(metal Plug)的製造方法。 一般形成金屬插塞的方法爲在絕緣層之上以及絕緣層 的介層窗中，先沈積一層共形的阻障層，再沈積一層金屬。 然後將阻障層之上的金屬去除掉’只留下介層窗中的金屬 而形成金屬插塞。 將絕緣層之上的金屬去除掉，習知已有幾種方法。以 金屬鎢插塞來說，第一種方法爲利用含離子的電槳來進 行回蝕。因爲氟離子電漿的高反應性，造成金屬鎢插塞的 表面凹陷，和阻障層表面的高度差可高達1000埃。第二 種方法爲回蝕之後，再對阻障層進行化學機械硏磨法 (chemical mechanical polishing，CMP) ’ 以減少金屬鑛插 塞表面的凹陷程度。一般金屬鎢插塞所用的阻障層之材質 爲氮化鈦，以絕緣層的材質爲氧化矽來說，CMP對此兩種 材質的選擇性很差。結果爲氮化鈦層被磨掉之後’常不能 停在氧化矽層的表面，造成金屬鎢插塞突出於氧化矽層的 表面，高度差可高達1500埃。以上述方法所形成之金屬 插塞不是表面凹陷就是突出於絕緣層之上，造成在後續形 成金屬導線層時，其表面也跟著不平整。因此當對金屬導 線層進行微影步驟時，將發生去焦（defocus)的問題，影響 到所形成之金屬導線的形狀，使產品品質低落。 於是提出另外一種方法，從一開始就對金屬鎢層使用 金屬鎢CMP，至阻障層時，再進行金屬鎢的改善CMP (t〇Uch up CMP)，降低硏磨速率。此種方法可以得到相當平整的 3 l·_____，丨_丨»冬_丨 (請先閱讀背面之注意事項存填寫本頁) 灯519722 45 5 5twf.doc / 002 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (丨) The present invention relates to a method for manufacturing a semiconductor element, and in particular to a metal plug Plug) manufacturing method. A common method for forming a metal plug is to deposit a conformal barrier layer on top of the insulating layer and in the interlayer window of the insulating layer, and then deposit a layer of metal. Then the metal on the barrier layer is removed ', leaving only the metal in the via window to form a metal plug. There are several methods for removing the metal on the insulating layer. For metal tungsten plugs, the first method is to etch back using an ion paddle. Because of the high reactivity of the fluoride ion plasma, the surface of the metal tungsten plug is recessed, and the height difference between the surface of the barrier layer and the barrier layer can be as high as 1000 angstroms. The second method is to perform chemical mechanical polishing (CMP) on the barrier layer after etch back to reduce the degree of depression on the surface of the metal ore plug. The material of the barrier layer used in general metal tungsten plugs is titanium nitride, and the material of the insulating layer is silicon oxide. The selectivity of CMP for these two materials is very poor. The result is that after the titanium nitride layer is worn away, it often cannot stop on the surface of the silicon oxide layer, causing the tungsten tungsten plug to protrude from the surface of the silicon oxide layer, and the height difference can be as high as 1500 angstroms. The metal plug formed by the above method is either concave on the surface or protrudes above the insulating layer, so that when the metal wire layer is subsequently formed, the surface thereof is also uneven. Therefore, when the lithography step is performed on the metal wire layer, a problem of defocus will occur, which affects the shape of the formed metal wire and lowers the product quality. Therefore, another method is proposed. From the beginning, tungsten CMP is used for the metal tungsten layer. When the barrier layer is used, the tungsten CMP (t0Uch up CMP) is performed to reduce the honing rate. This method can get a fairly flat 3 l · _____ ， 丨 _ 丨 »Winter_ 丨 (Please read the precautions on the back and save this page to fill in)
本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 519722 4555tvvf.d〇c/002 A7 B7 五、發明説明（2 ) 表面’金屬鎢插塞的表面高度差約在200 - 300埃之內， 但是成本非常昂貴，每片晶圓的成本高達約35美金。 医I此本發明提供一種金屬插塞的形成方法，可以以較 少^勺成本來得到具有相當平整表面的金屬插塞。此方法包 括：在具有絕緣層的基底上，形成共型之阻障層，且絕緣 層具有開□。然後形成金屬層於阻障層之上，塡滿開口。 手妾著:對金屬層進行第一回蝕步驟，至阻障層爲止，形成金 S插塞°再對暴露出之阻障層進行第二回蝕步驟，至絕緣 層爲止。最後才對金屬插塞以及絕緣層進行平坦化步驟。 依據本發明的方法，先用蝕刻的方法去除高於絕緣層 表面的金屬層和阻障層，然後才用化學機械硏磨法來平坦 化整個金屬插塞和絕緣層的表面。不僅省下許多成本，每 片晶圓只需約4 - 5美元，而且所花時間也較短，可大幅 提尚產能。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1A - 1E圖是依照本發明較佳實施例的一種金屬插 塞製造流程剖面圖。 圖式之標記說明： 100 :基底 110 :絕緣層 120 :開口 (請先閱讀背面之注意事項再填寫本頁) 訂This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) 519722 4555tvvf.doc / 002 A7 B7 V. Description of the invention (2) The surface height difference of the surface 'metal tungsten plug is about 200-300 angstroms Within, but the cost is very expensive, the cost of each wafer is as high as about 35 US dollars. The present invention provides a method for forming a metal plug, which can obtain a metal plug with a relatively flat surface at a relatively low cost. This method includes forming a conformal barrier layer on a substrate having an insulating layer, and the insulating layer has an opening. A metal layer is then formed over the barrier layer, filling the opening. Holding your hands: perform a first etch-back step on the metal layer until the barrier layer forms a gold S plug, and then perform a second etch-back step on the exposed barrier layer until the insulating layer. Finally, the metal plug and the insulating layer are subjected to a planarization step. According to the method of the present invention, the metal layer and the barrier layer above the surface of the insulating layer are removed by etching first, and then the entire surface of the metal plug and the insulating layer is planarized by chemical mechanical honing. Not only does it save a lot of costs, it only costs about $ 4 to $ 5 per wafer, but it also takes less time, which can significantly increase capacity. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments in detail with the accompanying drawings as follows: Brief description of the drawings: Sections 1A-1E FIG. Is a sectional view of a metal plug manufacturing process according to a preferred embodiment of the present invention. Explanation of the marks of the drawings: 100: substrate 110: insulation layer 120: opening (please read the precautions on the back before filling this page) Order
經濟部智慧財產局員工消費合作社印製 519722 45 5 5tvvf.doc/002 A7 B7 五、發明説明（/ ) / (請先閲讀背面之注意事項再填寫本頁) 13 0 :阻_:層 H0 :金屬層 11〇 :金屬插塞 實施例 請參照第1A - 1E圖，其繪示依照本發明較佳實施例 的一種金屬插塞製造流程剖面圖。 請參照第1A圖，在基底100上有絕緣層110 ’絕緣 層110具有開口 120。絕緣層的材質例如可爲氧化矽，其 形成的方法，包括有以矽酸四乙酯（tetraethyl orthosilicate， TEOS，Si(OC2H5)4)爲氣源的低壓化學氣相沈積法 (LPCVD) 〇 請參照第1B圖，形成共形之阻障層130於開口 120 中以及絕緣層110之上。阻障層130的材質例如可爲氮化 鈦，其形成的方法包括濺鍍法。再形成金屬層140於阻障 層130之上，其材質例如可爲金屬鎢，而形成的方法包括 以WF6爲主要氣源的化學氣相沈積法。 經濟部智慧財產局員工消費合作社印製 請參照第1C圖，對金屬層140進行回蝕，至阻障層 130爲止，形成金屬插塞150。在此回蝕步驟，若金屬層140 的材質爲金屬鎢時，可使用SF6/02/Ar電漿，來進行乾蝕 刻。 請參照第1D圖，對暴露出之阻障層13〇進行回蝕， 至絕緣層110爲止，以減少金屬插塞150之凹陷程度。在 此回蝕步驟，若阻障層130的材質爲氮化鈦時，可使用 C12/BC13電槳來進行乾蝕刻。 1 —本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ' · 519722 45 5 5tvvf.doc/〇〇2 A7 B7 ___ 五、發明説明（^ ) 請參照第1E圖，對金屬插塞~150以及絕緣層no進 行平坦化步驟。平坦化的方法，例如可用化學機械硏磨法， 以較緩慢的硏磨速率來進行之，來達到使金屬插塞15〇以 及其周圍之絕緣層110的表面平整之目的。 由上述本發明較佳實施例可知’因爲先使用蝕刻的方 法來去除絕緣層表面以上的金屬層和阻障層，使成本降 低，生產時間縮短。然後再使用平坦化方法，例如在此使 用化學機械硏磨法，來使金屬插塞表面平整。所以在兼顧 成本和產能之考量下，又能在金屬插塞製程之後，提供一 平整表面，使後續沈積的金屬導線層可有較平坦化的表 面’以利微影製程之進行。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與濁飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 6 本紙張尺度適用中國國家檩準（CNS ) A4規格（21〇χ297公瘦）Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 519722 45 5 5tvvf.doc / 002 A7 B7 V. Invention Description (/) / (Please read the precautions on the back before filling this page) 13 0: Resistance _: Layer H0: Metal layer 110: For an embodiment of a metal plug, please refer to FIGS. 1A-1E, which shows a cross-sectional view of a metal plug manufacturing process according to a preferred embodiment of the present invention. Referring to FIG. 1A, the substrate 100 has an insulating layer 110 'and the insulating layer 110 has an opening 120. The material of the insulating layer may be, for example, silicon oxide. A method for forming the insulating layer includes low pressure chemical vapor deposition (LPCVD) using tetraethyl orthosilicate (TEOS, Si (OC2H5) 4) as a gas source. Referring to FIG. 1B, a conformal barrier layer 130 is formed in the opening 120 and above the insulating layer 110. The material of the barrier layer 130 may be, for example, titanium nitride, and a method for forming the barrier layer 130 includes a sputtering method. A metal layer 140 is further formed on the barrier layer 130. The material of the metal layer 140 can be, for example, metal tungsten, and the formation method includes a chemical vapor deposition method using WF6 as a main gas source. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Please refer to Figure 1C to etch back the metal layer 140 to the barrier layer 130 to form a metal plug 150. In this etch-back step, if the material of the metal layer 140 is metal tungsten, SF6 / 02 / Ar plasma can be used for dry etching. Referring to FIG. 1D, the exposed barrier layer 13 is etched back to the insulating layer 110 to reduce the depression of the metal plug 150. In this etch-back step, if the material of the barrier layer 130 is titanium nitride, a C12 / BC13 electric paddle can be used for dry etching. 1 — This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) '· 519722 45 5 5tvvf.doc / 〇〇2 A7 B7 ___ 5. Description of the invention (^) Please refer to Figure 1E, insert metal The plug-150 and the insulating layer no are subjected to a planarization step. The planarization method, for example, can be performed by a chemical mechanical honing method at a slower honing rate to achieve the purpose of flattening the surface of the metal plug 15 and the surrounding insulating layer 110. From the above-mentioned preferred embodiments of the present invention, it is known that because the etching method is used to remove the metal layer and the barrier layer above the surface of the insulating layer, the cost is reduced and the production time is shortened. Then, a planarization method, such as a chemical mechanical honing method, is used to flatten the surface of the metal plug. Therefore, considering both cost and capacity considerations, it can provide a flat surface after the metal plug process, so that the subsequently deposited metal wire layer can have a flatter surface ’to facilitate the lithography process. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy
Claims (1)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW088105505A TW519722B (en) | 1999-04-07 | 1999-04-07 | Method for producing metal plug |
| US09/306,342 US6211067B1 (en) | 1999-04-07 | 1999-05-06 | Method for manufacturing metal plug |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW088105505A TW519722B (en) | 1999-04-07 | 1999-04-07 | Method for producing metal plug |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW519722B true TW519722B (en) | 2003-02-01 |
Family
ID=21640215
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW088105505A TW519722B (en) | 1999-04-07 | 1999-04-07 | Method for producing metal plug |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6211067B1 (en) |
| TW (1) | TW519722B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6479394B1 (en) * | 2000-05-03 | 2002-11-12 | Maxim Integrated Products, Inc. | Method of low-selective etching of dissimilar materials having interfaces at non-perpendicular angles to the etch propagation direction |
| WO2005055178A1 (en) * | 2003-12-02 | 2005-06-16 | Semiconductor Energy Laboratory Co., Ltd. | Display device, method for manufacturing the same, and television apparatus |
| US20050233563A1 (en) * | 2004-04-15 | 2005-10-20 | Texas Instruments Incorporated | Recess reduction for leakage improvement in high density capacitors |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5164330A (en) * | 1991-04-17 | 1992-11-17 | Intel Corporation | Etchback process for tungsten utilizing a NF3/AR chemistry |
| JP3318813B2 (en) * | 1995-02-13 | 2002-08-26 | ソニー株式会社 | Multi-layer wiring formation method |
| US5942449A (en) * | 1996-08-28 | 1999-08-24 | Micron Technology, Inc. | Method for removing an upper layer of material from a semiconductor wafer |
| US6140224A (en) * | 1999-04-19 | 2000-10-31 | Worldiwide Semiconductor Manufacturing Corporation | Method of forming a tungsten plug |
-
1999
- 1999-04-07 TW TW088105505A patent/TW519722B/en not_active IP Right Cessation
- 1999-05-06 US US09/306,342 patent/US6211067B1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US6211067B1 (en) | 2001-04-03 |
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