TW517338B - Method to form semiconductor device contact and method to form Ohmic contact on the same - Google Patents

Abstract

A method to form semiconductor device contact and method to form Ohmic contact on the same are disclosed, mainly pointing to forming the contact on the semiconductor substrate on which memory cell array area and peripheral circuit area are defined. Employ the self-aligned contact (SAC) etching to form the contact to bit-line (CB) of the memory array area and contact to substrate (CS) of the peripheral circuit area and then form the contact to gate (CG) of the peripheral circuit area. The above-mentioned method also comprises the low energy and high dosage plasma doping to the CS and CB contacts. According to this method, problems such as the contact misalignment induced short and short channel effect (SCE) and punch-through among the source/drain and contact can be prevented. Ohmic contact is achieved via low energy and high dosage plasma doping, so that a stable product is acquired and yield is elevated.

Description

517338 、 Invention description (l) μ i: Japan: ‚About semiconductor process technology, especially about-contact method of device contact window of i = method, and formation of ohmic connection to Tinan integrated circuit in these contact windows Packaging density and continuous efforts to reduce wafer size Alignment errors between different pattern layers are the main obstacles. Therefore, many self_aligned processes have been developed to reduce the distance between components and increase the Intensity.

In order to further understand the background of the present invention, the following is a description of the requirements for contacting and washing the mouth with the help of Figure 1. In FIG. 1, on a semiconductor substrate 1G having a plurality of closed pole structures, it is divided into a memory cell array (A array) and a peripheral circuit area s (SUpport). An oxide layer, a nitride layer, and a BpsG layer are sequentially formed on the semiconductor substrate. The gate junction is composed of a silicon nitride layer 15, a tungsten silicide layer 16, and a polycrystalline silicon layer 丨 7: and an etching stop layer 8 is formed on the silicon nitride layer 15, and a sidewall A spacer wall 4 is formed on the upper surface. In the above structure, a bit line contact window (CB) 30 must be formed on the memory cell array area A to connect the source / drain area / bit line of the transistor, and the peripheral circuit area S has a Shi Xi substrate. The contact window (^^) 32 and the gate contact window (CG) 31.

Traditionally, the Diaolong process using deep trench (DT — based), when forming the contact window, the silicon substrate contact window (cs) and the bit line contact window (cb) are separated separately, and are also located in the peripheral circuit area. The silicon substrate contact window (cs) is used, and the gate contact window (CG) is performed simultaneously. In addition, different filling materials (multicrystal stone is used in the array area, and the peripheral circuit area uses M i), and the contact method is different (CB uses diffusion contact, and cs uses implant contact

517338 V. Description of the invention (2)) It is also used in the above process. However, 'design guidelines (design oil) for DRAM devices in SUb-150 / ^ m, low-resistance materials must be used in the contact window', especially those with deep trenches as storage nodes_node, so they use complex crystals. Silicon is no longer suitable for bit line contact window (CB) materials. It is easy to affect the whole process because it is difficult to control the weight between the CG and the gate contact window (CG). The window (pr0cess) will cause problems such as short circuit, increased junction leakage (junctioon drain saturation current uDsat), and other problems. up) Quantities :: Planting = process 1 to form a contact window ... All are implanted with high energy, high dose, abundant Γ (plantation), and then fast supply :, RTP) tempering. However, the c in the above process is wrong. The problem 'will cause the contact implantation (eQntaet sundial to produce defects such as the button channel effect / penetration, and then reduce = Feng: rate. Therefore, a semiconductor device with good function must be' i: 7 h joint surface formation A shallow and low-resistance ohmic contact (〇hmic contact) allows current to flow. 坶 Summary of the invention: The square η :: The main purpose of this month is to provide a yield rate for the formation of the contact window contact area and the target process. At the same time, it can provide a larger connection area, and has better process stability. Another purpose of the post-rolling process is to provide a semiconductor process that forms an ohmic contact in the formation of a fixed 4 μ contact window. Traditional The manufacturing process is on page 6: 5993-6266TWF; 90007; Phoebe.ptd 517338 V. Description of the invention (3) ΐ = doping with heteropole / domain using electric mass doping ', but according to the method of the present invention, shallow: low thunder :, Low energy, high dose The method of the present invention can be applied to a metal contact or a metal silicide contact outside the shallow junction area where the contact window forms a deep ohmic contact. The method is: 'The present invention provides a product for forming a memory contact window. ΞΠ self-reshaping-

The process. According to the present invention; first: cattle; multiple gate junctions with CG walls and stagnation layers; 2; =; = semiconducting of gap region and peripheral circuit region; meaning a redundant memory cell array structure and the semiconductor substrate Top ;: Carve the oxygen :: Oxygen: Layers in the gate circuit areas, forming gates in the memory cell array area and the peripheral CCS) (CB) peripheral circuit areas, respectively, and etching The oxide layer is formed by a gate structure (CG) in the circuit area, and exposes the peripheral electrode. The CB and CS are also contacted. Including: after the CB is formed and the contact window is formed (1) Doping) The low-energy and high-dose plasma doping is performed after the above steps are completed. Metal, polycrystalline stone or metal stone ^ ^ system is developed into plugs, such as tungsten and other gate structures such as Feng Mo used in the present invention is a ^ body substrate has a plurality of gate structures, where , Shi Xihua: two and nitrogen cut layers. For other conductive metals, such as titanium. Bit 0953-6266TWF; 90007; Phoebe · ptd Page 7 517338 V. Description of the invention (4) Any low-k dielectric around the interrogation structure "The etch stop layer and the spacer can be used for any subsequent formation; ^ / iteGtrie material) 'For example. It is selected from, for example, a dibasic substrate and an optional oxide layer on the interpolar structure. The interelectrode contact window (CG) is 1 worm, and the high selection of wsi is suitable :: DRAM device In addition, the method for forming a contact window of the present invention is also a ferritic or magnetic random access memory (FeRAM or ... people. 1 ηκ V, plasma doping used in the present invention is low energy, preferably 100eV ~ 2e ^ range, and high doses, preferably in the range of 1E14 ~ 1E16 As + or P + / CI " to ensure the formation of shallow junctions of appropriate thickness. ^ According to the method of forming a memory contact window, It can avoid the product quality degradation caused by the misalignment of the ® mouth. In addition, the method of the present invention uses the same two masks as the existing process and can be immediately applied to the production line without increasing the complexity of the process. New mask design An additional (non-cricital MUV) as mask so that the above objects, features and advantages of the present invention more apparent hereinafter Laid include preferred embodiments and illustrated with the following, detailed description is as follows:

The drawing briefly illustrates a cross-sectional view of the port. Methods for Forming a Contact Window FIG. 1 is a cross-sectional view showing a contact window of a general DRAM device. FIGS. 2 to 5 are cross-sectional views showing a process of an embodiment of the present invention. Figures 6 to 7 show a towel according to an embodiment of the present invention.

517338

Cross-sectional view of the process of making contact [Symbol description] S ~ peripheral circuit area; 11 ~ oxide layer; 1 ~ 3 oxide layer; 15 ~ silicon nitride layer; 17 ~ polycrystalline silicon layer; 3 ~ bit line contact Window 3 2 ~ Shi Xi substrate contact window

A ~ array area; 10 ~ semiconductor substrate; 12 ~ nitride layer; 14 ~ spacer wall; 16 ~ petite tungsten layer; 18 ~ etch stop layer; 31 ~ gate contact window; 40 ~ ohm contact . Embodiments Please refer to Figs. 2 to 6, which show a method of forming a contact window on a semi-conductive substrate in an embodiment of the present invention. First, as shown in FIG. 2, the semiconductor substrate defines a memory cell array region A and a peripheral circuit region $. An oxide layer is sequentially formed on the semiconductor substrate 10 according to a conventional process technology. The nitride layer 12 and a plurality of inter-electrode structures g 1 ′ are respectively formed by a nitride stone layer 15 and a stone layer. It consists of chemical crane 16 and polycrystalline stone layer 17. The etch stop layer 18 and the spacer 14 are further formed with si3N4, which can usually be obtained by low pressure chemical vapor deposition (LPCVD) deposition. Next, as shown in FIG. 3, the semiconductor substrate 10 and the gate structures G1 are completely covered in order to form an insulating material, such as an oxide layer 13. As shown in FIG. 4, the area of the bit line contact window (CB) 30 and the silicon substrate contact window (CS) 32 are defined by a general lithography process, and the contact windows 3 are etched by automatic alignment contact (SAC) 3 0, 3 2 area removed to expose separately

0593-6266TWF; 90007; Phoebe.p t d p.9 517338 V. Description of the invention (6) Semiconductor substrate 10. Then, as shown in FIG. 5, the same is used for the gate contact window (cG) 31 area, and then the contact is removed to expose the tungsten silicide layer 16 in the gate structure. Via the 231 & domain, the memory contact window shown in Figure 1 It can be obtained from the escape step that another embodiment of the present invention is that after forming the bit line contact window 30 rCB) and the Shi Xi substrate contact 胄 32 (cs), that is, doping with plasma or Impulse ion implantation is not easy (Plasma I_rsion Ion Implanati), for example, pLAD / p⑴ ', 25: 10 ^ C low temperature, low energy (100OOVMOKeV), high dose (1E14 16 / cm), power factor ( duty fact (factor) 〇 ~ 10% conditions The bit line contact window 30 (CB) and the silicon substrate contact window 32 (cs) are doped with plasma to form an ohmic contact 40. In addition, doped materials such as bf, AsH3, PH3, B10HX, N2, Ar, etc. can be implanted at the same time to reduce activation energy and achieve the effect of suppressing ion diffusion too deeply. First, in the present embodiment, after forming the above ohmic contact, a gate contact window (C (J) 3) may be formed in the same manner as described in FIG. 7 to expose the silicide layer 16 in the gate structure. Figure 7 is a cross-sectional view showing the formation of an ohmic contact in a contact window according to this embodiment. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in the art, Without departing from the spirit of the present invention, some modifications and retouching can be made. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

Claims (1)

517338 VI. Patent application scope Memory 1 cell array method 'Applicable to the definition of a step-by-side circuit & + conductor substrate' includes the following steps: semiconductor bottom, f-thickness: wall and multiple gates of etch stop layer The structure is on the memory cell array area and peripheral circuit area of the present + V body; An emulsified layer is formed at the gate to form the gate structure and the half-etched oxide layer, and the gate is covered by the gates to cover the ground at the year ^ π j, The structural spacer is used as the etching Ψ α;-. In the dagger, the area and the peripheral circuit area, the same day Fengba 2 丨 formed a line contact window (CB) and silicon semiconductor substrate; and anti-contact (CS) and exposed the money and the gasification Layer in order to form a closed electrode contact window in the periphery (cg), and five-way gates located in the peripheral circuit area. 2 · Structure as described in item 丨 of the application scope . ㈣ ,,, and "冓 疋 are composed of a polycrystalline silicon layer, a silicon layer, and a silicon layer. 7 7 The grape layer and the siliconized silicon layer 3. As described in the first item of the patent application scope, the metal layer located on the gate structure is exposed. The following steps in the method # are used to determine: 方法 The method of forming an ohmic contact by the contact window of the memory device, which includes the following steps: A dry-waiting basket, including a semiconducting wall, a plurality of gaps and a silver stop layer. The electrode structure is on the memory cell array area and the peripheral circuit area of the conductor substrate; and a semiconductor layer is formed on the gate structure and the semiconductor substrate; the oxide layer is etched, and a spacer wall of the gate structure is used. As the remainder m, page 11 0593-6266TW; 90007; Phoebe.ptd 517338 VI. Patent application mask, in order to form a bit 70 line contact in the edge memory cell array area and the peripheral circuit area at the same time. Window (CB) and silicon substrate contact window (3) and expose the semiconductor substrate; plasma doping is performed on the surfaces of the CS and CB contact windows; and the oxide layer is etched to form a gate in the peripheral circuit area Pole contact window (CG) 'and exposed at the periphery Gate structure in the road area 5. The method according to item 1 of the patent application scope, wherein the plurality of gate structures are composed of a polycrystalline silicon layer, a tungsten silicide / metal layer, and a silicon nitride layer. 6. The method as described in item 1 of Shen Qing's patent scope, wherein the last step is to expose the metal layer located on the gate structure. 7. The method as described in item 4 of the scope of patent application, wherein the plasma is doped in the last step. Miscellaneous is performed with low energy and high dose. 8 · The method described in item 7 of the scope of patent application, where low energy refers to 100eV ~ lOKeV As +, and high dose is within the range of 1E14 ~ 1E16AS + or P + / era2. 9 · The method described in item 4 of the scope of patent application, wherein the plasma doping is performed at a low temperature of 25 ~ 100 ° C. I 0 · The method described in item 4 of the scope of patent application 'where electricity The power factor of the plasma doping is between 1 and 10%. II. The method described in item 4 of the patent application range, wherein the plasma-doped ions are selected from the group consisting of BF2, AsH3, PH3, N2, and Ar. Iso-doped ions.