TWI231010B - Mixed signal embedded mask ROM with virtual ground array and method for manufacturing same - Google Patents

Abstract

A mixed signal integrated circuit including an embedded ROM array is manufactured using a two polysilicon process, with small critical dimensions. A first layer of polysilicon covered with a dielectric, adapted for formation of transistor gates and capacitor bottom electrodes, is formed in a non-array portion of the substrate. A second layer of polysilicon, adapted for formation of word lines in the array portion of the substrate, and the capacitor top electrodes, is formed over the dielectric layer. The second layer of polysilicon is patterned to define word lines in the array portion and the capacitor top electrodes. Next, the array portion and the capacitor top electrodes are protected, and the first layer of polysilicon is patterned, to define transistor gates and the capacitor bottom electrodes. Salicide processing is applied to the non-array portion of the integrated circuit.

Description

1231010 _ Case No. 9210J832 _ Amendment _ V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to an integrated circuit element and a manufacturing method thereof for advanced mixed signal applications, and in particular Related to a mixed signal integrated circuit with embedded memory array. [Previous technology] The application of integrated circuit technology has developed to the point where analog and digital components can be integrated on a single chip. For example, a mixed signal device with a memory array, logic circuits, and capacitors has been developed. devices). In U.S. Patent No. 6,440,798B1, Lai et al. Disclosed a mixed signal consisting of an embedded mask ROM, a nitride read-only memory (NR0M), and a capacitor. Circuit. When the size of integrated circuit components is reduced, the design of integrated circuit for mixed-signal components becomes more complicated. For example, in the small-sized transistor, the automatic alignment metal silicide (sa 1 pesticide) process needs to be applied to It is possible to form a conductive metal silicide on the surface of the source / non-electrode of the peripheral circuit to improve the conductivity. However, for a memory array that requires automatic alignment of the sa 1icide process and a circuit capable of processing mixed signals, the following difficulties arise: Since the array part of the integrated circuit must be protected, the array part and the The metal alignment process is automatically aligned to form isolation, so the metal silicide is not formed in the space between the word lines. For example, the metal stone in the word line space will produce a leaking channel in the ground ROM of the flat ROM, so it has a mixed signal element.

TW0735 (041202) CRFl.ptc Page 7 1231010 j No. 92107832 Λ_η V. Description of the Invention (2)-The embedded memory is not practical for integrated circuits, for example], Zhiming, ζ ο inn or more See the integrated circuit in the small line. Therefore, it is necessary to provide a mixed-signal integrated circuit and a manufacturing process of the integrated circuit. Among them, the mixed-signal integrated circuit is a micro-line-width memory array, peripheral circuits, and capacitors. [Invented the method, and provided in the small, it is excellent to provide a silicide based on the mixed signal a polycrystalline stone is used to form on the capacitor area, its system pole; pattern electrode; a polycrystalline stone capacity] Ming Provided is the purpose of overcoming the line width system of small wires of the integrated electrical layer system of the present invention to form a second covering layer to shape the second adhesive layer. The polysilicon protection array formed on the gate and the dielectric substrate defines the high-performance hybrid signal element self-aligned metal silicide used in the manufacture of embedded read-only memory for mixed-signal components. The joint signal component has self-aligned gold, a capacitor lower electrode using a two-multibody circuit including an embedded read-only process to manufacture a non-array area crystalline silicon plate, and a first polycrystalline silicon layer; More than two inches; the word of the array area of the flow circuit according to the present invention is applied to the array area layer of the non-array of the integrated circuit to define the column area and the crystal gate, and the metal element line space is the column area. When the crystalline silicon layer forms the word line of the domain and the capacitor upper electrode of the electric array region, and the silicide of the capacitor lower electrode is formed, the self-aligned metal is memorized as: upper, layer is on the dielectric upper line and pattern One of the externally isolated silicides is at least the electrical layer capacitance of the capacitor. This is the date and time t 3-The purpose is to provide a mixed signal integrated circuit, i

TW0735 (041202) CRFl.ptc 1231010 Case No. 921078 ^ Year 5. Description of the invention (3) Includes a read-only memory, a polycrystalline silicon-insulator-polycrystalline silicon, a metal silicide in the source / drain region of the substrate Electricity

The peripheral and another embodiment of the present invention include a peripheral circuit and a hot circuit. A read-only memory array with a line width of 0. 25um or less. Lithography Process Forming According to a specific embodiment of the present invention, a shoe-making square is provided to form a shallow trench isolation structure on the substrate; the steps are as follows: Lit> forming a gate oxide layer on a non-array area of the substrate. Covering a first polycrystalline silicon layer on the non-array region structure // 磙 isolation junction with a capacitor dielectric layer on the first array plate region of the isolation structure in the non-array region; Shi Xi layer patterned a plurality of bit line patterns in the array area, and the direction of one bit line was performed; '' was implanted in the substrate doped between the bit line patterns; Removing the bit line patterns; forming a gate oxide layer in the array region; covering a first polycrystalline silicon layer and a metal oxide compound on the first polycrystalline silicon layer and the first On the capacitor region and on the array region "; patterning a plurality of word lines in the array region and an upper capacitor plate on the first capacitor region, and etching the second polycrystalline silicon layer and the Metal silicide to form a plurality of word lines in the An upper capacitor plate structure is formed in the column region and on the first capacitor plate region; the first polycrystalline silicon layer and the capacitor dielectric layer are patterned to define a plurality of transistor gates in the non-array region and a lower capacitor; Board

TW0735 (041202) CRFl.ptc Page 9 1231010 ____M: 92107832_ year, month, day and five. Description of the invention (4) In the area of the capacitor plate; a self-aligned metal silicide is formed on the drain and source of the non-array area Area; implanted read-only memory data code (rqjj codes) into the barrier array area; implanted a first dopant in the non-array area, which is based on the transistor gates in the non-array area Constructed as a mask;

A plurality of gap walls are formed between the transistor gate structures and the word lines in the array region. This is accomplished by forming a nitride stone. X implantation of a second dopant in the non-array region is performed. The gap is used as a mask; two dielectric layers are overlaid on the array area and the non-array area; a patterned metal layer is overlaid on the dielectric layer. Therefore, the present invention overcomes the difficulty in manufacturing the self-aligned metal silicide of a hybrid signal element with a read memory in the conventional technology. In particular, by using a simple array barrier and a simple and straightforward process, the array region of the substrate is isolated from the self-aligned full-flow watch. Therefore, the embodiment of the integrated circuit of the present invention is provided with bismuth. Reminiscence of small line width mixed signal design. Eight-entry read-only record In order to make the above-mentioned objects, features, and advantages of the present invention understandable, the following is a special embodiment-a preferred embodiment.卞 Bang elaborate [implementation]

1231010 Amendment 92107832

V. Description of the invention (5) The detailed description of the embodiments of the present invention is provided with drawings to facilitate the first 1A to 1B diagrams which are representative of the manufacturing method of the present invention, and the relevant structures in each manufacturing step are described in the first. ^ A mask-type read-only record for mixed signals_ ^ Ύ Eight-read memory is reduced to a memory-mask type is the first step in the process (block 10) is to form a board The isolation structure of the array region 110 and the non-array region U1 is shown in FIG. 2, which shows a cross-sectional view after performing this step. In the embodiment shown in FIG. 2 ”, the array region 1 10 is isolated from the non-array region 丨 i by a dielectric insulation structure 12. For a typical CMOS embodiment of a logic circuit, the non-array The region 111 is divided into an n-channel region and a p-channel region by a dielectric insulating structure 1 1 3. In addition, in this embodiment, an isolation structure 2 is formed in a non-array region 1 11 of a substrate In the capacitor region above, an oxide layer or other dielectric layer is deposited in a trench using a regional stone oxide method (LOC0S) or other conventional techniques, and the dielectric structures 112, 113 and the isolation structure 120 are formed. In a preferred embodiment, the formation of a shallow trench isolation (ST I) structure is the technology disclosed by Huang et al. In the US patent application No. 6,191,0 0 B1, and the invention name is "Shallow Trench Isolation Method Used in Semiconductor Wafers" (SHALLOW TRENCH ISOLATION METHOD USED IN A SEMICONDUCTOR WAFER). In the illustrated embodiment, the isolation structure 120 has a flat surface. The formation of the electrodes under the capacitor is described below. Alternatively, the surface of the isolation structure 120 may also have a shape, which can increase the formation of the isolation structure. The surface of the capacitor electrode on 120. The N-channel area is defined by a P-shaped well 114, of which ‘N-channel

TW0735 (041202) CRF1.ptc Page 11 1231010 __Case No. 92107832_year a_ amendment V. Description of the invention (6) The element system is formed in the P-type well 114, and the P channel area is defined by an N-type well 115 , Wherein a P-channel element is formed in the N-well 115. In this embodiment, the array region 110 includes a deep N-type well 116, wherein a P-type well 117 is formed in the deep N-type well 116 and an N-channel memory element is formed in the p-type well 116. In an embodiment of a process, the formation of a retrograde well is used to create a deep well structure, and

Vt implant implants are provided in the memory cell area. This process includes the formation of two concentration-inverted wells, and the process of formation of the concentration-inverted wells includes the use of the same mask to implant a well—an anti-punch through implant -A voltage threshold is implanted. According to the above-mentioned method for forming a concentration-inverted well, two masks are used in this embodiment to form a deep N-well 116 and a P-well 116. For the manufacture of NMOS devices, the typical implantation parameters are as follows: voltage threshold implantation with energy of 50k ~ 8 OK eV and boron difluoride at a dose of 1012 dose / cm2; energy of 50K ~ 80K eV and dose 1 〇 丨 2 boron implanted at a dose / cm2 of reverse penetration. 'Well implantation was performed at an energy of 150K ~ 250K eV and a dose of 1013 dose / cm2. For the manufacture of PM0S elements, the typical implantation parameters are as follows:

A voltage threshold implantation with an energy of 100K ~ 120K eV and a dose of 2 * 1〇12 dose / cm2; a reverse penetration implantation with an energy of 25 0K ~ 30 0 K eV and a dose of 2 * 1012 dose / cm2 of phosphorus; Wells were implanted with an energy of 5 50K ~ 60 0K eV and a phosphorus dose of 1013 dose / cm2. In some embodiments, the combination of well structures in the array region is used for isolation purposes. In the next step (block u) of FIG. 1A, a sacrificial dielectric layer 118 and a peripheral gate dielectric layer 9 and 9 are respectively formed in the array region and the non-array_array region. As shown. The sacrificial dielectric layer 118 in the array region and

HE

Page 121231010 __ Case No. 9210783g_ Year Month and Day x. V. Description of the invention (7) Peripheral gate dielectric layer in non-array area Different dielectric parameters are established in different process steps. At the same time, the peripheral gate dielectric layer 9 can have different characteristics in different regions to provide various combinations of integrated circuits. Next, a first polycrystalline silicon layer 125 is deposited on the sacrificial dielectric layer 118 and the peripheral gate dielectric layer 119 (block 12). For N-channel Mos devices, dopants are implanted in the first Region 121 of the polycrystalline silicon layer 125 and power down capacitor 1

Extremely, the region 122 (block 13) doped with the first polycrystalline silicon layer 125 is implanted, as shown in FIG. 3.

After the first polycrystalline silicon layer 1 2 5 is prepared, a photomask is used to expose the array region, and the first polycrystalline silicon layer of the array region is removed by an etching process, leaving a non-array region on the substrate. A first polycrystalline silicon layer with a capacitor region. As shown in FIG. 4, the protective dielectric layer 1 2 6 on the non-array region of the substrate is located on the surface of the remaining first polycrystalline silicon layer and the sidewall of the first polycrystalline silicon layer around the array region. Up (block 14). In this embodiment, the protective dielectric layer 126 includes a thermal oxide layer having a thickness of about 30 angstroms. Other materials can also be applied here as a protective layer or a capacitor dielectric layer. The combination of the remaining first polycrystalline silicon layer 125 and the protective dielectric layer 126 can be used as a mask when defining a memory array step. In the next step, the lithography process and subsequent ion implantation and photoresist stripping processes are used to form buried diffusion bit lines (buried diffusion biUines). In one embodiment, the line width of the bit lines is defined by a lithography process, and the size is about 0.25 μm or less. The generated bit lines include diffusion lines 13 and 13, which are parallel to each other and extend in the direction of the normal of the paper plane.

13 Page 13 1231010 Amendment No. 92107832 V. Description of the Invention (8), 15), as shown in Figure 4. The first example of the parameters of implantation for buried diffusion is the doping energy of 15K ~ 40K eV and the concentration of 5 * 103 at 0m / cm2 di-P boron. Prior to this, 1 was subjected to a typical buried diffusion implantation, the second of which is; arsenic of 2 ~ 3.5 * 1015 atom / cm2 and the incorporation of 30K ~ 60K eV: plutonium. Of course, the energy and concentration of all implantation processes are adjusted according to the specific film structure and the specific clean room process. Next, the sacrificial dielectric layer 1 1 8 in the array region is removed, and a gate dielectric layer (for example, in an oxide column region for isolation (block 16 in FIG. 1A) is formed in order to bury the diffusion potential lines in the array region. ^ When the bit lines 130 and 131 of the array and the gate dielectric layer 135 are completed, a second polycrystalline silicon layer 136 is deposited on the first polycrystalline silicon layer 125 and the protective layer 126 of the substrate, as in the fifth example. As shown in the figure, in one embodiment, the second polycrystalline silicon reed 1 36 is formed by chemical vapor deposition. In a preferred embodiment, a tungsten silicide layer 1 37 is deposited on the second poly On the crystalline silicon layer 丨 36, hafnium oxide 138 is formed by chemical vapor deposition on a thickness of about 300˜500 Å (block m. This second polycrystalline silicon layer 136 and The Shi Xihua tungsten layer is compounded, which means the upper electrode of the capacitance of the n line and the capacitance area in the above-mentioned array area. 'A-continue down-step' is to define the word line 145 by using the photolithography process. The upper valley electrode 146 ′ and the second polycrystalline stone layer 136 and the Shixihua town layer 丄 and

It is etched until the protective layer 126 (block 18), as I in FIG. 6… in the non-array area 148 and the capacitor area _______-.-一 _Ι · · 1ΙΜ — 一 ---- & quot Face

TW0735 (041202) CRF1.ptc Page 14 The line width of line U5 is determined during the lithography process. In some implementations, the line width may be 0.25um or less. Carry out different steps, its cost, 1231010

The electrode 149, at this time, the word line protects the array area, and during the etching, it is etched down to the gate dielectric layer 119 (the block is shown in FIG. 7 of the non-array area. One of the peripheral circuits) The line width of the gate junction of the transistor or more is defined during the lithography process. In some embodiments, the line width can be 0.2um or less. Then, the photoresist is removed and the non-array is continued. Region M region CMOS processes, including self-aligned metal silicide processes. Typical CMOS processes include a re-oxidation process and a lightly doped drain (1 丨 8) 11:17 doped after the re-oxidation process. drain (LDD) process, the lightly doped drain process uses the gate structure 14 '148 as a mask, and

The first implantation step in the array area begins. Refer to Figure 8 for a cross-section view parallel to the character line. After the first implantation step, a diffusion region 15 5 and a diffusion region 15 5 aligned with the sides of the gate structure 14 7 are generated. Then, a silicon nitride layer and Isotropic etching to the structure under the nitrided layer forms a silicon nitride spacer 157 ,. The parameters of an embodiment for depositing silicon nitride include a h / N ^ / SiHJl2 mixed gas in chemical vapor deposition and a temperature of 73 ° π in the reaction chamber. In: In the implementation process, the etching of silicon nitride uses a dry etching process, for example: 75mt / 16 0 0W / C4F8 / Ar / CH3F, where mt represents l * i〇-H〇rr,

W stands for Watt 'and its etch endpoint is set to stop on the silicon dioxide gate dielectric. As shown in FIG. 8, the structure of the spacer on the substrate is generated in this remaining step, for example: 157 and 158 (block 20). The lightly doped drain process in the non-array region is completed in the second implantation step, which uses the spacers 157 and 158 as a mask. As shown in FIG. 8, this step generates an alignment with the spacers 157 and 158. And there are diffusion regions 169, 160 'spaced apart from the gate structure 147, and the diffusion regions 169, 160 and the diffusion regions 155, 156 are partially

Page 15 1231010

overlapping. In this embodiment, the spacers 157 and 158 are formed of silicon nitride. If a dielectric layer is provided on the surface of the substrate under the silicon nitride, the silicon nitride can improve the etch back of the spacers (etch back). ) Selectivity during etching. Other materials that have a relative etching selectivity for the gate dielectric material can also be used as the constituent material of the spacer. The next step is to apply a self-aligned metal silicide process. As shown in FIG. 8, the self-aligned metal silicide process is performed in a non-array region to form a first alignment with the spacers 157 and 158. The conductive metal silicide 159 is on the exposed diffusion region and on the gate structure. In an embodiment for forming a metal silicide, the diffusion bit lines in the array region use a column mask to avoid the self-aligned metal silicide process. For example, during the etch-back process of the self-quasi-metal silicide process, an array mask is used in the array region to avoid the formation of a spacer wall in the array region of the element, so as to leave a silicon nitride layer and prevent the metal silicide from Between character lines. Another method is to form a partition that can fill the space between the character lines after the silicon nitride is deposited, and protect the space between the character lines to avoid the process of self-aligned metal lithotripsy. There is another method, which is to deposit a CVD oxide layer between the word lines before patterning the first polycrystalline silicon layer to avoid damage to the array area due to the CMOS process of the non-array area. After the self-aligned metal silicide process, a read-only memory data code (ROM code) was implanted in the array region of the device (block 21), which includes the following steps: n patterning photoresist layer, ion implantation Human and photoresistance HV0735 (041202 ^ CRF1, page 16 1231010-case number-Yila 107832, date and time _ face five, description of the invention (11) " wire and package to form a flat memory (F lat R0M) integrated circuit (block 23). Figure 8 shows a integrated circuit with a mask read-only memory in its array area and peripheral circuits in its non-array area 111. A cross-sectional view of the 'array area 110 is arranged in a flat virtual ground structure, and the non-j train line domain 111 has logic and analog transistors formed using a CMOS process. At the same time, polycrystalline silicon-insulating layer-polycrystalline silicon (PIP ) Capacitance system: 'wherein' the isolation structure 1 2 0 above the isolation structure 120 is to avoid the generation of parasitic capacitance of the substrate. The PIP capacitor includes a lower electrode 149 formed by using the first polycrystalline silicon layer i. A second polycrystalline layer In the manufacturing process of an embodiment, the upper electrode 146 is about 4Um2, so the capacitance of the upper electrode makes the application of typical mixed signals possible. Of course, for the application of special signals, it is smaller or larger. The upper electrode of the size can also be implemented in the present invention. In addition, the 'edge of the lower electrode 1 4 9' is preferably separated from the edge of the active area along the side of the isolation structure 1 20 by about 1 um. Fig. 9 shows it The integrated circuit is parallel to the cross-sectional view of the buried diffusion bit line 13 (), and is relative to the process step of FIG. 8, wherein the word line structures 150 and 151 are arranged perpendicular to the bit line. In this embodiment, The space 170 'between the word lines is filled by the above-mentioned silicon nitride spacer process. In the self-aligned metal silicide process, the dielectric layer 1 3 6 is prevented from forming metal silicide. If the manufacturing process of the integrated circuit is reduced to less than 0.25um, the conductivity of the metal is 'located on the source / drain region of the peripheral circuit and the deposit of the metal oxide on the gate electrode's electrode'. Become more critical. Ticks, and know-how The method of self-aligned metal process Shi Tokyo has incompatible compounds, are straight,

TW0735 (041202) CRFl.ptc 1231010 V. Description of the invention (12) The self-aligned metal silicide process is the most well-known process for forming a gold silicide. The invention overcomes the difficulty of the self-aligned metal silicide process and the operation of a small-sized mixed-signal element can be realized.妙-孰 Although the present invention has been disclosed as above with a preferred embodiment, why are you familiar with this technique #, = 2 The technology of the invention is not limited to this' 任 #. #. ^. Without departing from the spirit and scope of the present invention When applicable: The scope of protection of the invention of the invention shall be subject to the following one.

TW0735 (041202) CRFl.ptc Page 18 1231010 _Case No. 92107832_ Year Month Day Amendment _ Simple Description of Drawings [Simplified Description of Drawings] Figures 1 A and 1 B are drawings of the manufacturing method of an embodiment of the present invention flow chart. Figures 2 to 9 show the structural diagrams of the process embodiment in each step, which are used to form a mixed signal integrated circuit including an embedded photomask read-only memory. [Explanation of figure numbers] 10, 11 > 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 2 2, 2 3: Block 11 0: Array area 11 1: Non-array area 11 2: Dielectric insulation structure 11 3: Dielectric insulation structure 114: P-type well 115: N-type well 11 6: Deep N-type well 117: P-type well 11 8: Sacrificial dielectric layer 11 9: Peripheral gate dielectric Electrical layer 1 2 0 • Isolation structure 121: region 122: region 1 2 5: first polycrystalline silicon layer 1 2 6: protective layer

TW0735 (041202) CRFl.ptc Page 19 1231010 _Case No. 92107832_ Year, month, and day correction diagram brief description 1 3 0: diffusion line 1 3 1: diffusion line 1 3 5: gate oxide layer 1 3 6: second Polycrystalline silicon layer 1 3 7: tungsten silicide layer 1 3 8: oxide layer 1 4 5 ··· character line 1 4 6: capacitor upper electrode 1 4 7: gate structure 1 4 8: gate structure 1 4 9: Lower electrode 1 5 0: word line structure 1 5 1 · word line structure 1 5 5: diffusion region 1 5 6: diffusion region 1 5 7: silicon nitride spacer 1 5 8: silicon nitride spacer 1 5 9: conductive metal silicide 1 6 0: diffusion region 1 6 1: contact hole 1 6 2 · metal layer 1 6 3: dielectric layer 1 6 9: diffusion region 170: space

TW0735 (041202) CRFl.ptc Page 20

Claims (1)

Amendment 1231010 Case No. 92107832 6. Scope of patent application ^ 1 · A method for manufacturing an integrated circuit on a substrate, the method is to form a mask read-only memory (mask) located in an array area on the substrate ROM) and other circuit elements located in a non-array area on the substrate, the method includes: covering a first polycrystalline layer on the non-array area; covering a capacitor dielectric layer at least a first capacitor On the first spar layer in the plate area; the port forms an array area of a plurality of bit lines and a gate dielectric layer on the substrate; and covers the first polycrystalline silicon layer on the first array in the non-array area A crystalline silicon layer, the capacitor dielectric layer, and the array region; forming a plurality of word lines in the array region and forming an upper capacitor plate on the first capacitor plate region using the second polycrystalline silicon Forming a silicon layer; forming a transistor gate and a lower capacitor plate in one of the lower capacitor plate regions, which are completed using the first polycrystalline silicon layer in the non-array region; implanting dopants to form a drain and source Area Domain A in the non-array area; and ^ covering a dielectric layer on the array area and the non-array area, and supporting a patterned metal layer on the dielectric layer. 2. The method according to item 1 of the scope of patent application, further comprising: forming a metal silicide in the drain and source regions of the non-array region of the substrate, which is isolated when the formation of the metal silicide is isolated from the metal silicide. Column area. Surface m Page 21 TW0735 (041202) CRFl.ptc 1231010 a Amendment-Case No. 92107832 ^ η Scope of Patent Application ^ 3. The method described in item 丨 of the scope of patent application forms a metal silicide on the surface The dagger of the array area: 4. The method as described in the item No. of the patent claim, above.植 人 # The quality of the non-array region < the interpolar region is more detailed, including: ' and the polycrystalline silicon layer of the first capacitor plate region on the insulation structure 5. The method as described in the item of the scope of the patent application], and medium. : Forming the source and drain regions in the non-array region. Step: the pre-implantation is more temperament and then oxidizes the oxide layer in the non-array region. 6. The drain and source regions in the non-array region as described in item 1 of the scope of the patent application; ^ 1 straight): f a dopant, which is formed by the transistor gate structure to cover I A plurality of spacers are on the transistor gate structure; and a mask is implanted with a second dopant, which uses the spacers as a mask. The method of claim 1, wherein the step of implanting a dopant to form the drain and source regions in the non-array region includes: implanting a first dopant, which is based on The transistor gate structure is a mask; forming a plurality of gap walls between the transistor gate structure and the word lines in the array region, which are completed by forming a silicon nitride; and implanting a first Two dopants are in the non-array region, which are covered by the spacers. 8. The method as described in item 1 of the scope of patent application, where formed from the pair TWO735 (041202) CRFl.ptc page 22 After the step of correcting the quasi-metallic sulfide and the planting cues into the ROM code in the array region, the method further includes forming a self-aligned metal silicide in the non-array region. in. 9. The method according to item 1 of Shenjing's patent scope, wherein the line widths of the bit lines are about 0.25 um or less. 10. The method as described in the item of the patent scope, wherein the non-array: at least one of the gate structures has a line width of about 0.25um or less, and further includes: = formed metal silicide in The drain and source of the non-array region of the substrate are formed when the formation of the metal silicide is isolated from the array region of the substrate. τ A method for manufacturing an integrated circuit on a substrate, the method is to form a mask-type read-only memory in the Dm, A, and A array on the substrate. (mask ROM) and other 7L pieces including a non-array area located on a substrate, which is located on the substrate μ... The method includes: forming an insulating structure on the substrate; forming a The gate oxide layer is on the non-array area of the substrate: an H cap layer is placed on the non-array area and the insulation structure; a capacitor dielectric layer is placed on the first of the non-array area and the first capacitor of the insulation structure On the plate area; said patterning a plurality of bit line patterns in the array area in the direction of the straight bit lines; eight implants doped in the substrate between the bit line patterns; removing the Bit line pattern n 1231010 Modified MM 921078 ^ 6. The scope of the patent application forms a gate oxide layer in the array area; Rong Ji ΐ 7 second polycrystalline silicon layer on the first polycrystalline silicon layer and the electrical layer, and On the array area; patterning a plurality of word lines on the array area plate area, and engraving the second ... layer, a six, and a in the array area and forming an upper capacitor plate structure on the first valley area; ; Patterning the first polycrystalline silicon layer and the capacitor dielectric layer to define a plurality of transistor gates in the non-catfish do pa +, ― i i Φ a 1 in the non-array region, sub-define the capacitor Plate in the lower plate area; implant dopants to form a drain and source area in the non-array area; cover a dielectric layer on the array area and the non-array area; cover a patterned metal Layer on the dielectric layer. 12. The method as described in item 11 of the scope of patent application, further comprising: forming a metal silicide in the drain and electrode regions of the non-array region of the substrate, which is isolated when the formation of the metal silicide is isolated from the metal silicide. It is implemented in the area of the substrate. 13. The method as described in item 11 of the scope of patent application, further comprising: forming a metal > compound on the character line of the array region. 14. The method according to item 11 of the scope of patent application, further comprising: implanting a first polycrystalline silicon layer doped in a gate region of the non-array region, and a first capacitor on the insulating structure Plate area. 1 5 · The method described in item 丨 丨 of the scope of patent application 1231010 ----- mirror 92in7? M _ car a 1 n ^ 1 ^ a Six, the scope of the patent application to form the source and drain regions before the step of the non-array region 'more. Including: reoxidize the oxide layer in the non-array region. Chop 16 · The method as described in item 11 of the patent application range, wherein the step of implanting and pushing to form the drain and source regions in the non-array region further includes: implanting a first dopant Forming a plurality of spacers on the transistor gate structure; and implanting a second dopant using the spacers as a mask. 1 7 · The method as described in item 1 of the patent application scope, wherein the implanting of the substrate to form the drain and source regions in the non-array region is further included: implanting a first dopant , Which is formed by using the transistor gate structures as a mask; forming a plurality of gaps between the transistor gate structures and the word lines in the array region, which is completed by forming a silicon nitride; And implanting a second dopant in the non-array region, which is covered by the spacers. 1 8. The method as described in item 11 of the scope of patent application, after the step of forming the self-aligned metal lithotripsy and the implanted read-only memory data code (R0M codes) in the array region, further comprising : Forming a self-aligned metal silicide in the non-array region. 19 · The method as described in item 11 of the scope of patent application, wherein these bits TW0735 (041202) CRFl.ptc Page 25 1231010-Case No. 921078 along _year month I 倐 正 __ VI. Scope of patent application The line width of the yuan line is about 0.25um or less. 2 0. The method as described in item 丨 丨 of the patent application scope, wherein at least one of the gate structures has a line width of about 0.25um or less, and further includes: forming a metal silicide on the The drain and source regions of the non-array region of the substrate are implemented when the formation of the metal chopper is isolated from the array region of the substrate. 21 · —A method of manufacturing an integrated circuit on a substrate, the method is to form a mask ROM on an array region on the substrate, and includes a non- Array region two other circuit elements, the method includes: forming a shallow trench isolation structure on the substrate; forming a gate electrode layer on a non-array region of the substrate: covering a first polycrystalline silicon layer on the non-array Area and the isolation structure; covering a capacitive dielectric layer on the first polycrystalline silicon screen of the non-array area and on the first capacitor plate area on the isolation structure; S-bit: d ;: bit line pattern on the In the array region, it is implanted into the substrate doped between the bit line patterns; removing the bit line patterns; forming a gate oxide layer in the array region; covering a second The polycrystalline silicon layer is a polycrystalline silicon layer. The metal silicide is deposited on the first valley plate area and the array area; patterning a plurality of sub-element lines in the array area and Capacitor board TW0735 (041202) CRFl.ptc Page 26 1231010 Case No. 92107832 6. The scope of the patent application is on the area of the -capacitor plate, and the second silicide is engraved to form a plurality of characters. On the day, it is necessary to prepare Fanfan green in the array region and form an upper thunder capacitor plate structure on the first capacitor plate region; the first polycrystalline silicon layer and the capacitor dielectric layer are defined to define A plurality of transistors are located in the non-array region, and in the lower capacitor region, at least-the M & valley valley is at 025 center or less; the line width of the interpole structures is approximately formed -Self-aligned metal lithotripsy is implanted in the non-barrier column region of the non-barrier region and the source region, and read-only memory data codes (ROM codes) are implanted in the array region; ^ implanted-the first-doped in the non-barrier region In the array region, the transistor gates of the region are used as a mask; early N forms a plurality of gaps between the z-lines of the fish regions on the transistor gate structures. The nitride m ... array is implanted with a second dopant in the non-array region, which A wall is used as a mask; a gap covers a dielectric layer on the array region and the non-array region; and a patterned metal layer is covered on the dielectric layer. 22 · The method according to item 2 丨 of the patent application scope, further comprising: · implanting a first polycrystalline silicon doped in the gate region of the non-array region in the middle layer and a first capacitor plate region on the isolation structure No.-Polycrystalline. 23. The method as described in item 21 of the patent scope of the invention ^ 1 Page 27 TW0735 (041202) CRFl.ptc 1231010 Before forming the source region and the drain region in the non-array region, the method further includes oxidizing the oxide layer in the non-array region. 24 · —A kind of integrated circuit including at least: a semiconductor substrate; a previous read-only memory array unit cell located on the semiconductor substrate; a peripheral circuit coupled to the array and located on the periphery of the semiconductor substrate The circuit includes a plurality of metal oxides on the source and drain regions of a transistor having a source and an electrode region, wherein the source and electrode regions are located in the semiconductor substrate; and a capacitor is disposed in the On a semiconductor substrate. 25. The integrated circuit as described in item 24 of the scope of patent application, wherein the capacitor further includes a polycrystalline silicon-insulator-polycrystalline silicon device. 2 6 · The integrated circuit as described in item 24 of the patent application, and the array includes a plurality of character lines with polycrystalline silicon, and includes a polycrystalline silicon upper plate and a polycrystalline silicon Under the board. "Daggers 27. The integrated circuit described in item 24 of the scope of the patent application, which has a transistor with a closed electrode, and the transistor is between two polycrystalline stones, the array includes a plurality of The word it line of the second polycrystalline stone, i the capacitor includes-having the upper plate of the second polycrystalline chip ^ one having the lower plate of the first polycrystalline silicon. 28. As described in item 24 of the scope of patent application Integrated circuit, so that the read-only memory includes at least a mask-type read-only memory. TW0735 (041202) CRFl.ptc Page 28 1231010 _ Case No. 92107832_ Year Month Amendment _ 6. Scope of Patent Application Silicon nitride spacers are on the transistors of the peripheral circuit. 30. The integrated circuit as described in item 24 of the scope of patent application, wherein the capacitor includes at least a polycrystalline silicon-insulator-polycrystalline silicon device in a shallow trench isolation structure. 31. The integrated circuit as described in item 24 of the scope of patent application, wherein the peripheral circuit has a plurality of transistor gate transistors, and a line width of at least one of the transistor gates is about 0.25 um Or smaller. TW0735 (041202) CRFl.ptc Page 29