TW514993B - Method for making GaN MOSFET - Google Patents

Abstract

The present invention relates to a method for producing a GaN MOSFET. A liquid phase deposition method is used to deposit an oxide layer on a GaN semiconductor. The oxidation system is rather effective and cheap. It only requires to insert a GaN chip in a mixture solution of hexafluorosilicic acid and boric acid in room temperature and an atmospheric pressure to form a silicon oxide layer. This deposition method will deposit the oxide layer on the chip without depositing on metal. Meanwhile, the property where a PEC wet etching does not etch SiO2 facilitates the use of silicon dioxide as a mask in platform etching. During the process, a rapid thermal annealing is used as a necessary thermal treatment to improve the quality of the oxide layer.

Description

514993

_—Case No. 901 Test 4 V. Description of the Invention (1) [Field of Invention] [Background of the Invention]

The present invention relates to a gallium nitride gold-oxygen half method, and more particularly to an oxygen semiconductor using a liquid-phase deposition at room temperature. '' Loyal

The field-effect transistor manufacturer has deposited an oxide layer in the past few decades. Field-effect transistor (Field Ef Transistor, FET) has been developed in the semiconducting region α & Integrated Circuit (VLSI): Even the technology of == makes it the most important in the field of: =: Sophomore Integrated Circuit (ULSI Xuan inserted wire Ertian ^ Xidi 0 FET design There is a big difference. The difference between the gate and the channel is the difference between the two structures: for the fabrication of integrated circuits made of materials, metal oxide (MOS) junctions, transistors (MOS transistors) ) In addition to the above-mentioned FET, it also has high yield and good reliability, making it one of the most widely used components in recent years, but it is limited by the inherent lack of silicon materials. It is applied to the high-frequency, high-power stone that has been hindered and developed, and has been transferred to the Dish-V group of materials, with gallium arsenide (GaAs) == the most, followed by gallium nitride (GaN). Among them Gallium nitride (GaN) is a high-battery semiconductor material that is suitable for high-power elements. Good heat transfer rate and thermal stability under high temperature operation, there is no overheating problem when applied to high-power components. The following will explain the previous technology in two parts: [• Oxide layer: currently used for transistor oxidation Layer manufacturing methods include chemical vapor " CVD (CVD), sputtering, electron beam (E-Beam) and the present invention.

514993 _Case No. 90119434_ Year, Month, Date, Amendment _ V. Description of the invention (2) The low temperature (about 40 ° C) liquid phase deposition (LPD) silicon oxide layer (Si 1 icon oxide) used. CVD-deposited silicon oxide is known (refer to " AlGaN / GaN Metal Oxide Semiconductor Heterostructure Field Effect Transistor " M. Asif Khan, X. Hu, G. Sumin, A. Lunev, J. Yang, R. Gaska, MS Shur , Fellow. IEEE Electron Device Letters, volume 21, NO. 2, February 200 0, Page (s) 63-65) and E-Beam deposited gallium oxide (refer to `` GaN metal oxide semiconductor field effect transistors " F. Ren, SJ Pearton, CR Abernathy, A. Baca, P. Cheng, RJ Shul, SNG Chu, M. Hong, MJ Schurman, JR Lothian. Solid-State Electronics volumn 43 (1999), Page (s): 1817-1820 , N Properties of Ga2 03 (Gd2 03) / GaN metal-insulator-semiconductor diodes " M. Hong, K · Α · Anselm, J. Kwo, Η · M. Ng, JN · Baillarg eon, A · R. Kortan, JP Mannaerts, AY Cho, CM Lee, JI Chy i, TS Lay. Journal of vacuum science technology B volumn (18) 3, May / Jun 2 0 0 0, Page (s): 1453-1456 and, 'Effect of temperature on G a2 03 (G d2 03) / G a N metal-oxide-semiconductor field-effect tran sistors ”F. Ren, M. Hong, S.N.G. Chu, M.A. Marcus, M.J. Schurman, A. Baca, S. J.

Pear ton, C. R. Abernathy. Applied Physics Letters, Volume 73, NO. 26, December 1998

Page 6 514993 Amendment Case No. 90119434 V. Description of the Invention (3) Γ, Γ, 5} M0SFET ^ ^ ^ ^ ^ "Yangyang" low gate leakage current and high breakdown electric field. Take LPD The oxidized layer formed by ganxi * is electrical ... Although it is not as good as the above method, its safety, low temperature, simple and economical characteristics, and rational methods are used to improve the quality of the oxide layer. We use "、、 处 2 · J 程 部Content: Due to the strong chemical bonding of gallium nitride, it is different from the traditional manufacturing methods in silicon (Si) and gallium arsenide (GaAs) in the clothing process. Two key process technologies are used here: LPD The deposition selectivity (^ elective), the LPD oxide layer will not be deposited on the metal and the photo-induced chemical wet etching (PEC) will not etch the characteristics of silicon dioxide for the mask of the platform (MESA) etching (Mask) . Compared with dry etching, pEC is not as good in terms of etching rate and surface smoothness, but it is simple, economical, and safe (because of the need for toxic gases in dry etching). As for metal, metal electrodes which are plated on semiconductors by means of general sputtering and evaporation are processed by rapid thermal annealing (RTA). In the Si MOSFET process, the gate oxide layer plays an important role. It is difficult to grow a stable oxide layer on GaN. The most common method is deposition, such as physical or chemical vapor deposition, but this equipment is expensive. . For this reason, the present inventors have made intensive research, and through continuous testing and research, the inventors will use a simple and economical liquid phase deposition method that has been applied to silicon and gallium arsenide to produce an oxide layer. Other references related to the patents for the fabrication of GaN MOSFETs are as follows: US Patent: US0 5866925 ’US 0 5525535,

514993 _Case No. 901] 9434__Year Month Day Amendment V. Description of Invention (4) US05612239 'US05937281, US05773348, US05648128, US0 5 5479 0 0, US0 55 1 6 72 1 and Republic of China Invention Patent Certificate No. 121 134 Wait. [Summary of the invention] The main purpose of the present invention is to make a gallium nitride gold-oxygen half field effect transistor using a simple and economical liquid phase deposition method that has been applied to silicon and gallium arsenide. This deposition method 1 will deposit an oxide layer on On the wafer, but not deposited on the metal. At the same time, the characteristics of photo-induced chemical wet etching will not etch silicon dioxide as the mask of the platform I, and the rapid thermal annealing method is necessary in the process. Heat treatment to improve the quality of the oxide layer. In order to achieve the above-mentioned object, the present invention proposes a gallium nitride gold-oxide half-field-effect transistor: a method of fabricating clothes, which is formed on a gallium nitride base material wafer. The gold: half-field-effect transistor includes the following steps: An epitaxial layer is formed on the gallium nitride base material wafer, a source and a room temperature liquid phase deposition oxidation method are formed on the epitaxial layer to form an oxide layer at the source: forming a gate Between the source electrode and the drain electrode, the lice-iridium metal oxide half field effect transistor is formed. The thickness of the doped layer of the epitaxial layer as described in the gallium nitride metal oxide half is about 10 per cubic centimeter, and after the half-field effect of the gallium nitride metal oxide becomes a stupid crystal layer, Including one, main steps. 'month

The manufacturing method of the field effect transistor is between 2000 and 3000 angstroms, and its concentration reaches 10 to 17th power. ′, A method for manufacturing a transistor, wherein the step of washing the gallium nitride base material wafer is as described in the method for manufacturing a gallium nitride gold-oxygen half field effect transistor, wherein

Page 8 514993 V. Description of the invention (5) The step of cleaning the gallium nitride base material wafer is to sequentially clean the surface of the wafer with deacetone, methanol, and deionized water. As described in the method for manufacturing a gallium nitride gold-oxygen half field effect transistor, after the source electrode and the drain electrode are formed in the bean, a pair of the source electrode and the drain metallization system are further included, which includes the following Steps: spin-coat a photoresist on the wafer, define the drain and source with a mask; bake; apply a vacuum sputtering machine to coat three layers of metal titanium (300 angstroms) / aluminum with argon (1000 Angstroms of gold (1000,) 'and placing it in a furnace tube of 9 G ° C for rapid thermal annealing of titanium nitride in the contact area of Titanium. Titanium forms a layer on the surface of gallium nitride. The manufacturing method of the GaN-Gold-Oxide half-field effect transistor as described in Europe, should it be a warm-liquid-phase deposition-oxidation method, or a it ^ ， method, and Dentium is a selective room-temperature liquid phase. Deposition oxidation, the method of liquid phase deposition oxidation method is to place the wafer in a + system, first to grow the oxide layer, and the gas pump is optimized parameters for it. The thickness of the growth is based on A manufacturing method of the most gold-oxygen half field-effect transistor of a component, in which 彳 t * cang number is saturated hexafluoro々τ ion water and is stirred to different Λ. Ml Take 71.43ml to stir the gas and w stir again. 27ml 0.1M boric acid, finally Xuanfa horse squirrel silicic acid 0.4M, boric acid n ni M ^ P Take the silly / healing liquid as the machine h / 〇1M The growth environment temperature is 40 ° C. The manufacturing method of m :: effect transistor before formation of the idler electrode, wherein; the coating-photoresist on gallium:; ::; :: The above steps include the following steps: Emulsified layer with a (丨: 1 〇) ratio

Page 9 V. Inventive correction of the fatigue of the monthly example ^ is 13.5 2 222, the neodymium engraved solution is left for a while; put the wafer in an acid test solution and add ultraviolet light ^ method, In shape; and repeating the room temperature liquid deposition to oxidize the gate: a method for manufacturing a gallium arsenide metal oxide half field-effect transistor, in which a main photoresist is placed on the wafer with a mask Mask (Mask) defines two and two, then bakes, and then uses a vacuum steamer to steam the 200,000 angstroms. [Simplified description of the diagram] Buy. Figure 1 shows the growth system diagram of the present invention; Figure = shows the preparation flow chart of the liquid deposition solution of the present invention; Figure 2 shows the application flow chart of the present invention; Figure 4 (a) shows the first spin coating photoresist on nitriding Figure 4 (b) of the gallium base material shows source / drain formation and metallization; Figure 4 (c) shows the formation of the first oxide layer; Figure 4 (d) shows the second spin-coated photoresist on the gallium nitride-based Figure 4 (e) shows the platform etching isolation; Figure 4 (f) shows the formation of the second oxide layer; Figure 4 (g) shows the third spin-coated photoresist on the gallium nitride substrate; (4) The crystal map of the material shows the gate formation; Figure 5 shows the capacitance-voltage characteristic curve of the present invention. [Main component number]

Page 10

11 Wafer holder 12 Wafer 13 Temperature sensor 14 Stirrer 15 Temperature-controlled electric heater 16 Liquid deposition solution 3 Source and electrode 4 Oxidation layer 41 Oxidation layer outside the platform 5 Gate 6 Photoresistor 7 Nitride base Material wafer [Detailed description of the invention] Only detailed examples and drawings are used to make detailed descriptions of the following .... The growth system diagram of the native Ming Dynasty, including: with 11, designed to hold the wafer 12 to replace: 目 Γ; phase generation Controlled information to generate thermal energy. Deposition control signal

The device 14 is used to stir the temperature of the liquid phase deposition solution; The method of making Tsai in temperature control and 0 is shown in Figure 2. Figure 2 shows the preparation flow chart of the liquid phase precipitation pure hexafluorosilicic acid (H2SiF6) solution 3 in the liquid phase deposition solution 1 of the present invention, which is a method of adding 9M to silicon dioxide (Si02 Powder 514993

----- V. Description of the invention (8) Let the solution form a supersaturated state for 24 hours at the end, wait until the silica powder ^ = redissolve, and then filter the excess solute with filter paper to form a saturated six = acid solution. Take the freshly soaked hexafluorosilicic acid 3 · 09M 12mi plus 71 · 43ml of deionized water (D · I. Water), add 25 · 27ml 〇 · 1M boric acid (η3Β03) after 25 minutes of rotor stirring. After stirring for 20 minutes, the final solution was hexafluorosilicic acid 0.4M and boric acid 0.01M, and its temperature was maintained at 40. c. On this day, π can be inserted into the wafer to start the deposition. The boric acid in the solution is set to 0.4 M, which is the best point to take into account the remaining rate and the quality of the oxide layer. Figure 3 shows the application flow chart of the present invention. The present invention uses an empty metal-oxide half field effect transistor as an example. The process is described as follows: Step 2 1 epitaxial layer growth, molecular beam epitaxy or organic metal vapor phase In the stupid crystal method, an epitaxial layer is grown on a semi-insulating gallium nitride base material wafer in a (100) direction. The thickness of the doped layer of the epitaxial layer is about 2000 to 30. Between 00 Angstroms, its concentration is about 4 times per cubic centimeter multiplied by 10 to the 17th power. Step 22 is cleaning the wafer, and the gallium nitride base material wafer grown in the above step 21 is cleaned in order with acetone, methanol and deionized water. Step 2 3 series source / drain formation and metal Then, a photoresist 6 is spin-coated on the nitride base material wafer 7. As shown in FIG. 4 (a), the drain and source 3 are defined by a mask (M ask) and baked for 15 minutes. A vacuum sputtering machine was used to coat three layers of metallic titanium (300 angstroms) / aluminum (1000 angstroms) / gold (100 angstroms) with argon, and then placed them in a furnace at 900 ° C. Rapid thermal anneal in the tube for 20 minutes, forming a layer of ohmic contact between titanium and gallium nitride surface

Page 514 993

Case No. 90119434 V. Description of the invention (9) Titanium nitride to reduce the energy barrier between metal and semiconductor, as shown in figure 4 (b)

TfT ο 'Step 24 is a room temperature liquid-phase deposition oxidation method. Step 23 * The wafer is placed in the growth system of Figure-! Hours, where the liquid phase: the parameters are shown in Figure 2. The room temperature liquid deposition oxidation method is two liquids. "6 selected = to the warm liquid phase deposition emulsification method, that is, the oxide layer 4 is deposited on the gallium nitride base = material. Wafer 7 'is not deposited on metal 3, where the oxidation and the system are silicon. The completed wafer structure is shown in Figure 4 (c). This is the formation of the primary oxide layer 4, which is used for masking. = 25 is the last name of the platform. It is the wafer and structure completed by spin coating photoresist 6 in step 24. The drain and source metals 3 and oxide layer 4 are used as the platform. After the platform is carved, it is baked for 15 minutes. Then, the other oxide layer 41 is edited at a ratio of one (1:10): f into # 2, the liquid is etched away, as shown in FIG. 4 (d), and then the wafer value f3 · 5 is · Oxidize the bell (_) material and add ultraviolet light ',,, and light to the photo-excited chemical wet etching (PEC) device (not shown), in which the following chemical reactions will be performed: 2GaN-> 2Ga3 + + N2 Ga ^ HSOH--> Ga (〇H) 3 dry t-cut squared.Compared to the narrative rate and surface smoothness, though;) the special points are easy, economical and safe (due to Toxic gas must be used for dry etching: the first-deposited oxide layer formed in Λ 2 4 has been etched away with lice acid to the damaged oxide layer, as shown in Figure 4 (e). dry

Month θ Amendment No. 90119434 V. Description of the invention (10) Step 2 6 is a liquid-phase deposition gasification at room temperature. Repeat step 24 and place it again in the picture—the phoenix deposits yy # /, ', shown at the deposition rate of 500 angstrom / mi η, this is the flute ... prepare a few ^ thickness' as shown in Figure 4⑴ 22: Formation. The oxide layer 4 is a formal gate electrode layer 4 because the silicon oxide is slightly transparent and will not be easier to align. In step 27, the interpole formation is performed, that is, in step 2, a photoresist 6 is spin-coated on the wafer, such as gang, 风, 风, 月, 、, 口, 口, and r μ, χ ^ ,, as shown in Figure 4 on the chip. (G), then the gate electrode 5 is used to define the gate electrode 5 and then baked for 15 minutes. The plating machine is steamed with 2000 angstroms of aluminum to complete the German-Taiko H0 > -The wafer structure of the present invention after 70% is shown in Figure 4 (h). In terms of u μ characteristics, when the thickness of the oxide layer is about 50 ~ 55nm, we get the interface trap density of about Λ 2 sy! η〗, 2 π ^ Τ ^ M αν / From a ^ horse A 8X 1011cnr2eV_1, the collapse electric field is about 3 ~ 4MV / Cm, and when the collapsed electric field v H is about 1 · 9 x 10 llcr2eV] and the leakage current density is reduced to 10_7A / cm2, as shown in Figure 5. The advantages of the invention are as follows:

^ Early and cheaper liquid deposition method is used to make gallium nitride MOSFET 2 · Positive voltage is applied to the gate. As the voltage increases, the source-drain current increases, and the large j is caused by a positive bias The channel layer can become an enhanced metal-oxide half-field-effect transistor. 3. Existing method for manufacturing oxide layer of gallium nitride, plating with E-beam Page 14 514993 Case No. 90119434 V. Description of the invention (11)

Ga2 03 (Gd2 03) In the furnace tube of molecular beam stupid growth (MBE), the LPD method used in the present invention has the advantages of simpler and more economical manufacturing process than the LPD method. 4. Existing methods for growing a dielectric layer on gallium nitride by chemical vapor deposition (CVD) of Si02, Si ^. The LPD method used in the present invention can form an oxide layer close to the quality of ordinary chemical vapor deposition, and has the advantages of simplicity and economy. Meaning 5. The M0SFET fabricated on Ga2 03 (Gd2 03) is plated with E-beam, and its element is dry-etched. Compared with the LpD silicon oxide layer used in the present invention and compared with the PEC etching method, the M of the present invention. Comparison of SFETs in the process ^ Operation =: at temperature (about 4.... Has better safety and lower: this. Πνί method for growing dielectric layers in disorder, chemical vapor deposition (CVD) S: i02, Sl3N4 The invented transistor is close to the current characteristics of the transistor and has a relatively simple advantage in the process m, which is an electrical process. The transistor of a knows how to make a MOS transistor with g = GaN as the base material. There is electricity in Si and ^.% Of electricity is flat. 8. GaN power devices are used as materials and under the environment. Known as higher temperature. Comprehensive: description, the nitride provided by the present invention Gallium metal oxide half-field effect = method, not only can achieve the expected practical effect and is the former ::: system: 2 patents in accordance with the elements of the invention of the patent law, according to the law with the new sense of the letter L. * Beijing to review , Yaqi said the grant of the patent early, to page 15 514993 _ case number 90119434_ year month date __ 5. Description of the invention (12) The invention has been described above For a detailed description, the above are only the preferred embodiments of the present invention. When the scope of the present invention cannot be limited, that is, all equal changes and modifications made in accordance with the scope of the patent application of the present invention should still be It belongs to the scope of protection of the patent scope of the present invention.

Page 16 514993 _Case No. 90119434_ Year Month Day Amendment Simple Illustrations Page 17

Claims (1)

514993 Case No. 9011Q4: M 6. The scope of the patent application is as follows: 1. The manufacturer of a kind of gasification gold-oxygen half-field-effect transistor; the metal-oxygen half-corpse is formed on the de-gallium nitride base material wafer. Steps: The step of forming a staggered crystal layer on the gallium nitride base material wafer to form a source electrode and an electrode on the worm crystal layer is performed by performing a room-temperature liquid-phase deposition oxidation method. Between the _ & electrode and the drain electrode, the room temperature liquid-phase deposition oxidation method oxidizes the source temperature liquid-phase deposition oxidation method, the selective room-temperature liquid-phase smoke, and the selective chamber sheet is placed in a growth The oxide layer is grown in the system, and the oxygen f = chemical method is based on the optimization parameters of a component; and the thickness of the ytterbium is 70% between the source and the electrode, Metal Oxide Half Field Effect Transistor. Clothing into the gallium nitride 2. The manufacturing method of nitriding as described in item 丨 of the scope of application for patent, 苴 中西 石 石, 永 金 乳 乳 半场 电 晶 30. . Between Angstroms, its concentration 2 is about 2_ to the power. Is the knife 1 to the 16th power to 10 to the 1 7 3 · According to the patented manufacturing method of the bell, the above mentioned epitaxial growth of the gallium nitride gold-oxygen half field-effect electro-crystallization gallium base material II After the layer, it further includes a step of cleaning the nitrogen. 4 · According to the manufacturing method of the patent application, the steps of washing the gallium nitride base material wafer by removing the GaN and GaN half field effect transistors as described in J and 5 are as follows. Normal ion water cleans the wafer surface in order. The manufacturing method, the gallium nitride gold-oxygen half field-effect transistor Bajia described in item 1, after forming the source and the drain, further includes a 514993 _ 銮 90119434__ year and month. Amendment __ VI. Application The scope of the patent is a process for metalizing the source and the drain, which includes the following steps: spin coating a photoresist on the wafer, and defining the drain and the source with a mask; baking; The vacuum sputtering machine was used to coat three layers of metal titanium (300 angstroms) / aluminum (100 angstroms) / gold (100 angstroms) with argon; and it was placed in a furnace tube at 900 ° C to quickly Thermal annealing (Rap id thermal anneal) for 20 minutes, forming a layer of titanium nitride with an ohmic contact area between the titanium and the gallium nitride surface. 6. The method for manufacturing a gallium nitride gold-oxygen half field-effect transistor as described in item 1 of the scope of the patent application, wherein the optimization parameter is saturated hexafluorosilicic acid 3. 0 9M 12ml plus 7 1.43ml deionized water After stirring, 9. 2ml (KlM of boric acid was added, and the final solution was hexafluorosilicic acid 0.4M, boric acid 0.01M, and the growing environment temperature was 40 ° C. 7 · As the first item in the scope of patent application The method for manufacturing a gallium nitride gold-oxygen half-field-effect transistor further includes a platform etching step before forming the gate electrode, which includes the following steps: Spin coating a photoresist on the gallium nitride base material wafer to draw The electrode and source metal and the gate oxide layer are the platform mask (MESA Mask) to define the platform name engraved area; baking; gas acid will oxidize the hydrogen… ι: ι °) ratio of the wafer into the acid to the letter as iq e ^ Meaning of Mald · 5 in potassium hydroxide (K0H) solution Page 19 514993 Case No. 90119434 6. The scope of the application for patents is equal to the light-excited chemical wet etching irradiated by ultraviolet light and strong acid. The damaged oxide layer is etched with hydrofluoric acid, and x is centered. 8 Room temperature liquid-phase deposition oxidation Method, forming a gate oxide layer. Announcement = Gallium Nitride Oxide Half Field Effect Transistor Cap n 'as described in the item 1 of the range, wherein the gate is first spin-coated with a photoresist on the wafer to vaporize aluminum. After the gate electrode, it is baked, and then vacuum-deposited,