TW514735B - Measurement and estimation method of the delay time of circuit in the chip under the consideration of voltage variation - Google Patents

Abstract

A measurement and estimation method of the delay time of circuit device in the chip under the consideration of voltage variation is disclosed, which comprises the following steps: measuring the delay time of each unit under the first voltage to obtain the corresponding first delay time; measuring the delay time of each unit under the second voltage to obtain the corresponding second delay time; then obtaining the corresponding delay time variation rate of each unit based on the first voltage, the second voltage, the first delay time, and the second delay time; measuring the input voltage variation of each unit, obtaining the corresponding delay time variation based on the delay time variation rate and the input voltage variation of each unit; obtaining a confirmed delay time based on the first delay time and the delay time variation.

Description

14735, case number 89114503 ... May 5. Description of the invention (1) Delayed components in the nature of the intersegmentation are in the entry pressure part. The present invention relates to a wafer analysis method, and particularly to Method used to analyze wafer delay time. On the day of testing the wafer, the delay time of each internal unit is obtained according to the voltage drop due to the impedance inside the wafer, so as to obtain the actual situation: Result and then confirm the timing delay of the wafer operation. Wu Due to the recent high density of wafer materials, the execution efficiency of wafers has also increased. However, there are specific units in the wafer, and this characteristic causes a delay in the response speed of the wafer. At the wafer 'phase = 的 The timing delay during operation is a very important parameter. Therefore,' positive; grasping the reaction speed of the wafer, that is, confirming the delay of the wafer 'θ is an important issue. The technology currently used in the industry to confirm the chip delay time is the standard delay method (standard delay f0rmat (SDF)). The method is as follows: First, prepare a unit simulation table for description. In this crystal / 5 configuration The interconnection relationship between the components; then, simulate the chip: the timing delay generated at a specific voltage; finally, calculate the sum of the delay times of the above elements ^ this predetermined voltage, you can get this. The analog value of the timing delay generated below. However, the result obtained by the above-mentioned conventional standard delay format method is not due to the fact that the above method is based on the assumption that the components of the crystal element are all the same, that is, the same as the input voltage of the chip under test: the same Operation. But in fact it is not, because the voltage in the chip will change due to the existence of impedance in its internal circuit path. State = is not the same as the situation predicted by the conventional standard delay format method described above. The test results did not match the circumstances. From this we know that

: The result simulated by the conventional standard delay format method is not too early: for the component, 'in the same situation, = 2: b' ::: long delay time 1 It can be found that the conventional standard will lead to the expected chip delay time. It will be shorter than the actual situation. If this formula is used, the result will be used as the standard rule for testing the chip performance: The yield of the disease town has increased sharply. However, the test result is wrong and widespread: production; The standard delay grid U is expected to change the simulation result of 1 time. The method of estimating the delay time of circuit components in the Chinese famous country patent announcement and the method of estimating the delay time of the circuit component delay time rise and fall rate for the delay of the circuit component, due to the impact of the delay time of each component due to the impedance, There is no technical problem. No. 3 345 1 2 accurately estimates the circuit device, its purpose is also positive, but it only considers the effect of time above the input voltage, and the circuit is discussed about the input voltage changes in the chip, Therefore, the conventional method cannot be improved. In view of this, the main purpose of the present invention is to provide an analysis method of θ delay%. Under the framework of the standard delay format method generally applicable in the industry at present, the inside of the chip is caused by impedance. Factors such as the timing delay increase caused by the input voltage drop of each component are taken into account, so that the result of the delay time of the test chip can be more accurate. "In order to achieve the above-mentioned object, the present invention proposes a method for measuring and estimating the delay time of circuit elements in a wafer under a change in voltage, which is suitable for measuring the confirmation delay time of a wafer with a plurality of early elements, including the following steps. The delay time of each unit at a first voltage to obtain the corresponding first delay time; measure each of the units at a second voltage

0503-5480TWF2; TSMC2000-0176; Robert.ptc page 5

514735: ❹1 · 4 ”29

No. 891URf ^ V. Description of the invention (3) The corresponding delay time is obtained, and the corresponding second voltage, second voltage, first delay time, and time interval are obtained, and the delay time corresponding to the first to the above units is changed. 1 The input voltage change of the unit is obtained by a delay time; according to the above-mentioned delay, the corresponding input voltage of each element in the chip is changed to B = conversion rate and the above-mentioned single-delay time and the above-mentioned delay time. Based on time. In order to make the above-mentioned purpose of the present invention, a specific example is given below-a preferred embodiment, and it can be more clearly understood in conjunction with the following: σ The detailed description is as illustrated: Figure 1 shows a diagram according to the present invention, and Figure 2 shows a diagram according to the present invention. Explanation of symbols: Flow chart of the implementation example. The embodiment includes the steps S1 to S5 to the operation flow steps of the preparatory action; S1 to S1 5 to the operation flow steps. Implementation Example: Please refer to FIG. 1, which is & ‘1 ^. First, a flowchart (S1) concerning the second embodiment of the present invention must be prepared. Refer to Fig. 2 and Fig. 2: Example #Preparatory actions for the process In the meta simulation table (Spice Net 1 i st), first prepare the test chip list.

0503-5480TWF2; TSMC2000-0176; Robert.ptc flow chart of standby operation. In preparation, the architecture of a chip is described in advance according to an embodiment of the present invention. Then, ^ (SH). The unit simulation table is used to ---- mean the input / output path of the unit

514735 _ # 号 89114Sn ^,; V. Description of the invention (4 ^-^ (S 1 2). In the path of the input and output of Xu > Yuan according to the present invention, in the example, a single step must be defined first It will be used in the next step. This information will be used later in the circuit analysis step Simulation deck (Sl ^ t 冓 unit simulation platform (sPice is mainly based on the circuit unit under test). In this step, the unit simulation platform contains The two-dimensional array of the structure. The turn-on signal conversion time and output negative voltage (S14). This method is based on the analysis of the circuit structure of the input of each unit in the chip, which can be calculated by the circuit analysis. The tool analyzes the difference between the internal voltage of the chip and the input voltage. Under the input voltage changes at the nodes of each unit in the chip, the input j is used to obtain the chip and the unit is ignored (S15). This step is based on-specific voltage The obtained delay time is obtained by measuring the delay time of the wafer, and the standard delay format method is used to simulate the delay time of the wafer. This definition of the simulated time is the first one described above about preparing the person familiar with this technology. 1) The steps are simplified descriptions for the general industry. 'Therefore, only the above steps are described briefly after completing the preparatory actions (^〗 彳 ％ η 士 M r Q 9, ^ > Time (S2), here record one yuan Du Gancan # 1 Ping Wu of the delay / 5 Hi Hi bow, _ 9 pieces corresponding to different input voltages + +, between, also called the so-called delay time. Generally, = and When receiving a higher input voltage, the combination of ## is required to give a short delay of θ θ. 5 — When the input voltage is lower, there will be a #, and the acceptance will be based on different voltages and different lightning. In the cold rush, A is called the delay time of the wide-flow path. J Early 疋 corresponds to the next-Next, according to the previously simulated unit delay time, the delay time change rate of the unit corresponding to the electric > 1 change. DR (S3). Different from each other

II 0503-5480TWF2; TSMC2000-0176; Robert.ptc Page 7 514735

i. No. 89114. V. Description of the invention (5) ^ Delay time change rate DR = AT / AV. Among them, in the crossover at the time of delay, AV is the change amount of the input voltage. The calculation method is based on the delay time result simulated in step S2. Assume that when a first · ㈣ is input to a specific unit, the delay time is [, and when the _th is entered into a specific unit, the delay time is? 2. Among them, "2" is greater than the second input voltage V2. As mentioned above, Yuanwen will have a shorter delay time when it has a higher input voltage; otherwise, it will have a longer delay when the input voltage is lower. The delay time can therefore be: The delay time τ2 is greater than the delay time ^. And τ2_Τι = ΔΤ ΔΤ divided by AV can know the delay time change rate Dr. Next, obtain the change amount (in) of the delay time of each unit. The calculation method is to multiply the voltage change amount between the input voltage of each unit node calculated in step S14 and the delay time change rate DR by multiplying the delay time change rate DR to obtain the delay time change amount of each unit. Now taking a wafer with 1 ^ cells as an example, the voltage change between the voltage of each unit and the input voltage is respectively Richter Day △%, △ ', ..., △, ", △ , And so on, and the respective delays are calculated as DR1, DR2,... DRh, DRn. Therefore, the respective delays vary between 匕 / 量, △ Tf △ & *]) &, .. .... △

Li AVny DI ^, ΔΤη-. And the total delay time change △ ΤΓΓί " ί + ΔΤ2 + ...... + ΑΤη- 丨 + △ !; This can calculate the delay time of the chip due to the voltage change caused by its internal impedance the amount. Next, according to the chip under test provided in step S15 without considering the f-drop effect, the simulated delay date _ ^ _ ^ and the total delay obtained in step S4 514735 _ case number 89114503 _ year month month amendment _ V. Invention Explanation (6) The amount of time change ΛΤΤ (^ ι, which is the sum of the two can be used to obtain the confirmation delay time (S5) of the wafer. The invention provides a method for analyzing the delay time of the wafer, which solves the impedance of each component inside the wafer As a result of the fact that the input voltages of the internal units are different from the input voltage of the chip, the error of the conventional standard delay format method makes the result of testing the delay time of the chip more accurate. Although the present invention is disclosed as above with a preferred embodiment However, it is not intended to limit the scope of the present invention. Any person skilled in the art can make some changes and decorations without departing from the spirit and scope of the present invention.

0503-5480TWF2; TSMC2000-0176; Robert.ptc Page 9

Claims (1)

514735 i No. 891 〖45 like six, patent application scope 1 · A method that considers voltage measurement and estimation, including measuring the corresponding delay time of each of the above units, obtaining the above unit pair, measuring the above unit, and obtaining the corresponding delay according to the above unit The time is extended according to the above unit. 2 • The delay time of the circuit element delay in the patent application is based on the standard. 3 • The delay time change rate of the circuit element delay in the patent application is the change between generations. 4 · If the delay time of the circuit element delay unit in the patent application is changed and the input voltage is changed.5 · If the delay time of the circuit component in the patent application is confirmed, the delay time is based on the sum of the changes. In the chip, the following steps are included: the delay time of the circuit board is from a specific electrical stress ^; the delay time under the penman, and the corresponding rate of change of the delay time. The amount of change in the input voltage, noon, the change of the delay time, and the amount of change ; And the amount of change in input voltage and the delay time and the extension of the base time, said Culture 1 to get a certain range as described in the first item — the measurement of the delay time # kinds of quasi-delay format method considering the voltage change & = different methods, where The measurement of the obtained late time as described in the above item 1 < considers the voltage variation in the unit voltage table below considering the voltage change. σ two methods, where one of the delay time corresponding to the above-mentioned early time frame is described in item 1 (1), (2), (1), (2) Considering the page measurement and estimation of Gan Shi L, and the amount of time between late-day guards under the consideration of voltage changes. It is based on the above product in the above unit / ^ eight. The delay time change rate is a method for measuring and estimating the delay time in consideration of the voltage change described in item 1, wherein the delay time of each of the above units and the corresponding delay time. 0503-5480TWF2; TSMC20〇〇〇〇i76; Robert.ptc Page 10-^^ 89114503 6. Application for patent scope 6 · A method that considers the voltage measurement and estimation method, including measuring each of the above units to obtain the corresponding first delay amount Measure each of the units to obtain a corresponding second delay. According to the first electric two delay time, obtain the measured delay time change of the unit according to the delay according to the first delay. The patented patent claims that the circuit elements have a first delay time and a second delay. 8 · If the difference in delay time of the on-chip circuit applied is divided by the above 9 · If the delay time and input voltage of the on-chip circuit unit are changed as 7 · The on-chip patented component delay rate is the first electrical patented model The amount of change in the delay of a component is described, and the delay time of a circuit component in a chip under a modified change includes the following steps: time delayed from a first voltage | time; time delayed from a second voltage Time; the voltage, the second voltage, the first delay time, and the delay time change rate corresponding to the first unit; the input voltage change amount; the time change rate and the input voltage change amount are obtained: the delay time and the above delay time change amount are A measurement and estimation method of delay time under voltage variation described in item 6 is obtained, wherein the above delay time is a measurement of delay time under voltage variation described in item 6 taken by standard delay format method. And the estimation method, wherein the difference between the voltage of the first delay time and the second delay time and the difference between the second voltage are obtained. The measurement method described in item 6 taking into account the voltage change and the delay time is a different method for estimating the distance, where the above is based on the product of the delay time change rate of the above unit. _ 0503-5480TW2; TSMC2 0OO〇-〇m; R〇bert page 11 514735 _ U _ case number 89114503 _ year 'factory amendment ___ VI. Patent application scope 1 0 · as described in the patent application scope item 6 A method for measuring and estimating the delay time of a circuit element in a wafer considering a voltage change, wherein the above-mentioned confirmation delay time is obtained according to the sum of the first delay time of each unit and the corresponding delay time variation. 0503-5480TWF2; TSMC2000-0176; Robert.ptc Page 12