TW513861B - Improved third order sigma-delta modulator - Google Patents

Improved third order sigma-delta modulator Download PDF

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Publication number
TW513861B
TW513861B TW090132446A TW90132446A TW513861B TW 513861 B TW513861 B TW 513861B TW 090132446 A TW090132446 A TW 090132446A TW 90132446 A TW90132446 A TW 90132446A TW 513861 B TW513861 B TW 513861B
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Taiwan
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output
gain
input
signal
feedback
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TW090132446A
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Chinese (zh)
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Tsung-Yi Su
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Ind Tech Res Inst
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Priority to US10/152,670 priority patent/US7075995B2/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/436—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type
    • H03M3/438—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H03M3/43—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a single bit one

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

There is provided an improved third order sigma-delta modulator, which has a feedback and feed-forward implementation for realizing the desired quantified noise transfer function by adjusting the coefficients of the feedback and feed-forward implementation. The improved third order sigma-delta modulator includes: an A/D converter for outputting a digital modulated signal; a D/A converter for converting the outputted digital modulated signal into analog signal and generating a feedback signal; a first integrating network for receiving an externally inputted signal and the feedback signal to generate a first output signal with a first gain coefficient; a second integrating network connected to the first integrating network in series for receiving the first output signal and a feedback gain signal having a feedback gain coefficient from the feedback signal to generate a second output signal with a second gain coefficient; a third integrating network connected to the second integrating network in series for receiving the second output signal to generate a third output signal with a third gain coefficient; and an adder for combining a feed-forward output signal with a feed-forward gain coefficient from the first output signal and an adjusting output signal having adjusting gain coefficient and from the third output signal to generate the required quantified error function.

Description

513861 五、發明說明（1) 發明背景 本發明係有關於一種改良式三階積分三角調變器，其 採用一回授及一前授配置（feedback and feedforward implementation)，以使所需要之量化誤差轉換函數 (Noise transfer function)經由調整該回授及前授配置 之係數來實現。 積分三角調變器（si gma —delta modulator)具有高解 析度、電路簡單、不需外加修整（trimming)電路且對電路 元件變動的谷忍度南專優點。例如’理論上，每增加一階 數（per order)可提升SNR約6dB，而其量化器（a/D)14每增 加一位元也可提升SNR約6 dB。因此，這類調變器已廣汎 地應用於需要較高訊號雜訊比（SNR )之場合，例如，應用 於數位光碟播放器（DVD player)。如第1圖所示，習知之 三階或更高階積分三角調變器是將量化器（A/D)14所輸出 之數位信號Y經由數位/類比（D/A)轉換器15回授至每一階 積分器11、12、13的輸入端來合成出預定的三階或更高階 的i化誤差轉換函數。此類架構可藉由調 整積分器的係數來合成不同的量化誤差轉換函數。然而， 這類積分三角調變器（sigma一deita modulat〇r)雖因回授 架構（configuration)而具有階數越高其解析度 (resolution)及訊號雜訊比越兩的特性，但其回授架構合 產生過載（overload)問題，致使其在實作一量化誤差函數 時之電路較為複雜。 有鑑於此，本發明之一目的係提供一種改良式三階積513861 V. Description of the invention (1) Background of the invention The present invention relates to an improved third-order integral delta modulator, which uses a feedback and feedforward implementation to make the required quantization error. The transfer function (Noise transfer function) is realized by adjusting the coefficients of the feedback and pre-allocation configuration. Integrating delta modulator (si gma-delta modulator) has the advantages of high resolution, simple circuit, no additional trimming of the circuit, and valley tolerance of circuit component changes. For example, 'theoretically, each additional order (per order) can increase the SNR by about 6dB, and the quantizer (a / D) 14 can increase the SNR by about 6 dB each bit. Therefore, this type of modulator has been widely used in applications that require higher signal-to-noise ratio (SNR), for example, in digital DVD players. As shown in Figure 1, the conventional third-order or higher-order integral delta modulator is a digital signal Y output from the quantizer (A / D) 14 via a digital / analog converter (D / A) converter 15 The inputs of each integrator 11, 12, 13 are used to synthesize a predetermined third-order or higher-order i-error conversion function. This type of architecture can synthesize different quantization error transfer functions by adjusting the coefficients of the integrator. However, this type of integral delta modulator (sigma-deita modulat0r) has the characteristics of higher resolution and higher signal-to-noise ratio due to the configuration of the feedback. The problem of overload caused by the combination of the architecture and the architecture makes the circuit more complicated when implementing a quantization error function. In view of this, an object of the present invention is to provide an improved third-order product

〇412-6885TW;ERSO-900048;SUE.ptd 第 5 f ----- 513861 五、發明說明（2) 分三角調變器（improved three order sigma-delta modulator)，其具有一回授及一前授配置（feedback and feedforward implementation)，以使所需要之量化誤差 轉換函數（Noise transfer function)經由調整該回授及 前授配置之係數來實現。 本發明係一改良式三階積分三角調變器，其經由回授 及前授的配置來產生所需的量化誤差函數（noise transfer function)並解決習知的電路不穩定的問題。該 改良式三階積分三角調變器包括：一類比/數位轉換器 (A/D converter)，用以輸出一數位調變信號；一數位/類 比轉換器（D/A converter)，用以將該輸出之數位調變信 號轉換為類比信號並產生一回授信號；一第一積分器 (first integrating network)，用以接4欠一夕卜杳p輸入信 號及該回授信號以產生一具有一第一增益係數之第一輸出 4吕號’一串接於该第一積分器之第二積分器（second integrating network) ’用以接收該第一輸出信號及一來 自該回授信號並具有一回授增益係數之回授增益信號以產 生一具有一第二增益係數之第二輸出信號；一串接於該第 一積分器之第二積分器（third integrating network)， 用以接收該第二輸出信號並產生一具有一第三增益係數之 第三輸出信號；及一加法器，用以結合一來自該第一輸出 信號並具有一前授增益係數之前授輸出信號及一來自該第 三輸出信號並具有一調整增益係數之調整輸出信號以產生 所需之量化誤差函數。〇412-6885TW; ERSO-900048; SUE.ptd 5th f ----- 513861 V. Description of the invention (2) Improved three order sigma-delta modulator, which has a feedback and a Feedback and feedforward implementation, so that the required quantization error transfer function (Noise transfer function) is realized by adjusting the coefficients of the feedback and feedforward configuration. The present invention is an improved three-order integral delta-sigma modulator, which generates the required quantization error function through the configuration of feedback and pre-feedback and solves the conventional problem of circuit instability. The improved third-order integral delta-sigma modulator includes: an analog / digital converter (A / D converter) for outputting a digital modulation signal; and a digital / analog converter (D / A converter) for converting The output digital modulation signal is converted into an analog signal and a feedback signal is generated; a first integrating network is used to connect 4 input signals and the feedback signal to generate a signal having A first output number 4 of a first gain coefficient is a second serial integrator (second integrating network) connected to the first integrator for receiving the first output signal and a feedback signal from the feedback signal. A feedback gain signal of a feedback gain coefficient to generate a second output signal having a second gain coefficient; a third integrating network connected in series to the first integrator for receiving the first integrator Two output signals and generate a third output signal having a third gain coefficient; and an adder for combining a first output signal from the first output signal and having a pre-gain gain coefficient and a from Three output signal and having an output signal to adjust the gain adjusting coefficients of the quantization error to produce a desired function.

0412-6885TWF;ERSO-900048;SUE.ptd 513861 五、發明說明（3) 圖示之簡單說明 為讓本發明之上述及其它目的、特徵、與優點能更顯 而易見，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 第1圖係一典型三階積分三角調變器； 第2圖係一本發明三階積分三角調變器之示意圖；及 第3圖係根據本發明第2圖之一實施例。 [符號說明] 11、 2 1〜第一階積分器； 12、 22〜第二階積分器； 1 3、2 3〜第三階積分器； 14、24、31 5〜類比/數位轉換器； 2 5、1 5、3 1 6〜數位/類比轉換器； 301 、30 3 、30 6 、308 、311 、314 〜力口法器； 304、309、312〜延遲器； 3 0 2〜第一階增益器； 3 0 7〜第二階增益器； 3 1 0〜第三階增益器； 3 0 5〜前授增益器； 3 1 3〜調整增益器； 3 1 7〜回授增益器。0412-6885TWF; ERSO-900048; SUE.ptd 513861 V. Description of the invention (3) The illustration of the diagram is to make the above and other objects, features, and advantages of the present invention more obvious. The preferred embodiments are given below. In conjunction with the drawings, the detailed description is as follows: Figure 1 is a typical third-order integral delta modulator; Figure 2 is a schematic diagram of the third-order integral delta modulator of the present invention; and Figure 3 is based on this An embodiment of the second figure of the invention. [Symbol description] 11, 2 1 ~ first-order integrator; 12, 22 ~ second-order integrator; 1, 3, 2 3 ~ third-order integrator; 14, 24, 31 5 ~ analog / digital converter; 2 5, 1 5, 3 1 6 to digital / analog converter; 301, 30 3, 30 6, 308, 311, 314 to Likou device; 304, 309, 312 to delay device; 3 0 2 to first Order gain device; 3 07 to second order gain device; 3 1 0 to third order gain device; 3 0 5 to pre-gain gain device; 3 1 3 to adjustment gain device; 3 1 7 to feedback gain device.

0412-6885TWF;ERSO-900048;SUE.p t d 第7頁 513861 五、發明說明（4) ------ 較佳實施例之詳細說明 以下類似功能元件係以相同參考號代表。 第2圖係一本發明三階積分三角調變器之示意圖。在 第2圖中’ §亥電路包括：—第一積分器 integrating netWOrk)21 、—第二積分器（sec〇nd integrating netW〇rk)22、一第三積分器（third0412-6885TWF; ERSO-900048; SUE.p t d page 7 513861 V. Description of the invention (4) ------ Detailed description of the preferred embodiment The following similar functional elements are represented by the same reference numbers. FIG. 2 is a schematic diagram of a third-order integral delta modulator of the present invention. In the second figure, the §Hai circuit includes:-a first integrator integrating netWOrk) 21,-a second integrator (secOnd integrating netWOK) 22, a third integrator (third

integrating network)23、一類比 / 數位轉換器（A/D C〇nverter)24 及一數位 / 類比轉換器（D/A c〇nverter)25。 如第2圖所示，該第一積分·(ΠΓ3Ϊ integrating netw〇rk)21接收一外部輸入信號並產生一第一輸出信號。 該第一輸出信號被輸入至串接於該第一積分器irst integrating network)21 後之一第二積分器（sec〇n(i integrating network)22以產生一第二輸出信號。同時， 該第一輸出化號經一包括一前授增益係數q之前授路徑 (feedforward path)FW輸入至該類比/數位轉換器（a/d converter)24 中。該第三積分器（third integrating network)23係串接於該第二積分器22後以接收該第二輸出 並產生一第二輸出jg 5虎。該第三輸出信號係經一調整增益 係數C3輸入至該類比/數位轉換器（a/d converter)24中。 此時，該外部輸入信號經過該三階積分器及該前授及調整 增益係數後會產生一量化誤差信號（未顯示）。該量化誤差 信號經一串接於該第三積分器後之類比/數位轉換器（A/D converter)24轉換成一數位調變信號Y。該數位調變信號γ 經一數位/類比轉換器（D / A c ο n v e r t e r) 2 5轉換成一類比回integrating network) 23, an analog / digital converter (A / D Converter) 24 and a digital / analog converter (D / A Converter) 25. As shown in FIG. 2, the first integration (ΠΓ3Ϊ integrating network) 21 receives an external input signal and generates a first output signal. The first output signal is input to a second integrator (secon (i integrating network) 22) serially connected to the first integrator irst integrating network 21 to generate a second output signal. At the same time, the first An output number is input to the a / d converter 24 via a feedforward path FW including a pre-gain gain factor q. The third integrating network 23 series Connected in series to the second integrator 22 to receive the second output and generate a second output jg 5 tiger. The third output signal is input to the analog / digital converter (a / d via an adjusted gain coefficient C3). converter) 24. At this time, the external input signal will generate a quantization error signal (not shown) after the third-order integrator and the pre-feedback and adjustment of the gain coefficient. The quantization error signal is connected in series to the third The analog / digital converter 24 after the integrator is converted into a digital modulation signal Y. The digital modulation signal γ is converted into an analog by a digital / analog converter (D / A c ο nverter) 2 5 return

0412-6885TWF;ERSO-900048;SUE.p t d 第8頁 513861 五、發明說明（5) 授彳§谠並經一回授路徑FB回授至該第一及第二積分器。如 此’上述之這類架構就可經由調整該前授係數匕及調整係 數〇3末產生所舄之I化誤差函數。以一實施例進一步說明 於下。 第3圖係一根據本發明第2圖之實施例。在第3圖中， 該電路包括：一第一加法器3〇1、一第一增益器3〇2、一第 二加法器303、一第一延遲器304、一前授增益器3〇5、一 第二加法器3 0 6、一第二增益器3 〇 7、一第四加法器3 0 8、 一第二延遲器309、一第三增益器31〇、一第五加法器 311、一第三延遲器312、一調整增益器313、一第六加法 器314、一N位元類比/數位轉換器（ADC)315、一n位元數位 /類比轉換器（DAC)316及一回授增益器317，其中，N為大 於零之任意整數。如第3圖所示，該加法器3 0 1將一輸入 信號與一來自該N位元數位/類比轉換器（DAC)31 6之回授信 號兩者之差值輸入至該第一增益器3〇2以放大匕倍後輸入 至該第二加法器3 0 3。該第二加法器3 〇 3將該放大&倍之信 號及該放大&倍之信號經過該第一延遲器3 〇 4以延遲一時 脈週期所產生之回饋信號相加，並將其相加結果再輸入至 該第一延遲器以產生上述第2圖中之第一輸出信號。將該 第一輸出信號輸入至該第三加法器3 0 6且同時經包括該前 授增盈器305之前授路徑FW產生一具有一回授係數匕增益 之前授輸出信號至該第六加法器3 1 4。又，該第三加法器 306將該第一輸出信號及一來自該回授增益器317之輸出信 號兩者之差值輸入至該第二增益器3〇7以放大B2倍後輸入0412-6885TWF; ERSO-900048; SUE.p t d page 8 513861 V. Description of the invention (5) Granted §§ and feedback to the first and second integrator via a feedback path FB. In this way, the above-mentioned architecture can generate the Iized error function by adjusting the pre-coefficient and the coefficient of adjustment. An example is further described below. Fig. 3 is an embodiment according to Fig. 2 of the present invention. In FIG. 3, the circuit includes a first adder 3101, a first gainer 3202, a second adder 303, a first delayer 304, and a feedforward gainer 305. A second adder 306, a second gain 307, a fourth adder 308, a second delay 309, a third gain 31o, a fifth adder 311, A third delay 312, an adjustment gain 313, a sixth adder 314, an N-bit analog / digital converter (ADC) 315, an n-bit digital / analog converter (DAC) 316, and a loop Gain gainer 317, where N is any integer greater than zero. As shown in FIG. 3, the adder 3 0 1 inputs the difference between an input signal and a feedback signal from the N-bit digital / analog converter (DAC) 31 6 to the first gain device. 3002 is inputted to the second adder 3 0 3 with a magnification. The second adder 3 03 adds the amplified & signal and the amplified & signal through the first delayer 3 04 to delay the feedback signal generated by a clock cycle and add them. The addition result is input to the first delayer to generate the first output signal in the above second figure. The first output signal is input to the third adder 3 06 and at the same time, a pre-feed output signal having a feedback coefficient gain is generated to the sixth adder via the pre-feed gain path 305 pre-feed path FW. 3 1 4. In addition, the third adder 306 inputs the difference between the first output signal and an output signal from the feedback gainer 317 to the second gainer 307 to amplify B2 times and then inputs

513861 五、發明說明（6) 至該第四加法器308，其中，該回授增益器317具有回授增 益值Ai。該第四加法器308將該放大匕倍之信號及該放 倍之信號經過該第二延遲器3 〇 9以延遲一時脈週期所產生2 之回饋信號相加，並將其相加結果輸出以產生上述第2圖 中之第二輸出信號。將該第二輸出信號輸入至該第三增益 器以放大&倍後輸入至該第五加法器3 1 1。該第五加法器 3 11將該放大Bs倍之信號及該放大bs倍之信號經過該第三延 遲器3 1 2以延遲一時脈週期所產生之回饋信號相加以產生 上述第2圖中之第三輸出信號。將該第三輸出信號輸入至 該調整增盈器313以產生一具有一調整係數C3之三階積分 輸出信號。利用該第六加法器3 1 4來整合該具有前授係數 G之前授信號及該具有調整係數c3之三階積分輸出信號以 產生一量化誤差信號N T F。將該信號輸入至該n位元類比/ 數位轉換器315以產生輸出至外部及回授至該n位元DAC以 產生該回授及前授信號所需之數位調變信號γ。如上述， 所需之量化誤差函數NTF可以下式表示之： NTF = — _ ¢^-1)3 Z3 + + +^5253C3) + Z(3 - + ΒλΒ2Β^ - AXB2BZC3) + (Β,Ο, -1) 其中’ Ζ係指積分裔’而Ai係為第二階積分器之回授增513861 V. Description of the invention (6) to the fourth adder 308, wherein the feedback gainer 317 has a feedback gain value Ai. The fourth adder 308 adds the amplified signal and the doubled signal through the second delayer 309 to delay the feedback signal 2 generated by a clock cycle, and outputs the addition result to A second output signal is generated in the above second figure. The second output signal is input to the third gainer to be amplified & multiplied by the fifth adder 3 1 1. The fifth adder 3 11 adds the amplified Bs signal and the amplified bs signal through the third delayer 3 1 2 to delay the feedback signal generated by a clock cycle to generate the first Three output signals. The third output signal is input to the adjustment gain increaser 313 to generate a third-order integral output signal having an adjustment coefficient C3. The sixth adder 3 1 4 is used to integrate the pre-signal with the pre-coefficient G and the third-order integral output signal with the adjustment coefficient c3 to generate a quantization error signal NTF. The signal is input to the n-bit analog / digital converter 315 to generate a digital modulation signal γ required for output to the outside and feedback to the n-bit DAC to generate the feedback and pre-feedback signals. As mentioned above, the required quantization error function NTF can be expressed by the following formula: NTF = — _ ¢ ^ -1) 3 Z3 + + + ^ 5253C3) + Z (3-+ ΒλΒ2Β ^-AXB2BZC3) + (Β, Ο, -1) where 'Z is the integrator' and Ai is the feedback increase of the second-order integrator

0412-6885TW;ERSO-900048;SUE.ptd 第10頁 513861 五、發明說明（7) 階、第二階、第三階積分器 益’Bi、B2、B3係分別為第 ，/「一 槓分哭 增盈，G係為前授增益及(：3係為調整增益。因此，麵由上 式調整該、、Bi、B2、B3、q、C3增益係數來合成出:^ 需量化誤差函數之三階積分三角調變器。實作上，二 任何開關電谷器（switche(j capacitor)來_ ϋ θ + ㈣差函數之類比三階積分三角調變器末=量 (l〇glC Circuit)來架構具有上述量化誤差函 ^電路 階積分三角調變器。例如，上述延遲器之數位三 容器也可使用一正反器（1?/1?)來實/吏用—交換式電 遲一時脈週期之功能。 1達使輸入信號延 雖然本發明已以一些較佳實施 用以限定本發明，#何熟知此技術如上，然其並非 明之精神及範圍内，當可做更動盘士，在不脫離本發 護範圍當視後附之中請專利範圍^ ϋ此本發明之保 ’疋者為準。 第11頁 0412-6885TWF;ERS0-900048;SUE.p t d0412-6885TW; ERSO-900048; SUE.ptd Page 10 513861 V. Description of the invention (7) The second, third, and third-order integrators benefit from the Bi, B2, and B3 series, respectively. To increase profit, G is the pre-gain gain and (: 3 is the adjustment gain. Therefore, the above formula is used to adjust the gain coefficients of Bi, B, B2, B3, q, and C3 to synthesize: ^ The error function to be quantized Third-order integral delta modulator. In practice, any switche (j capacitor) to _ ϋ θ + ㈣ difference function is analogous to third-order integral delta modulator. Let ’s construct the above-mentioned quantization error function ^ circuit-order integration delta modulator. For example, the digital three-container of the above-mentioned retarder may also use a flip-flop (1? / 1?) To implement / operate—the switching type is delayed by one hour The function of the pulse cycle. 1. The input signal is delayed. Although the present invention has been used to limit the invention with some preferred implementations, #He is familiar with this technology as above, but it is not within the spirit and scope of the clear. Without departing from the scope of this hair care, please consider the scope of patents attached to the appendix ^ ϋThe protection of this invention shall prevail. 1 page 0412-6885TWF; ERS0-900048; SUE.p t d

Claims (1)

513861 六、申請專利範圍 1 ·:種改良式三階積分三角調變器，包括： 类員比/數位轉換器（A/D converter)，用以輸出 位調變信號； 婁文位/類比轉換器（D/a converter)，用以將該輸出 之數位，變信號轉換為類比信號並產生一回授信號； 第 積分器（first integrating network)，用以 接收一外部輸入信號及該回授信號以產生一具有一第一增 益係數之第一輸出信號； 一串接於該第一積分器之第二積分器（sec〇n(i integrating network)，用以接收該第一輸出信號及一來 自该回授#號並具有一回授增益係數之回授增益信號以產 生一具有一第二增益係數之第二輸出信號； 一串接於該第二積分器之第三積分器（third integrating network)，用以接收該第二輸出信號並產生 一具有一第三增益係數之第三輸出信號；及 一加法器，用以結合一來自該第一輸出信號並具有一 月’j授增盈係數之前授輸出信號及一來自該第三輸出信號並 具有 °周整增盈係數之調整輸出信號以產生所需之量化誤 差函數。 2 ·如申請專利範圍第1項之改良式三階積分三角調變 器’其中’上述各積分器所對應之第一、第二、第三增益 係數、該前授、回授增益係數及該調整增益係數與一量化 誤差函數間具有下列關係：513861 6. Scope of patent application1: An improved third-order integral delta modulator, including: A / D converter for output bit modulation signal; Lou Wen bit / analog conversion A D / a converter for converting the output digits into analog signals and generating a feedback signal; a first integrating network for receiving an external input signal and the feedback signal To generate a first output signal with a first gain coefficient; a second integrator (secon (i integrating network)) connected to the first integrator for receiving the first output signal and a The feedback # sign has a feedback gain signal with a feedback gain coefficient to generate a second output signal with a second gain coefficient; a third integrating network connected to the second integrator (third integrating network) ) For receiving the second output signal and generating a third output signal with a third gain coefficient; and an adder for combining a first output signal with a gain of one month The previous output signal and an adjusted output signal from the third output signal and having an integral gain coefficient of °° are used to generate the required quantization error function. 2 · As an improved third-order integral triangle in the first scope of the patent application The modulator 'where' has the following relationships between the first, second, and third gain coefficients corresponding to the above integrators, the pre-feedback, feedback gain coefficients, and the adjusted gain coefficients and a quantization error function: 0412-6885TW;ERSO-900048;SUE.ptd 第12頁 513861 六、申請專利範圍 NTF- __ (Z -1)3___ Z3 + Z2 (-3 + B^cx + 53c3) + Z(3- 2B1C1 + a,B2 53C3) + -1) 其中’ N T F係為量化誤差函數’ Z係為積分器，而Ai係為回 授增益係數，Bi、B2、B3係分別為第一、第二、第三增益 係數，q係為前授增益係數及c3係為調整增益係數。 3 ·如申請專利範圍第2項之改良式三階積分三角調變 器’其中，任何具有上述量化誤差函數之類比三階積分三 角調變器包括一交換式電容電路（switched capacitor)。 4 ·如申請專利範圍第2項之改良式三階積分三角調變 器’其中’任何具有上述量化誤差函數之數位三階積分三 角調變器包括一數位邏輯電路。 5· —種改良式三階積分三角調變器，包括： 第 加法器’具有一第一輸入端、一第二輸入端及 一輸出端’該第一輸入端連接至一外部輸入信號； 一第一增益器，具有一輸入端及一輸出端，該輸入端 連接至上述第一加法器之輸出端； 一第二加法器，具有一第一輸入端、一第二輸入端及 一輸出端’該第一輸入端連接至上述第一增益器之輸出 端； 苐 延遲器’具有一輸入端及一輸出端，該輸入端0412-6885TW; ERSO-900048; SUE.ptd Page 12 513861 VI. Patent application scope NTF- __ (Z -1) 3 ___ Z3 + Z2 (-3 + B ^ cx + 53c3) + Z (3- 2B1C1 + a , B2 53C3) + -1) where 'NTF is the quantization error function' Z is the integrator, Ai is the feedback gain coefficient, and Bi, B2, and B3 are the first, second, and third gain coefficients, respectively , Q is the pre-gain gain coefficient and c3 is the adjustment gain coefficient. 3. The improved third-order integral triangular modulator according to item 2 of the patent application, wherein any analog third-order integral triangular modulator having the above-mentioned quantization error function includes a switched capacitor circuit. 4. The improved third-order integral trigonometric modulator according to item 2 of the patent application, wherein any of the digital third-order integral trigonometric modulators having the above-mentioned quantization error function includes a digital logic circuit. 5. · An improved third-order integral delta modulator, including: a first adder 'having a first input terminal, a second input terminal, and an output terminal', the first input terminal being connected to an external input signal; The first gainer has an input end and an output end, the input end is connected to the output end of the first adder; a second adder has a first input end, a second input end, and an output end 'The first input terminal is connected to the output terminal of the first gain device; 苐 delayer' has an input terminal and an output terminal, and the input terminal 0412-6885TWF;ERS0-900048;SUE.p t d 第13頁 513861 六、申請專利範圍 連接至上述第二加法器之輸出端，該輸出端連接至上述第 二加法器之第二輸入端； 一前授增益器，具有一輸入端及一輸出端，該輸入端 連接至上述第一延遲器之輸出端； 一第三加法器，具有一第一輸入端、一第二輸入端及 一輸出端，該第一輸入端連接至上述第一延遲器之輸出 端； 一第二增益器，具有一輸入端及一輸出端，該輸入端 連接至上述第三加法器之輸出端； 一第四加法器，具有一第一輸入端、一第二輸入端及 一輸出端，該第一輸入端連接至上述第二增益器之輸出 端； 一第二延遲器，具有一輸入端及一輸出端，該輸入端 連接至上述第四加法器之輸出端，該輸出端連接至上述第 四加法器之第二輸入端； 一第三增益器’具有一輸入端及一輸出端’該輸入端 連接至上述第四加法器之輸出端； 一第五加法器，具有一第一輸入端、一第二輸入端及 一輸出端，該第一輸入端連接至上述第三增益器之輸出 端， 一第三延遲器，具有一輸入端及一輸出端’該輸入端 連接至上述第五加法器之輸出端，該輸出端連接至上述第 五加法器之第二輸入端； 一調整增益器，具有一輸入端及一輸出端，該輸入端0412-6885TWF; ERS0-900048; SUE.ptd Page 13 513861 6. The scope of the patent application is connected to the output of the above-mentioned second adder, which is connected to the second input of the above-mentioned second adder; The gain device has an input end and an output end, the input end is connected to the output end of the first delayer; a third adder has a first input end, a second input end, and an output end, the A first input terminal is connected to the output terminal of the first delayer; a second gain device having an input terminal and an output terminal, the input terminal is connected to the output terminal of the third adder; a fourth adder, It has a first input terminal, a second input terminal and an output terminal. The first input terminal is connected to the output terminal of the second gain device. A second delay device has an input terminal and an output terminal. The input Terminal is connected to the output terminal of the fourth adder, the output terminal is connected to the second input terminal of the fourth adder; a third gain device has an input terminal and an output terminal; the input terminal is connected to the first four The output end of the amplifier; a fifth adder having a first input end, a second input end and an output end, the first input end is connected to the output end of the third gain device, and a third delay device Has an input end and an output end, the input end is connected to the output end of the fifth adder, and the output end is connected to the second input end of the fifth adder; an adjustment gain device having an input end and An output, the input 0412-6885TWF;ERSO-900048;SUE.p t d 第14頁 六、申請專利範圍 連接至^述第三延遲器之輸出端； 一 =/、加法器，具有一第一輸入端、一第二輸入端及 二輸出端:該第一輸入端連接至上述調整增益器之輸出 鸲，該第'輪入端連接至上述前授增益器之輸出端； 一N位7L類比/數位轉換器（ADC)，具有一輸入端及一 =减ΐ ΐ輸人端連接至上述第六加法器之輸出端，該輸 出端連接至外部； w 輸出：N，H數位山/類比轉換器（DAC)，具有一輸入端及一 出端，該；= 位元類比/數位轉換器之輸 -回授増益器，具有器=ί輸入端；及 連接至上述Ν位元數位/類：鈿&輸出知’該輸入端 接至上述第三加法比轉換器之輸出端，該輪出端連 6.如申請專利範上輸/端。， 器，其中，Ν為大於零之任音改良式二階積分三角調變 7 ·如申凊專利範圍第 器，其中，上述分別屬&項^改良式三階積分三角調變 器之第-、第=、第—階、第二階、第三階積分 益器各具有一第一、第:皿為與上述前授、回授及調整增 係數。 —、第三、前授、回授及調整增益 8 ·如申請專利範圍第7 一 器，其中，上述第一、第-、之改良式二階積分三角調變 益係數與一量化誤差函素^、第三、前授、回授及調整增 曰’具有下列關係：0412-6885TWF; ERSO-900048; SUE.ptd Page 14 6. The scope of the patent application is connected to the output of the third retarder; a = /, an adder with a first input and a second input And two output terminals: the first input terminal is connected to the output of the above-mentioned adjusting gain device, the first input terminal is connected to the output terminal of the aforementioned pre-gaining device; an N-bit 7L analog / digital converter (ADC), It has an input terminal and a = minus ΐ input terminal connected to the output terminal of the sixth adder, and the output terminal is connected to the outside; w output: N, H digital mountain / analog converter (DAC), has an input Terminal and an output terminal, this; = bit analog / digital converter input-return gain device, with device = ί input terminal; and connected to the above N bit digital / type: / & output know 'the input The output terminal is connected to the output terminal of the third addition ratio converter, and the output terminal of the wheel is connected to the output / terminal as in the patent application. , Where N is an improved second-order integral triangular modulation of any tone greater than zero. 7 As described in the patent scope of the patent, where the above are respectively the & item ^ improved third-order integral triangular modulator- The first, the third, the second, and the third-order integrators each have a first and a third: the gain coefficients are in accordance with the aforementioned pre-grant, feedback, and adjustment. —, Third, Pre-Grant, Feedback and Adjust Gain 8 · If the 7th device in the scope of patent application, where the above-mentioned modified first-, second-, and third-order integral triangular modulation gain coefficients and a quantization error function ^ , Third, pre-grant, feedback and adjustment Zeng Yue 'has the following relations: $ 15頁 513861 六、申請專利範圍 NTF 二 ____(Z -1)3______ F + Z\-3^B^+A1B2B^) + ^(3- 25^! + BXB^C^ AlB2B3C3) + -1) 其中，NTF係為量化誤差函數，z係為積分器，而Ai係為回 授增益係數，Bi、B2、B3係分別為第一、第二、第三增益 係數，G係為前授增益係數及&係為調整增益係數。 9.如申請專利範圍第8項之改良式三階積分三角調變 =，其中，任何具有上述量化誤差函數之類比三階積分三 角調變器包括一交換式電容器電路（swi tched capacitor) ° -，二：'凊專利範圍第8項之改良式三階積分三角調變 =q s Μ 3 =何f有上述量化誤差函數之數位三階積分三 角调^裔包括一數位邏輯電路（logic gate)。$ 15 pages 513861 VI. Patent application scope NTF II ____ (Z -1) 3 ______ F + Z \ -3 ^ B ^ + A1B2B ^) + ^ (3- 25 ^! + BXB ^ C ^ AlB2B3C3) + -1 ) Among them, NTF is the quantization error function, z is the integrator, and Ai is the feedback gain coefficient, Bi, B2, and B3 are the first, second, and third gain coefficients, respectively, and G is the pre-gain gain. The coefficient and & are adjustment gain coefficients. 9. The improved third-order integral trigonometric modulator according to item 8 of the scope of patent application =, wherein any analog third-order integral trigonometric modulator having the above-mentioned quantization error function includes a swap capacitor circuit (swi tched capacitor) °- Second, the modified third-order integral triangular modulation of item 8 of the patent scope = qs Μ 3 = where the digital third-order integral triangular modulation with the above-mentioned quantization error function includes a digital logic circuit. 第16頁Page 16
TW090132446A 2001-12-27 2001-12-27 Improved third order sigma-delta modulator TW513861B (en)

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TW090132446A TW513861B (en) 2001-12-27 2001-12-27 Improved third order sigma-delta modulator
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FR2864734B1 (en) * 2003-12-31 2006-03-03 Eads Telecom MODULATOR SIGMA-DELTA DIGITAL SINGLE LOOP OF HIGH ORDER
JP4372184B2 (en) * 2007-09-20 2009-11-25 株式会社東芝 Sample rate converter
US7782239B2 (en) * 2008-10-28 2010-08-24 Robert Bosch Gmbh Multi-stage resettable sigma-delta converters
EP2582050B1 (en) * 2011-10-13 2017-08-09 OCT Circuit Technologies International Limited Multi-level sigma-delta ADC with reduced quantization levels
EP2582051A1 (en) 2011-10-13 2013-04-17 ST-Ericsson SA Multi-level sigma-delta ADC with reduced quantization levels
TWI517596B (en) * 2013-07-18 2016-01-11 瑞昱半導體股份有限公司 Feedforward delta-sigma modulator
CN104348489B (en) * 2013-07-25 2019-01-18 瑞昱半导体股份有限公司 Feed forward type triangular integration modulator

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US5673044A (en) * 1995-08-24 1997-09-30 Lockheed Martin Corporation Cascaded recursive transversal filter for sigma-delta modulators
US5623263A (en) * 1995-10-20 1997-04-22 National Science Council 4th-order sigma-delta modulator with leapfrog topology
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