JPH08242173A - Integrator and delta sigma modulator of distributed feedback type - Google Patents

Abstract

PURPOSE: To stably hold the whole system by gradually saturating each integra tion stage from a high order to a low order corresponding to the amplitude width of an input signal. CONSTITUTION: These integrators 11 to 14 obtain an integration output by adding a signal obtained by delaying its own integration output by one sample and an after-mentioned feedback signal, inputting the added output to a limiter 2 and adding the output of the limiter 2 and the integration input. These integrators 11 to 14 are combined to be plural stages in serial so that an input signal X is inputted to the integrator 11 at a first stage and the output of the integrator 14 at a last stage is inputted to a quantizer 30. Then a signal obtained by delaying the output signal of the quantizer 30 and multiplying it by a proper coefficient is made the feedback signal to each integrator 11 to 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is a ΔΣ modulator (generally called a ΣΔ modulator overseas, which is a main constituent of A / D converters and D / A converters in digital audio equipment and the like. In particular, the present invention relates to a distributed feedback ΔΣ modulator in which a plurality of integrators are connected in series and an integrator used for the distributed feedback ΔΣ modulator.

[0002]

2. Description of the Related Art A / D converters and ΔΣ modulators in D / A converters include a feedforward system and a distributed feedback system. Since the distributed feedback system does not require an adder in the feedforward system, it has the merit that the circuit can be downsized and the transfer function can be widely selected. The basic configuration of such a distributed feedback system ΔΣ modulator is shown in FIG. Is shown in.

In FIG. 3A, this example shows a fourth-order ΔΣ in which four integrators 11, 12, 13, and 14 are connected in series.
It is a modulator. Coefficient units 21, 22, 23 are provided between the integration stages.
Are inserted respectively. The input signal X is applied to the integrator 11 in the first stage, and the output of the integrator 14 in the final stage is the quantizer 3
0 is input to obtain a quantized signal Y. Quantized signal Y
Is delayed by the 1-sample delay unit 40, and each integrator 11, 12, through the coefficient unit 51, 52, 53, 54, respectively.
It is fed back to the input stages of 13 and 14, and the feedback signal is added (correctly, subtraction) to the integration input of each stage. Each integrator 11-14 is shown in FIG.
As described above, the integrated output of itself is delayed by one sample by the delay device 1, and the integrated output is obtained by adding the delayed signal and the integrated input signal.

Here, in the distributed feedback ΔΣ modulator of FIG. 3A, in order to keep the system stable even when a large amplitude input signal X is applied, the transmission system from the input X to the output Y is used. It is necessary to add amplitude limiting means (limiter). Therefore, conventionally, as shown in FIG. 3C, it has been considered to insert the limiter 2 on the output path of the integrated signal of each of the integrators 11 to 14.

[0005]

However, if all the integration stages are constructed as shown in FIG. 3 (c), the limiter 2 in the fourth-order integrator 14 operates first as a matter of course. However, since the integrators 11 to 14 are connected in series, the signal loops of the other three stages are also limited by the activated fourth-order limiter 2, and the input X to the output Y
The system leading to becomes non-linear.

That is, the ideal operation of the amplitude limiting means is that each integration stage is gradually saturated from high order to low order according to the amplitude level of the input signal to keep the whole system stable. If the distributed feedback ΔΣ modulator of FIG. 3A is configured by the integrator with a limiter of FIG. 3C, such an operation cannot be realized.

The present invention has been made in view of the above-mentioned conventional problems, and an object thereof is to gradually saturate each integration stage from a high order to a low order according to the amplitude level of an input signal and to make the entire system. It is an object of the present invention to provide a distributed feedback ΔΣ modulator that can be kept stable and an integrator for the same.

[0008]

An integrator according to the present invention adds a signal obtained by delaying its own integrated output by one sample and a feedback signal from another system, inputs the added output to a limiter, and outputs the added output of the limiter. The integrated output is obtained by adding the output and the integrated input.

Then, the integrators having the above-mentioned structure are connected in series, and an input signal is added to the integrator at the first stage, the output of the integrator at the final stage is input to the quantizer, and the output signal of the quantizer is input. A distributed feedback ΔΣ modulator is constructed by delaying the signal by one sample and using the signal multiplied by an appropriate coefficient as the feedback signal for each integrator.

[0010]

Since the limiter is applied to the added output of the signal obtained by delaying the integrated output of itself by one sample and the feedback signal, and the output of the limiter and the integrated input are added to form the integrated output, the amplitude limiting function of the limiter. Even when is activated, the limiter output added to the integral input is saturated, but the system from the integral input to the integral output is not saturated. Therefore, in a distributed feedback ΔΣ modulator in which a plurality of stages of these integrators are connected in series, even if the limiter of a high-order (final stage) integrator works, the integration function of that stage is saturated, but a lower-order integrator is used. There is no hindrance to the operation of the integrators of the other stages, and the system from the input of the first stage to the quantizer of the output stage is kept almost linear. Therefore, it is possible to realize a ΔΣ modulator that operates stably even with a large amplitude input and exhibits excellent characteristics.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of a fourth-order distributed feedback ΔΣ modulator according to an embodiment of the present invention. The basic structure is the same as the conventional one, and four integrators 11 and 1
This is a fourth-order ΔΣ modulator in which 2, 13, and 14 are connected in series. Coefficient units 21, 22, and 23 are inserted between the respective integration stages. The input signal X is applied to the integrator 11 in the first stage, the output of the integrator 14 in the final stage is input to the quantizer 30, and the quantized signal Y is obtained. The quantized signal Y is delayed by the 1-sample delay unit 40, and the coefficient units 51 and 5 are respectively delayed.
Via integrators 11, 12, 13, 1 via 2, 53, 54
Feedback to 4.

A limiter 2 is built in each of the integrators 11 to 14, and a 1-sample delay unit 1 for integration is used.
The relationship among the integration input, the integration output, and the feedback signal is significantly different from the configuration of FIG. 3C described in the section of the related art. That is, as shown in FIG. 1, in each of the integrators 11 to 14 of the present invention, the output of the delay device 1 obtained by delaying the integrated output of itself by one sample and the coefficient devices 51 to 51, respectively.
The feedback signal that has passed through 54 is first added by the adders 61 to 6
Added in 4, input the added output to the limiter 2,
The output of the limiter 2 and the integral input are added by the adders 65 to 68 to form the integral output.

In the distributed feedback ΔΣ modulator in which four stages of integrators of this configuration are connected in series, even if the limiter 2 of the final stage integrator 14 works, the integration of that stage is performed even if the amplitude of the input signal X becomes large. Although the function is saturated, it does not hinder the operation of the integrators 11, 12, and 13 of the other stages of lower order, and the system from the input signal X of the first stage to the quantizer 30 of the output stage is kept almost linear. Be drunk When the level of the input signal X further increases, the limiter 2 of the third-order integrator 13 also operates next, but the system from the input X to the output Y is kept substantially linear. When the level of the input X further increases, the limiter 2 of the second-order integrator 12 also works, but the input / output system as a whole is kept almost linear.

The structure of the integrator according to another embodiment of the present invention is shown in FIG. This embodiment is an analog integrator. The main body of the integrator is the operational amplifier OP and the capacitor C0, and the diode D1 and the diode D2 correspond to the limiter 2 described above. In this integrator, the four switches SW1 to SW4 included therein operate at the four-phase timing as follows.

That is, in the first phase, SW1 = a, SW2 =
b, SW3 = a, SW4 = OFF, capacitor C
i is charged with the integral input, and the capacitor Cf is charged with the feedback signal. The second phase is SW1
= Open, SW2 = a, SW3 = b, SW4 = ON, and the charge charged in the capacitor Cf is added to the capacitor C0. Diode D in capacitor C0
Since 1 and diode D2 are connected in parallel, the voltage on capacitor C0 does not exceed the diode forward drop voltage of 0.7 volts (this is the action of the limiter). In the third phase, SW1 = b, SW2 = a, SW3 = open, SW4 =
It is turned off, and the electric charge charged in the capacitor Ci is added to the capacitor C0. At this time, since the diode D1 and the diode D2 are separated, the result is the same as the limit value of the limiter being added to the integral input. The equivalent circuit of this circuit is shown in FIG.

As described above, also in the integrator of the analog circuit, similarly, the signal one sample before and the feedback signal from the output can be added first, and then the limiter can be applied and added to the main signal line. In the above embodiment, the case where the integrators 11 to 14 have four stages is shown, but the present invention can be applied as long as the integrator has two stages or more.

[0017]

As described above, according to the present invention, the signal obtained by delaying its own integrated output by one sample and the feedback signal described below are added, the added output is input to the limiter, and the output of the limiter is set. An integrator that obtains the integrated output by adding the integrated inputs is connected in multiple stages in series, an input signal is added to the integrator in the first stage, the output of the integrator in the final stage is input to the quantizer, and the quantization is performed. Since the output signal of the integrator is delayed by one sample and the signal multiplied by an appropriate coefficient is used as the feedback signal for each integrator, each integration stage changes from high order to low order according to the amplitude level of the input signal. It has the effect of gradually saturating and keeping the whole system stable. That is, the distributed feedback modulator has an advantage over the feedforward modulator in that the adder before the quantizer is unnecessary and the transfer function and the internal amplitude can be set more freely. Then, without losing this advantage, it is possible to construct a ΔΣ modulator that stably operates even with a large amplitude input and exhibits excellent characteristics.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a distributed feedback type ΔΣ modulator according to an embodiment of the present invention.

2A is a configuration diagram of an integrator according to another embodiment of the present invention, and FIG. 2B is an equivalent circuit diagram thereof.

3A is a basic configuration diagram of a distributed feedback ΔΣ modulator, FIG. 3B is a configuration diagram of an integrator, and FIG. 3C is a configuration diagram of a conventional integrator.

[Explanation of symbols]

 1, 40 ... 1 sample delay device 2 ... Limiter 11-14 ... Integrator 21-23, 51-54 ... Coefficient device 30 ... Quantizer

Claims (2)

[Claims] 1. The integration is performed by adding a signal obtained by delaying its own integrated output by one sample and a feedback signal from another system, inputting the addition output to a limiter, and adding the output of the limiter and the integration input. An integrator characterized by obtaining an output. 2. The integrated output of itself is delayed by one sample and a feedback signal described below are added, the added output is input to a limiter, and the integrated output is obtained by adding the output of the limiter and the integrated input. The integrators to be obtained are connected in multiple stages in series, the input signal is added to the integrator at the first stage, the output of the integrator at the final stage is input to the quantizer, and the output signal of the quantizer is delayed by one sample and appropriately A distributed feedback delta-sigma modulator characterized in that a signal obtained by multiplying by is used as a feedback signal for each integrator.