TW513774B - Tunable structure and method for fabricating the same utilizing the formation of a compliant substrate - Google Patents

Abstract

A highly tunable structure (20) can be monolithically integrated upon a monocrystalline semiconductor substrate (22) according to the structure and process described herein. High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates (22) such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An amorphous interface layer (28) dissipates strain and permits the growth of a high quality monocrystalline buffer layer (24). In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy (61) and epitaxial growth of Zintl phase materials (130).

Description

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Reference to previous patent application This application was filed in the United States on January U. 2001 with patent application number 09 / 758,723. FIELD OF THE INVENTION The present invention relates to an adjustable structure and device, and a method for manufacturing the same. More particularly, the present invention relates to an improved adjustable structure and a monolithic etching method for integrating an adjustable structure with a silicon device and a circuit. Together. BACKGROUND OF THE INVENTION The dielectric constant of a tunable structure can be changed (ie, adjustable) with an external dc (direct current, bias) electric field. As the dielectric constant of a material changes, the electrical length of the material changes. This phenomenon can lead to the use of tunable structures as variable units in tunable microwave devices, such as phase shifters, tunable filters, phased array antennas, and delay lines. It is known that titanic acid is used in different electronic applications. High η (in the range of 200 to 6,000) of barium europium (BST〇). For example, in DRAM (Dynamic Random Access Memory), bypass capacitors, IR detectors and tunable microwave devices In application, BST0 has been paid considerable attention as a suitable dielectric material. Generally, BST0 will exhibit high dielectric constant, low dielectric loss, good thermal stability, and good high-frequency characteristics. Its dielectric The non-linearity of the characteristics relative to the applied ECG makes BSTO particularly attractive for tunable microwave devices, such as' filters, variable resistors, delay lines, and phase shifters. Thin-film BSTO has additional advantages, ， Rugged, low operating temperature, low operating voltage, and compatibility with semiconductor process technology. -4-This paper is suitable for national materials (CNS) A4 specification (21GX297 public) 513774 A7 B7 V. Description of the invention ( 2 )

Different methods have been proposed to combine (doped Λ 乂 乂) BSTO with different other materials and / or compounds to further improve the use of electrical applications. For example, it has been reported that the BST0 | t tick maggot (MgO) of the bulk composite material will improve the dielectric tunability characteristics' and reduce the dielectric loss compared to pure BSTO. For specific examples of the structural and electrical properties of doped BSTO, please refer to the following patents and journals: US Patent 5,427,988, Seng = ta et al. Filed on June 27, 1995 (BSTO-MgO composite materials); US Patent 5,635,433, Sengupta et al. Filed an application on June 3, 1997 (BST〇_Zn〇 composites); Joshi et al. "Mg-Doped Ba〇6Sr〇4Ti03Thin

Films For Tunable Microwave Applications ", Applied Physics Letters, vol 77 num 2, pp. 289-291 (10 July 2000); Carlson et al.," Large Dielectric Constant (ε / ε〇 > 6000) Ba〇4Sr〇. 6Ti03 Thin Films For High-Performance Microwave Phase Shifters ",

Applied Physics Letters, vol 76 num 14, pp. 1920-1922 (3 April 2000) (BST / MgO and BST / LA0 (LaAL03)). Semiconductor devices often include multiple conductive layers, insulating layers, and semiconductor layers. Often, the desired characteristics of these thin layers will improve with the crystallinity of the layers. For example, the electron mobility and band gap of a semiconductor layer will improve as the crystallinity of each layer increases. Similarly, the free electron concentration of the conductive layer and the electronic charge displacement and electron energy recoverability of the insulating or dielectric film will improve as the crystallinity of these thin layers increases. For many years, we have worked hard to grow different monoliths on foreign substrates.

I thin film, such as silicon (Si). However, in order to achieve different optimal characteristics, a single crystal thin film having a high crystal density is required. For example, we are committed to growing different single crystal layers up to -5- This paper size applies the Chinese National Standard (CNS) A4 specification (21 × 297 mm) 513774 A7 B7 V. Description of the invention (3) On the substrate, Such as germanium, silicon and different insulators. These efforts are generally unsuccessful, because the lattice between the main crystal and the growing crystal is not matched, which will cause the final single crystal material layer to have a lower crystalline quality. If a large-area, high-quality single-crystal material film is available at low cost, it is produced by starting with a bulk wafer of a semiconductor material or a stupid thin film of this material on a bulk wafer of a semiconductor material. Compared with the cost of such a device, a semiconductor device can be manufactured in a low-cost manner or at a relatively low cost. In addition, if you can start with a bulk wafer such as a silicon wafer to realize a thin film of high-quality single crystal material, you can achieve a structure of a device such as an integrated adjustable structure or an integrated phase shifter. The advantages are At the same time, it has the best characteristics of a high quality single crystal semiconductor layer such as BSTO and a high quality single crystal semiconductor layer such as germanium arsenide. Therefore, there is a need for a tunable structure with a high-quality single crystal thin film or a thin layer with a variable dielectric constant. The thin layer is on another single crystal material suitable for different electrical devices. Structural approach. That is, it is necessary to form a single crystal substrate that is compatible with a high-quality single-crystal material layer, to achieve actual two-dimensional growth, and to form a high-quality tunable structure and a semiconductor device integrated in a silicon matrix circuit. Brief Description of the Drawings The present invention is described by way of example with related drawings, but is not limited thereto. Similar reference numerals represent similar units, and among them: Figures 1 and 2 are sectional views. The diagram shows the structure of the device according to different embodiments of the present invention; -6-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

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Fig. 3 is a graph showing the relationship between the maximum thickness, the thickness of the film, the thickness of the film, and the mismatch between the day and the day when the main crystal person grows the crystal; Fig. 4 does not show the inclusion Single crystal auxiliary slow seeding electron micrograph; high-resolution transmission structure of the read layer structure Figure 5 shows the X-ray diffraction spectrum of the structure including the single crystal auxiliary buffer layer; Figure 6 A-6D is a sectional view The method _ ,,,,,,,, and the formation of a device structure according to another embodiment of the present invention; Figures 7A-7D show the possible molecular bonding of the magnetic garment structure shown in Figures 6A-6D Structure; FIG. 8-10 is a sectional view showing the formation of a device structure according to another embodiment of the present invention; FIG. 11 is a sectional view showing a display according to an embodiment of the present invention; Adjustable structure; and FIG. 12 is a diagrammatic illustration of a phase array antenna system according to the present invention. Skilled technicians will take the boat to the bottom. The early element in the diagram is for simplicity and clear display. It does not depend on the actual size. For example, the dimensions of some elements in the drawings may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention. Detailed Description of the Drawings Fig. 1 is a sectional view showing a partially adjustable structure 20 according to an embodiment of the present invention. The structure 20 includes a single crystal substrate 22 including a single crystal auxiliary buffer layer 24 'of a single crystal material and a single crystal semiconductor layer 26. In this specification, the term "single crystal" has the meaning commonly used in the general semiconductor industry. This term refers to materials with single crystals or essentially single-junction paper. Applicable to China National Standard (CNS) A4 Specifications (210 X 297 mm) 513774

The materials that are also used must include materials with few defects, such as niches and similar defects commonly found in silicon or germanium substrates or silicon-germanium mixture substrates, and commonly found in the semiconductor industry ^ The epitaxial layer of the material. According to an embodiment of the present invention, the structure 20 also includes an amorphous intermediate layer 28 between the substrate 22 and the auxiliary buffer layer 24. The structure 20 also includes a sample layer 30 between the single-crystal auxiliary% punch layer and the single-crystal semiconductor layer 26. The following will be done the following month, and the slab layer will help start the growth of the single crystal semiconductor layer on the auxiliary buffer layer. The amorphous intermediate layer will help reduce strain in the auxiliary buffer layer and help grow a high crystalline quality auxiliary buffer layer. The substrate 22 according to the embodiment of the present invention is a single crystal semiconductor or a compound semiconductor wafer, and preferably has a larger radius. For example, Shaw wafers are Group IV materials in the periodic table, and SIVB materials are preferred. Examples of the semiconductor materials of the ιν group include Shi Xi, Ge Xi's mixed Shi Xi and Ge, mixed Shi Xi with carbon, Ge and Ge, and similar materials. The substrate 22 is preferably composed of wafers or wafers, and the high-quality f-single-crystal® used in the semiconductor industry is more preferred. The material of the line auxiliary buffer layer 24 is preferably selected to be compatible with the bottom The substrate and the bottom half of the material have crystalline compatibility. In addition, the auxiliary buffer layer 24 is preferably tunable. In addition, the auxiliary buffer layer 24 is preferably a single crystal oxide 3 compound, which has here Required properties, including materials such as soil test gold titanate 'earth test gold hammer salt, alkaline earth gold test salt, soil test gold knowledge West meaning salt' test soil gold ruthenium salt, test soil Au group niobate, test Au group Au sulphate Dilovsgate (p⑽ν_) oxides, such as Ming acid, steel oxidation ', lice 釓, alkaline earth Au tin base matrix Pelovs Gate .general'

513774 A7 B7 V. Description of the invention (6) These materials are metal oxides or metal nitrides, especially these oxide bite nitrides include at least two different metal elements. In some applications, the metal oxide or nitride is comprised of three or more metal elements. In addition, depending on the particular application, the auxiliary buffer layer 24 may be a composite material of two or more compounds. The material of the single crystal semiconductor layer 26 may be selected to give a particular structure or application required, and in particular, to accommodate the next electrical device or devices. For example, the single crystal semiconductor layer 26 may include a compound semiconductor for a desired specific semiconductor structure, which is selected from Group IIIA and Group VA elements (Group III-V semiconductor compounds), mixed with Group III-V compounds, and Group II ( A or B) is mixed with a group VIA element (a group 11-VI semiconductor compound) and a group vi compound. Examples include gallium (GaAs) 'indium gallium arsenide (GalnAs), aluminum gallium arsenide (GaAlAs), scaled marriage (InP), cadmium sulfide (CdS), cadmium mercury telluride (CdHgTe), zinc selenide, Petrochemical zinc sulfur (ZnSSe) and other similar materials. However, the single crystal semiconductor layer 26 may also include other semiconductor materials, metal or non-metal materials, for use in forming semiconductor structures, devices, and / or integrated circuits. The long auxiliary buffer layer 28 according to the present invention is preferably a silicon oxide. Strain in the buffer layer 24. At this point, the atomic layer in the crystal lattice is lightened, and the substrate 22 grows on the interface 22 of the interface. The amorphous oxide is formed by oxidizing the substrate 22, and it is more preferable that the thickness of the interlayer 28 is reduced enough to cause the substrate 22 to mismatch with the co-constant (generally in the range of about 0.05 to 5.0 nm). The lattice constant used refers to the distance between f in the crystal plane of the surface. If this strain is not supplemented by the middle, the strain will cause the crystal structure of the auxiliary buffer layer to be suitable for this paper. ) A4 specification (210 X 297 public reply) — 513774 A7 --------- B7 V. Description of the invention (7) ~ — Defects in the crystal structure of the lack of the auxiliary buffer layer will make the single crystal semiconductor layer 26 It is difficult to achieve a crystalline structure. The single crystal semiconductor layer 26 may include a semi-annual plate material, a compound semiconductor material, or other types of materials, such as metal or non-metal. The appropriate sample layer 30 material will be described below. Appropriate The material of the template layer is chemically bonded to the surface of the auxiliary buffer layer M at the selected position, and provides the position required for the polynuclear reaction of the epitaxial growth of the single crystal semiconductor layer 26. In use, the template layer 30 has about i to About 10 monolayers thick Fig. 2 is a sectional view showing a part of a semiconductor structure 40 according to another embodiment of the present invention. The structure 40 is similar to the previously proposed semiconductor structure 20, except that the additional buffer layer 32 is located on the auxiliary buffer layer 24 and (Single crystal semiconductor layer) 6. In particular, the additional buffer layer is located between the template layer 30 and the underlying semiconductor layer 26. When the single crystal semiconductor layer 26 includes a semiconductor or compound plate conductor material, the additional buffer layer is preferably composed of a semiconductor or compound plate conductor material to provide an auxiliary buffer layer whose lattice constant cannot sufficiently match the underlying early-crystal semiconductor or Crystalline compensation in the compound semiconductor material layer. The substrate 22 is a single crystal substrate, such as a single crystal silicon or gallium arsenide substrate. The characteristics of the crystal structure of a single crystal substrate are determined by the lattice constant and lattice orientation. In a similar manner, the auxiliary buffer layer 24 is also a single crystal material, and the crystal lattice of the single material is determined by the lattice constant and the lattice orientation. The lattice constants of the auxiliary buffer bank and the single crystal substrate must be closely matched together. Θ, or when the crystal orientation is rotated relative to other crystal orientations, ... . In this manual, "must match" inch must ’’ must match -10-513774 A7

The word “matching” is that there is enough similarity between a and chengsheng t, so that the high-layer body grows on the bottom thin layer. Figure J 疋 is a graph showing the thickness of the crystal; ^ v 広, 、, 曰, 日, 日, 口, 口, 口, 成长, 成长, 成长, the growing crystal layer, y, the main crystal and the growing crystal, the crystal 袼 constant does not match the relationship, and now Household library θ $ | n 仏 丄 match w 厗 degree 疋 ⑮ is a function that does not match between lattice constants 42 means that Gao Shishi said σ so 丄 丨 Baitian, · Fruit =, the boundary of the material 'curve 42 $ field It means "" the layer of the defect. If there is no mismatch, in theory, it is possible to grow an infinitely thick and high-quality worm crystal layer on the main crystal. 1 ¾ Amplifier with the mismatch of the crystal constant i can be achieved And the thickness of the high-quality crystalline layer will decrease rapidly. As a reference point 'for example' ±. If the lattice constant mismatch between the main crystal and the growing crystal is greater than about 2%, it is impossible to achieve more than about 2 ^^ Single crystal stupid layer. According to the embodiment of the present invention, the substrate 22 is a (100) or (111) oriented single crystal silicon wafer, and the auxiliary buffer layer 24 is a BS TO layer. The crystal orientation is rotated 45 ° relative to the crystal orientation of the silicon-based wafer to achieve these two types. The lattice constants between the materials must be matched. Included in the structure of the amorphous intermediate layer 28, that is, the silicon oxide layer of this example, if it has a sufficient thickness, is used to mitigate the Unmatched strain between the lattice constants of the main crystal and the growing crystal. As a result, according to the embodiment of the present invention, a high-quality and thick single crystal BSTO layer can be achieved. For other reasons, this is an advantage because it is considered as a phase shift The characteristics of the BSTO layer for the device will be affected by the crystallinity of the thin layer. Generally, as the crystallinity of the BSTO improves, the adjustability will also increase. The single crystal semiconductor layer 26 is a single crystal material grown by stupid crystals' and Crystal material also-11-This paper size meets China National Standard (CNS) A4 size (210 X 297 mm) 513774 A.7

It is determined by the lattice constant and crystal orientation. The lattice constant of the crystalline semiconductor layer 26 is the same as that of the substrate 22, which is often the same as the high adhesion a σ w in the early-epitaxially grown single crystal layer. The quality is ... the auxiliary buffer layer must be high — ° " Furthermore, in order to achieve the "crystal" of the single crystal semiconductor layer 26, "the lattice constants between the main crystal and the growing crystal are two," the single crystal auxiliary buffer layer and the growing crystal. The positive + is relative to the orientation of the main crystal. Rotate the material taken out of the post by Guangyou to transfer the crystal orientation of the long-form crystal. Mosquito must reach this lattice constant to match I. For example, if the growing crystal is; Zinc or selenide and sulfur, and if the auxiliary buffer layer is single crystal SrzBai.zTi〇3, the μ matching of the lattice constants of the two materials is achieved, where the crystal orientation of the growing layer is relative to the orientation of the main single crystal oxide. Similarly, if the main material is _ or barium, or acid or barium, or barium tin oxide, and the compound semiconductor layer is indium phosphide or indium gallium arsenide or indium aluminum arsenide, Crystal layer can be grown by rotation relative to the main oxide crystal The orientation is 45 °, and the crystal lattice constant must be matched. In some cases, a crystalline semiconductor auxiliary buffer layer between the main oxide and the growing single crystal material layer can be used to mitigate the growth that will cause small differences in lattice constants. Strain in the single crystal material layer. Better crystal quality in the grown single crystal material layer can thus be achieved. Figure 4 shows a high-resolution transmission electron microscope (TEM) of a semiconductor material manufactured according to an embodiment of the present invention. Single The crystalline SiTi〇3 auxiliary buffer layer 24 成长 grows out of the substrate 2 every 7 days. During the growth process, the formation of the amorphous interface layer 2 8 ′ will relieve strain due to lattice mismatch. Then use the template layer 30 In the epitaxial manner, a GaAs compound semiconductor layer 26 is grown. -12- This paper size is in accordance with the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 513774 5. Description of the invention (10. Figure 5 shows the inclusion of GaAs The structure of the single crystal layer 26 includes a GMs single-crystal auxiliary buffer layer. The GaAs layer has a λ r λ 1 layer on the silicon substrate 22 with a read layer 24. The peak of the spectrum indicates the auxiliary buffer layer 2 GaAs The physical semiconductor layer 26 is a single crystal and is (100) oriented. Using the method described above and adding an additional buffer layer deposition step, the structure shown in Fig. 2 can be formed. Auxiliary buffer layer 疋 is used to deposit a single crystal Before the material layer

’Is formed by covering the template layer. If the auxiliary buffer layer is a single crystal material including a semiconductor superlattice of a compound, the seed superlattice material can be deposited on the template f using MBE '. If the auxiliary buffer layer is a single crystal material of a germanium layer, then the above method is modified to cover the single crystal layer of the titanate with the last indium or titanium layer, and then deposit the wrong and react with the lock or titanium. A germanium-assisted buffer layer is then deposited directly on the template layer. The following non-limiting illustrative examples show different combinations of materials according to other embodiments of the invention, useful for structures 20 and 40. Example 1 According to an embodiment of the present invention, the single crystal substrate 22 is a silicon substrate, and the orientation is in the (100) direction. For example, the Shi Xi substrate may be a silicon substrate generally used to fabricate complementary metal-oxide-semiconductor (CMOs) integrated circuits with a diameter of about 300-300 mm. According to the embodiment of the present invention, the 'auxiliary buffer layer 24 is a single layer of SrzBaKzTi03' where z ranges from 0 to 1. The z value is selected to obtain one or more lattice constants closely matching the lattice constants of the semiconductor layer 26 to be formed subsequently. The auxiliary buffer layer has a thickness of about 2 to 1,000 nanometers (nm), and preferably has a thickness of about 1,000 rim. Generally, it is necessary to have a sufficiently thick auxiliary buffer layer to insulate the semiconductor layer and the substrate to obtain the required electrical-13. This paper size is applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) 513774 A7 B7 V. Description of the invention (11) and optical characteristics-. According to an embodiment of the present invention, the amorphous intermediate layer 28 is a silicon oxide (SiOy layer) formed on an interface between a silicon substrate and an intermediate auxiliary buffer layer. The intermediate layer 28 has a thickness of about 0.5-5 nm, And preferably, it has a thickness of about 1 to 2. According to an embodiment of the present invention, the single crystal layer 26 is a compound semiconductor layer of gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs), and the thickness is about 1 nm to about 10. 0 micron (V m), and preferably a thickness of about 0.5 vm to about 10 #. The thickness is generally dependent on the application to prepare the thin layer. To facilitate the oxidation of gallium arsenide or aluminum gallium arsenide in single crystal An epitaxial layer grows on the surface and forms a template layer on the oxide layer. The template layer is preferably a single layer of 1-10 Ti-As, Sr_〇-As. Using a better example, 1- 2 A single layer of Ti-As or Sf-Ga-〇 has been shown to successfully grow a GaAs layer. Example 2 This embodiment of the present invention is an example showing the structure 40 shown in Figure 2. Substrate 22, auxiliary buffer layer 24 and the single crystal semiconductor layer 26 may be similar to those described in Example 1. In addition, the additional buffer layer 32 is used to reduce the crystal size due to the auxiliary buffer layer. Any strain caused by the mismatch of the crystal lattice of the semiconductor material. The auxiliary buffer layer 32 may be a germanium layer or a GaAs layer, aluminum gallium arsenide (A1GaA0, indium gallium phosphide (InGaP), aluminum gallium phosphide ( AiGap), indium gallium arsenide (InGaAs), indium aluminum phosphide (AllnP) 'gallium arsenide phosphide (GaAsp) or indium gallium phosphide (InGap) strain-compensated superlattice. According to the characteristics of the present invention, the buffer layer 32 Including GaAS \ P ^ Super

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V. Description of the invention (12th Japanese grid 'where x value is in the range of 0 to 1. β according to another-characteristics' buffer layer 32 includes InyGal' vp superlattice, in which gifts are in the range of 0 to 1. Borrowing changes Ky, let the lattice across the superlattice be changed from bottom to top to generate a lattice constant match between the bottom oxide and the bottom single crystal material, where the bottom oxide in this embodiment should be the bottom early crystal material It is a compound semiconductor material. The composition of the compound semiconductor material, as described above, can be similarly changed to control the auxiliary buffer layer ": Lattice constant. The superlattice can have a thickness of about 50_500, and it is best厚度 Approximately 100-200 nm in thickness. = On the one hand, the buffer layer 32 may be a single crystal of the -thickness layer. 'The thickness is preferably about 2-20 nm. When using the wrong auxiliary buffer layer, it is about monophonic ^ The germanium-pin (Ge-Sr) or germanium-titanium (Ge_Tl) # plate layer can be used as a polynuclear site: 'For subsequent growth of a single crystal material layer, the single crystal material is in the solid compound semiconductor material. Oxidation is formed. The layer is 卞 ... En 疋 Ti 2: Subsequent deposition of a single crystal is used. Single layer or titanium Water core position, where the first single layer of germanium can be bonded. The sample layer of this structure can be the same as described in Example 丨 Example 3 Substrate 22 This example also shows the useful materials in the structure shown in Figure 2 〇 Auxiliary buffer layer 24, single crystal material layer 26 and template layer 30. In addition, 'extra buffer layer 32 is inserted between the auxiliary buffer layer and the bottom single layer = material Γ layer 32' is in this example a semiconductor material: An early wrestling can be, for example, Kunhua indium gallium, phosphide. The involute layer according to another feature of the present invention is an additional buffer layer 32 • 15- B7 5. Invention description (13) includes InGaAs :, of which indium The composition is changed from 0 to 50%. The buffer layer preferably has a thickness of about 10-j0 nm. The composition of the buffer layer is changed from GaAs to InGaAs to provide a layer between the single crystal oxide material and the single crystal material cover layer The lattice matching of this single crystal material cover layer is a compound semiconductor material in this example. This buffer layer is particularly useful if there is a lattice mismatch between the auxiliary buffer layer 24 and the single crystal material layer 26. The following example shows According to an embodiment of the present invention, Method for fabricating tunable structures, such as those shown in Figures 丨 and 2. The method begins by providing a single crystal semiconductor substrate including silicon or germanium. According to a preferred embodiment of the present invention, the semiconductor substrate is silicon crystal Round, with (100) orientation. The substrate is preferably directed to the axis ~ or the surface is more than about 4 o from the center of the axis. At least a part of the semiconductor substrate is a bare surface, although other substrates, The structure of the dagger is included as described below. The term "naked" in this specification means that the surface of the base portion has been cleaned to remove any oxides, 'wood or foreign materials' . As is well known, bare silicon is highly reactive and can form raw oxides at any time. The term "naked" is meant to include the original oxide of the species. Thin silicon oxide can also be grown on semiconductor substrates, although such a grown oxide is not necessarily required for this method in accordance with the present invention. ^ After epitaxial growth of a single crystal oxide layer, covering the single crystal substrate, the original oxide layer must be removed first to expose the crystal structure of the underlying substrate. The following methods are preferably performed using molecular beam epitaxy (mbe), although other epitaxy methods can also be used in accordance with the present invention. In the MBE device, you can first use thermal deposition to deposit a thin layer of barium, a layer of barium or a combination of lock and lock, or other alkaline-earth metals or combinations of alkaline-earth metals to remove ^ -16- 513774 A7 B7

V. Description of the invention (14 Then the substrate should be heated to a temperature of about 850 ° C. # 思 疋 Use to reduce the oxidized stone while leaving the original oxide. If gills are used, then 'total the original oxide layer The surface containing no silicon oxide under the reaction. The final surface with the 2 × 1 structure is composed of tritium, oxygen, and silicon. The 2x1 structure is arranged to form a template layer, which is used to coat the single-crystal oxide layer that grows sequentially. The template layer provides the necessary Chemical and physical properties are used for polynucleation of the crystalline growth of the cover layer. According to another embodiment of the present invention, the original silicon oxide is transformed, and the surface of the substrate can be prepared for growing a single crystal oxide layer, using MBE at low temperature Alkaline earth metal oxides, such as hafnium oxide, barium yttrium oxide, or barium oxide, are deposited on the surface of the substrate, and the structure is subsequently heated to a temperature of about 85 ° t. At helium, oxidation occurs between the oxide and the original oxide. The solid state reaction reduces the original oxide and leaves a residue on the surface of the substrate. The 2x1 structure of oxygen and silicon is left behind. Once again, a template layer is formed for subsequent growth of the aligned single crystal oxide layer. After the silicon oxide is removed from the surface of the substrate, according to an embodiment of the present invention, the substrate is cooled to a temperature in the range of 200-80 (rc), and a non-beam beam stupid crystal is used to form a hafnium titanate layer on the sample layer. The MBE method is to open the shield in the MBE device to expose radon, and the source of oxygen and silicon starts. The ratio of radon to titanium is about 1: 1. The partial pressure of oxygen is set to a minimum at the beginning in order to grow the chemical Measured titanate gills, the growth rate is about 03_0.5 nm per second. After the growth of lutetium titanate begins, the partial pressure of oxygen is increased to a minimum value. Excessive pressure of oxygen will cause the underlying substrate and growing titanium An amorphous oxide layer is grown between the acid gill layers. The silicon oxide layer grows because the oxygen will diffuse through the total growing titanic acid layer to the interface where oxygen will react with the silicon on the underlying substrate surface. This paper Standards apply to China National Standard (CNS) A4 specifications (210X 297 mm)

The titanate is a single crystal that grows in a row, and it is said that the arrangement of the 2 × 1 crystal structure of the sunward position with respect to the underlying substrate is Hanler 4 s. …, The strain existing in the thorium titanate due to the small mismatch of the day-to-day lattice coefficient between the silicon substrate and the growing crystal will be relieved in the amorphous silicon oxide intermediate layer. When the titanic acid reaches the required thickness, the single crystal titanic acid is covered by the sample layer, and the 5 xuan sample layer is used for the worm crystal layer that subsequently grows the required single crystal material. For example, 'for Shi Shenhua's subsequent growth of a single-crystal compound semiconductor material layer', with 1-2 single-layer titanium ', a 1- and 2-single-titanium titanium-lice or 1-2 strontium, said earlier this morning. Oxygen to stop the growth, and can be covered with the single crystal layer of acetic acid grown by MBE. After the cap layer is formed, the deposits are deposited to form Ti_As bonding, Ti_〇_As bonding, or SrOAs bonding to yttrium. Any of these will form a suitable template layer, > Gaia will form a gallium arsenide single crystal layer. After the formation of the template layer, gallium will be subsequently added to the reaction form of "Shen" and iridium arsenide. Another way is that gallium can be deposited on the back layer to form an Sr-0-Ga bond, and arsenic and gallium will follow Adding 'to form GaAs. The above method explains a method of forming a semiconductor structure "The semiconductor structure includes a silicon substrate, covering an oxide layer and a single crystal material layer, and the single crystal material layer includes arsenization using a molecular beam epitaxial process Gallium compound semiconductor layer. This method can also use chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD) 'Migration Enhanced Epitaxial (MEE), Atomic Layer Epitaxial (ALE), Physical Vapor Deposition (PVD), Chemical Solution Deposition (CSD), pulsed laser deposition (PLD), or similar processes. In addition, by using similar methods, other single crystal auxiliary buffer layers can also be grown, such as the alkaline earth gold titanate, zirconate, hydrochloride, phosphonate, ruthenate, ruthenate, Pelovsgai-18- This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 public love)

Special oxides' such as alkaline earth gold lanthanum, Fu Qiao'er, Bekou / Fufuste special oxides, aluminate two steels and T 2 sulfide I. In addition, using a similar method as _, the half = ΓΓ: 1; 1, and 1- compounds to the semiconductor material layer, and cover the single-crystal oxide auxiliary buffer layer. Each change of the single crystal material layer and the single crystal oxide auxiliary buffer layer is provided with a suitable sample layer 'for starting to grow the single crystal material layer. For example, „The buffer layer is a gold salt of the gold group, and the oxide is a thin layer. The sand or scales are deposited immediately after the hammer is deposited to react with the hammer as a precursor ' Indium arsenide, indium aluminum arsenide, or indium phosphide were deposited separately. Similar 'if the auxiliary buffer layer is an alkaline earth gold osmium salt, the oxide is covered by a thin rhenium layer. Immediately after the erbium is deposited, The "shen or li" is deposited to react with the scab that acts as a precursor, and the layers of Shishenhua Indium, Shisinhua and Indium Phosphide are grown respectively. In a similar way, gill titanate can be covered with a layer of barium or s -Layers of barium and oxygen. Each deposition can be followed by the deposition of stone or stone gangue, which reacts with the covering material to form a template layer, which is used to deposit single crystal material layers, such as indium bell i, indium bell This compound semiconductor is shown in FIG. 6 or indium. Fig. 6 A-6D shows the formation of an adjustable structure 50 according to another embodiment of the present invention in a sectional view. As described above with reference to the embodiments of Figs. An embodiment of the invention involves a method of forming a flexible substrate using single crystal oxidation The epitaxial growth of the object, such as forming the auxiliary buffer layer 24 and forming the template layer 30 described above with reference to FIGS. 1 and 2. However, the embodiment in FIGS. 6A-6D uses a template layer including a surfactant to facilitate layer alignment. Layer of single crystal material grows. -19- This paper size applies to China National Standard (CNS) A4 (210X 297mm)

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Turning now to FIG. 6A, the amorphous intermediate (θθ, ψ ς, ', T gate layer) 8 is grown to the boundary between the substrate 52 and the growing intermediate buffer layer 54 (the bottom layer) (2), On the other hand, the amorphous intermediate layer 58 is formed by oxidizing away the substrate 52 during the period when the intermediate buffer layer 54 is grown. In the middle, for example, the single crystal η of snzT103 is equal to the premature early-crystal oxide layer, where the range of 2 is 0 to 1. However, the intermediate buffer layer 54 may also include any of the compounds described in the reference layer 94 of FIGS. 1 and 2. Τ The intermediate buffer layer 54 is grown with a 镙 (sr) stopper, and a stop surface is formed. The stop surface 表面 is indicated by the hatched line 55 in FIG. 6A, and then the template layer 6 is added. It includes a surfactant layer 61 and a cover layer as shown in FIGS. 6B and 6C. . The surface active agent layer may include elements such as A1, In |% Ga, but it is not limited to this, but depends on the composition of the intermediate buffer layer 54 and the cover layer of the single crystal material to obtain the best results. In a typical example, it is used to act as a surfactant sound 6! 'And to change the surface and surface energy of the intermediate buffer layer 54. The surface = agent layer 61 is preferably on the intermediate buffer layer 54 shown in FIG. 6B. The molecular beam worm crystal (MBE) 'worm crystal is grown to the thickness of one or two single layers, although other epitaxial methods can be performed. 'Including chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), migration enhanced worm crystal (mee), atomic layer worm crystal (ALE)' Physical vapor deposition (PVD), chemical solution deposition (csd) :: Laser Laser Deposition (PLD) or similar process. The surfactant layer 61 is then exposed to a halogen such as arsenic, for example, to form a cover layer 63 as shown in FIG. 6C. The surfactant layer 6m may be exposed to materials such as As, P, Sb, and N elements to generate the cover layer 63, but is not limited thereto. The surfactant layer 61 and the cover layer. Combined with -20, this paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ------------ 513774

Arises to form a template layer 60. Then, a single crystal semiconductor layer 66, which in this example is a GaAs compound semiconductor, is deposited through MBE 'CVD, MOCVD, MEE, ALE, PVD, CSD' PLD or similar processes to form the final structure shown in Fig. 9D. FIGS. 7A-7D show possible molecular bonding structures of the characteristic 疋 compound semiconductor structure 50 formed in accordance with the embodiment of the present invention in FIGS. 6A-6D. More specifically, Figs. 7A-7D show the growth of GaAs (single-crystal semiconductor layer 66). On the terminating surface of the pin-titanate doped single-crystal oxide (intermediate buffer layer 54), a surfactant-containing template layer ( Template layer 6 0). A single crystal semiconductor layer 66, such as GaAs, is grown on the intermediate buffer layer 54 such as an amorphous intermediate layer 58 and the titanium hafnium oxide on the base layer 52, and both the amorphous intermediate layer 58 and the base layer 52 are grown. Including the previous reference figure! The material of the amorphous intermediate layer 28 and the base layer 22 in 2 shows a limit thickness of about 10 Angstroms, in which one-dimensional (2D) and two-dimensional (3D) growth will be due to the surface involved Change with energy. In order to achieve a true layer-to-layer growth method (Frank Van der Mere growth method), the following relationship must be satisfied: s STO > (5 INT + δ GaAs) where the surface energy of the single crystal oxide layer 54 must be greater than The surface energy of the amorphous intermediate layer 58 among the surface energy of the eighty-three layers 66. Since it is not practical to satisfy the equation, a template layer containing a surfactant is used, as shown in FIGS. 6B-6D, to increase the surface energy of the single crystal oxide layer 54 and transform the crystal structure of the template layer into Diamond-type structure compatible with the original GaAs layer. Figure 7A shows the molecules on the lithium-terminated surface of the gill titanate single crystal oxide layer-21-This paper is in accordance with the Chinese National Standard (CNS) A4 specification (210X297) -------- 5. Description of the invention (19-bond structure. The aluminum surfactant layer is deposited on top of the terbium termination surface, and together with the surface shown in Fig. 7B; the surface bonds, ,,, and so on, will react to form a single-layered covering of AhSr, Αασ, ι 盍 layer This early layer AhSr has a molecular bond structure as shown in FIG. 7B, the points + green &. ,,, α 冓 S form a diamond with a sp-terminated surface and compatible with its compound semiconductor Type structure. Qian this knot ". Into As'" as shown in Fig. 7C. AiAs layer is deposited afterwards, and the molecular bond obtained by the growth method shown in Fig. 7D is completed. GaAs can grow to any thickness to form other semiconductor junctions or integrated circuits. For example, the alkaline earth group metals in group IIA are: :: Take a good cover to form the covering surface of the single crystal oxide layer 24, because it can form It has the required molecular structure. In this example, the 'surfactant-containing template' The layer will help the formation of a flexible substrate 'for the monolithic accumulation processing of different material layers including III-V compounds to form an A-quality semiconductor structure' device and integrated circuit. Figure 8-10 is shown in a sectional view The formation of the adjustable structure 1GG according to another embodiment of the present invention. This embodiment includes a flexible layer that functions as a transfer layer. The transfer layer uses clathrate or Zintl-type bonding. Structure 100 includes an intermediate metal template layer to reduce the surface energy at the interface of the material layer, thereby providing a two-dimensional thin layer through the growth of the thin layer. The structure 100 shown in FIG. 8 includes a single crystal substrate 102 and an amorphous interface. Layer and auxiliary buffer layer 104. The amorphous interface layer 108 is grown on the substrate 102 on the interface between the substrate 102 and the auxiliary buffer layer 104, as previously referred to FIG. 2. Amorphous Interface layer} 〇8 may include any of those previously shown in Figures 1 and 2 of the amorphous interface layer 28, but preferably includes single crystal oxygen-22-513774

AT ____B7___ 5. Description of the Invention (20) A single crystal layer of a chemical material, such as SrzBaNzTi03, where z ranges from 0 to 1. The substrate 102 is preferably Shi Xi 'but may also include any of those compounds of the substrate 22 described above. The template layer 130 is deposited on the auxiliary buffer layer 104, as shown in FIG. 9, and preferably includes a thin layer of a Zintl type phase material, including metals and metalloids having a large number of ionic characteristics. As shown in the above embodiments, MBE, CVD, MOCVD, MEE, ALE, PVD, CSD, PLD, or similar processes can be used to form the template layer 130 to achieve a single layer thickness. The function of the template layer 130 is to treat ‘soft twelve layers’ with non-directional bonding but high crystallinity, which will absorb the stress established between the lattice mismatched layers. The material of the template layer 130 may include materials containing Si, O &, In, and Sb, such as AlSr2, (MgCaYb) Ga2, (Ca, Sr, Eu, Yb) In2,

BaGe〗 As and SrSnzAs], but it is not limited to this. The single crystal material layer 126 is epitaxially grown onto the template layer 130, and the final structure shown in FIG. A specific example is that the SrAl2 layer can be used as a template layer π0 'while a suitable single crystal material layer 126 such as a compound semiconductor material GaAs is grown on SrAh. Al-Ti (from the auxiliary buffer layer of SrzBakTiO; where the range of z is 0 to 1) the bonding is mostly metallic, while Ai-AS (from the GaAs layer) bonding is very weak Price key. Sr participates in two independent types of bonding. Its electrical charge is toward the oxygen atom including the auxiliary buffer layer 104 under SrzBabzTiC ^ to participate in the ionic bonding, while the other covalent charges are carried out with general Zintl-type phase materials. The amount of charge transfer that is assigned to a is determined by the relative anions of the elements including the template layer 130 and the atomic distance. In this example, it is assumed that A1 is a mixture of sp3 and will be mixed with the single crystal material layer at any time. -23- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public directors) "-

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513774 A 7 _ —___ B7 V. Invention May (No. 21 Plant " " "-" 126 forms a bond, which in this example includes the compound semiconductor material GaAs. Using this embodiment order The Zlntl-type sample layer, which generates a flexible substrate, can absorb a large amount of strain without having too much energy. In the above-mentioned example, the volume of the SrAl2 layer was changed to adjust the bond strength of A1, and then manufactured. The application-specific adjustable devices include monolithic III-V group and Si devices, and monolithic low-value dielectric materials for CMOS technology. Figure 11 is a cross-sectional view. A part of the tunable structure 110 according to the embodiment of the present invention is shown. The structure 110 is a structure similar to the above, wherein the silicon structure 1 1 10 includes a single crystal semiconductor substrate L1 2, the single crystal buffer layer 124 and the single crystal semiconductor 俨The layer 126. In addition, the tunable structure 110 can also be formed by using any one of the embodiments shown in FIGS. 1-10. The semiconductor substrate 112 can include any of the materials suitable for the tunable structure described above, such as a monocrystalline wafer. Buffer layer 1 24 includes any suitable The material for the adjustable structure includes any of the above materials. In a specific embodiment, the buffer layer 124 includes part of barium titanate thorium (BSTO), because BSTO has some good characteristics (such as low dielectric loss, good high Frequency characteristics (good thermal stability). In a specific embodiment, the BSTO layer 124 may be doped with a suitable material to further improve the tunability or phase shift characteristics. For example, an oxide ball (Mg〇) may be used in combination with BSTO to use In the application of different antenna systems including frequencies in the microwave and millimeter wave ranges, but is not limited thereto. In another feature of this embodiment, the BSTO layer 124 may be doped with oxide (ZnO) for use including multiple layers. Capacitors, Capacitors-Variable Resistors, Non-volatile-24- A7 A7

V. Description of the invention In the application of the computer memory and the phase array system, it is not limited to this. It should be understood that the buffer layer 1 and the BST0 layer 1 2 4 in this particular embodiment may be pure or doped depending on the desired application. Besides, except

Besides MgO and ZnO, you can also

Use different other materials as impurity replacement with BSTO. For example, some other materials that can be combined with BST0 are suitable, including hammer alumina 'alumina and silica, but are not limited thereto. The semiconductor layer ⑶ includes an appropriate semiconductor material, is used, and may include any of the above-mentioned materials. In a particular embodiment, the bulk layer 126 is stable-a layer of a group of m_v semiconductor materials such as a g-center. The structural further step includes one or more electrical devices', which are represented in schematic form by dashed lines 13 1 ′ 132 and 134. The electrical devices are generally indicated by dashed lines 131 and are formed on at least a portion of the substrate 112. Electrical device η] can be a resistive 'capacitance' active semiconductor component 'such as a diode or transistor or integrated logic unit or a circuit element such as a CMOS integrated circuit, and it is known and widely used in the industry Formed using conventional semiconductor processes. For example, the electrical device 131 may be a circuit that controls the supply center to the adjustable structure. The semiconductor device 132 is formed in at least a part of the compound semiconductor layer 126. The semiconductor device 132 may be formed using conventional process steps used to manufacture a GaAs or other compound semiconductor material device. The device 3 is preferably an active component, such as a device that generates an RF signal. Can be formed by solid lines 135, 136 and 237 as a schematic representation of the conductor, and the device is electrically used -25- This paper size applies to the Chinese national standard A4 specifications (210 X 297 mm) 513774 A7-B7 V. Description of the invention (23) 13 1, 132, and 134 are coupled to the phase shift layer 124. Therefore, a fully integrated tunable structure is realized, including at least one component formed in a single crystal compound semiconductor layer and a plurality of components formed in a silicon substrate. Another electrical device, generally indicated by dashed lines 1 3 4, is formed on a substrate 12 using conventional Shixi device processing techniques. Alternatively, the device 134 may be formed on the semiconductor layer 126. The device 134 may include any suitable input / output unit 'ratio antenna or similar device. An insulating material layer 138, such as a silicon dioxide layer or a similar material layer, can be covered on the electrical components 1 31, protecting the underlying components from the environment, and avoiding short circuits inside the structure. It is to be noted that a similar layer of insulating material may cover the electrical devices 132 and 134. In fact, electromagnetic waves (usually very high frequencies) are generated in the RF unit 132 and are coupled to the BSTO layer 124. The electromagnetic wave passes through the 8 § 〇 layer 124 at a rate determined by the dielectric constant of a medium such as BST04-doped BSTO. The dc voltage generated by the digital circuit 丨 31 can be applied to change or change the number of "packages" of the material. When the dielectric constant changes, the length of the electrical period of the material also changes. Therefore, as the electromagnetic wave passes through: 88 〇 layer 124, the phase of the electromagnetic wave will be effectively changed (displaced). Appropriate input / output components 134, such as antennas, will be coupled to the BST0 layer 124 in order to transmit / receive the phase-shifted electromagnetic wave. Figure 12 shows A typical arrangement of a phased array antenna system 140 having a plurality of adjustable structures 145 according to the present invention is provided. The column and row driving circuits 15 and 52 are units for controlling the core voltage to the phase shift unit and controlling the radiation pattern of the antenna. System 140 -26- A7 B7 V. Description of the invention (24) Useful for many applications, such as antenna tracking. Very specific examples of structures with compound semiconductor parts and ϊν group semiconductor parts, are used to show | The embodiments of the present invention are not intended to limit the present invention. There are many other combinations and other embodiments of the present invention. For example, the present invention includes a structure for manufacturing a material layer to Method, the material layer is to form a semiconductor structure, a substrate, and an integrated circuit, and the integrated circuit is another thin layer including, for example, metal and non-metal layers. More particularly, the present invention includes forming a compatible substrate and material The structure and method are suitable for manufacturing those structures, devices, and integrated circuits. By using the embodiments of the present invention, it is now easy to integrate devices including a single crystal layer, which includes a semiconductor and Compound semiconductor materials and their daggers can be used to form layers of materials for devices with other components that are well-manipulated or easily and / or cheaply formed in semiconductor and compound semiconductor materials. Reduce, reduce manufacturing cost, and increase yield and reliability. In the above description, the present invention has been described with reference to specific embodiments. However, those skilled in the art will understand that it is possible to apply for a patent without departing from the following: Under the scope of the invention mentioned in the scope, different modifications and changes are made. Therefore, 'Explanation content and drawings Illustrative rather than restrictive 'and all of these modifications are included within the scope of the invention of the board. Specific embodiments have been described with respect to advantages, solutions to other advantages and problems. However, advantages, other advantages and The solution to the problem 'and any other advantages and solutions that will cause advantages or -27- This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 513774 A7 B7 V. Description of the invention (25) The units that become more emphasized are not intended to constitute strict, required or necessary features, or any or all of the elements of the patent application scope. As used herein, "includes", "includes", or other altered uses Words are intended to cover non-exclusive content, so that processes, methods, literature, or equipment that includes a series of units will not include only those units, but may include those that are not explicitly listed or include dependencies on this A process, method, document, or other unit of equipment. -28- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

A8 B8 C8 '— ____D8 ^ ___ Patent scope ~ Kinds of phase-tunable structures, including grass-grass substrates; single crystal layers formed on the substrate, the single crystal layers including materials with different adjustable dielectric constants; sample objects , Formed on the single crystal layer; a single crystal semiconductor material covering the sample; an active semiconductor device, at least in part, is formed in the single crystal semiconductor material and coupled to the single crystal layer; and an electrical device, at least in part It is formed in the substrate and is coupled to the single crystal layer. For example, the phase adjustable structure of the first patent application scope, wherein the sample object includes a transparent phase material. For example, the phase tunable structure in the second item of the patent application, wherein the permeation-type phase material includes at least one of SrAi2, (MgCaYb) Ga2, (Ca, Sr'Eu'Yb) In2. For example, the phase-tunable structure in the first item of the patent application range, wherein the layer includes a single crystal layer of ^ BakTiO3, where the range of z is 0 to 1, the sample object includes SrAL and the 3x single crystal material layer includes GaAs. The female Shen Qiao patent scope item 1 phase adjustable structure, wherein the sample object includes a surfactant material. For example, the phase-adjustable structure of item 5 of the patent application scope, wherein the surfactant includes at least one of Al and Ga. For example, the phase-adjustable structure of item 5 of the patent scope is claimed, wherein the model object further includes a cover layer. -29- A B c D The scope of patent application for women's claim The phase-adjustable structure of item 7 of the patent claim, wherein the covering layer is formed by exposing the surface / tongue biomaterial to the covering induction material. 9. The phase-adjustable structure as claimed in item 7 of the May patent scope, wherein the overlay sensing material includes at least one of As, P'Sb, and N. ^ Phase-adjustable structure in item 7 of the declared patent scope, wherein the surface-active 刎 G includes A! '5 Xuan cladding layer includes Al2Sr, and the single crystal material layer includes GaAs 〇11. As in the scope of patent application item 1 A phase adjustable structure, wherein the template includes a fragment. 12 The phase-adjustable structure according to item 11 of the patent application scope, further including a covering layer. 1J The phase-adjustable structure according to item 1 of the patent application scope, further comprising an input / output device 'which is electrically coupled to the single crystal layer. 14_ The phase adjustable structure according to item 13 of the patent application scope, wherein the input / output device includes an antenna. 15. The phase-adjustable structure according to item 1 of the scope of patent application, wherein the layer includes an oxide, which is selected from the free alkaline earth gold group titanate 'alkaline earth gold group zirconate, soil test gold private salt, soil test Groups of gold group salts, alkaline earth gold group ruthenates and test soil gold group niobates. 16. The phase-tunable structure according to item 1 of the scope of the patent application, wherein the layer includes a single crystal layer of complex SrzBa ^ TiOa, where the range of z is 0 to 1. 17. The phase-tunable structure according to item 6 of the patent application, wherein the layer includes a BSTO-MgO complex. 1 8 · If the phase adjustable structure of item 7 in the scope of patent application, the single crystal base -30- this paper size applies Chinese National Standard (CNS) A4 specifications (210 X 297 mm) A8 B8 C8 :: Includes Group IV materials, which is characterized by the first lattice constant of the conductive material zinc _ weekday noon and the one-day lattice constant of the younger brother, the second lattice constant is different from that of the first-lattice constant. 19. The compound of the scope of patent application is characterized by different lattice constants. The phase-tunable structure of item 18, wherein the single crystal oxygen lattice constant, and the third lattice constant and the 20th. The phase-tunable structure of item 17 of the Zhongli patent scope, wherein the single crystal a = bottom Is characterized by the first crystal orientation, and the single crystal oxide is characterized by the second crystal orientation, wherein the second crystal orientation is rotated relative to the first crystal orientation. 21. The phase-adjustable structure according to item 17 of the patent application scope, further comprising a second amorphous oxide layer formed between the group IV substrate and the single crystal oxide. 22. The phase-adjustable structure according to item 21 of the patent application, wherein the family substrate includes Shi Xi and the second amorphous oxide layer includes silicon oxide. 23. The phase-tunable structure according to item 1 of the scope of patent application, wherein the single crystal semiconductor material layer is a compound semiconductor material selected from the group consisting of: III-V compound 'mixed III-V compound , Η-νι compounds and mixed II-VI compounds. 24. The phase-tunable structure according to item 1 of the scope of patent application, wherein the single crystal semiconductor material layer includes a material selected from the group consisting of: GaAs ′ AlGaAs, InP, InGaAs, InGaP, ZnSe and ZnSeS. 25. The phase adjustable structure according to item i of the patent application scope, wherein the active device includes an RF component. -31-This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X 297 mm) 513774 A8 B8 C8 D8 VI. Application for patent scope 26 · Phase adjustable structure such as item 25 of patent scope, where the electrical device Including resistor, capacitor, diode, transistor, integrated logic unit or CMOS integrated circuit. 2 7. A phase shift structure, including: a single crystal silicon substrate; a single crystal doped barium strontium titanate (BSTO) layer formed on the substrate, barium titanate hafnium is expressed as BazSn.zTiC ^, where the range of z Is 0 to 1; and A single-crystal semiconductor layer is mounted on the BSTO layer. 28. The phase shift structure according to item 27 of the application, wherein the BSTO layer includes a composite of BSTO and Mg0 (oxidized town). 29. The phase shift structure of item 27 of the patent application scope further includes an RF component, a DC (direct current) circuit and an antenna, wherein the RF component, the DC circuit and the antenna are electrically connected to the doped BST0 layer. 3 0. A phase-tunable structure, including: a single crystal substrate;-a single crystal oxide material covering the substrate, the oxide material having a phase tunable characteristic; and a single crystal semiconductor material covering the single crystal Oxide material. 3 1. The phase-tunable structure according to item 30 of the patent application scope, further comprising a template layer 'formed between the early-crystal oxide material and the early-crystal semiconductor material. 3 2. The phase-tunable structure according to item 30 of the scope of patent application, wherein the single crystal oxide material includes a free soil test gold group titanate, a soil test gold group acid salt, and a soil test gold group acid salt , Alkaline earth metal group acid salt, earth metal group ruthenium-32-this paper size applies to Chinese National Standard (CNS) A4 specification (210 X 297 mm), patent application is-acid salt and metal group metal A group of sharp salts. ΊφPlease patent the phase-adjustable structure of item 3G in Patent No. 21. The single crystal oxide material in # includes a single crystal layer with 8 cores and 11 π. The range of 2 in 纟 is 0 to 1.0. Phase-adjustable structure of item 3Q, wherein the single crystal semi-bulk material includes a compound semiconductor material selected from the group consisting of a III-V compound 'mixed III-v compound, a π-vl compound and mixed II -Group VI compound. 35. The phase tunable structure of item 30 of the patent application scope, wherein the single crystal semiconductor material includes Kunhualu. j 6 · The phase-adjustable structure according to claim 30 of the patent scope, further including at least one electrical device 'is electrically connected to a single-crystal oxide material forming the integrated tunable structure. 37. A method for manufacturing a phase-tunable structure, comprising the steps of: providing a single-crystal semiconductor substrate including silicon; growing a single crystal phase-tunable oxide layer on the single-crystal substrate, and covering the single-crystal substrate; and A single crystal semiconductor layer is grown to cover the single crystal phase tunable oxide layer and cover the oxide layer on the single crystal substrate. 38. The method of claim 37, further comprising forming a template layer on the single crystal phase tunable oxide layer. 39. The method of claim 37, wherein the step of epitaxial growth of a single crystal phase tunable oxide layer comprises: heating the substrate to a temperature between about 400 ° C and about 600 ° C; and- 33- This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210 X 297 public directors) 513774 6. Scope of patent application A8 B8 C8 D8 Add reactants including gill 'titanium and oxygen. 40. The method of claim 37, wherein the step of growing a single-day semiconductor layer from a telecrystal includes the step of growing a worm crystal from a gallium layer. 3 said 4 1 · If the patent application is applied, the method of enclosing the item, wherein the step of forming a template layer includes the step of growing a surfactant layer. 42. The method according to the patent application, further comprising the step of exposing the surfactant layer to form a cover layer. 43. A method according to item 42 of the patent application, wherein the exposing step includes exposing the surfactant layer to the dentin. 44. For example, the scope of application for patent No. 42 The surfactant layer is exposed to the self-prime in the group. Method, which makes the exposure step include selecting 45. 46. 47. = consisting of free As, p, Sb, and n, the method of claim 38, in which the step of forming a template layer is included > Steps to accumulate a layer of transparent phase material. For example, the method in the 37th aspect of the patent application, the $ -step includes the step of forming an active device in the single crystal semiconductor layer ', which is electrically connected to the single crystal phase-tunable oxide layer. If the method of applying for a patent scope item 46, further comprises: forming an electrical device at least in a single crystal semiconductor substrate; and electrically connecting the electrical device to the single crystal phase adjustable oxide layer Paper standard suitable for financial 8 S home standard (CNS) A4 specification (21GX297 public director) β ----