511277 A7 B7 五、發明説明（1) 〔技術領域〕 本發明槪括地有關半導體積體電路，尤其是有關含有 用於調整用於取樣輸入信號之時鐘信號之相位之定時控制 電路之半導體積體電路。 〔背景技術〕 在數位信號之傳輸與再生中，爲採樣被接收或再生之 輸入信號而使用時鐘信號。此時，係根據輸入信號之轉移 點（transition point )產生具有適當相位之時鐘信號，或藉 由將輸入信號過取樣（over sampling)，並對一個取樣點產 生具有多個相位之多相時鐘信號，再由其中選擇具有適當 相位之時鐘信號。通常，爲減少電路規模與消費電力，而 選擇前者方式。以下針對前者之方式說明先前技術。 先前做法係產生時鐘信號俾檢測出輸入信號之轉移點 ，並使由該轉移點僅錯開位元周期之5 0 %之位置成爲取 樣點，並利用該時鐘信號採樣輸入信號。在此，如輸入信 號爲差動信號時，差動信號交叉之位置即相當於輸入信號 之轉移點。 然而，在傳輸或再生數位信號時，由於信號之傳輸路 上之浮動電容等而發生波形偏斜與不穩定，或在記錄再生 系統之符號間干擾等而發生波形偏斜或不穩定。當該等波 形偏斜或不穩定變大時，在先前之定時控制電路中，即不 易將將取樣點設定於最適當之位置。其狀況如第1至第3 圖所示。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐) Z " (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 511277 A7 _ B7 五、發明説明（2) 在第1圖至第3圖中，在差動輸入信號發生大的波形 偏斜或不穩定，構成差動輸入信號之正相輸入信號I n 1 與逆向輸入信號I η 2相交叉之位置不在一點上。如第i 圖所示，正相輸入信號I nl與逆相輸入信號I n2之電 位差整體上成爲最大之定時t 1至t 4爲最佳的取樣點。 但是，實際上，受到波形偏斜或不穩定性之影響，取樣點 會由最佳位置向前或向後錯開。例如，在第2圖中，取樣 點係根據正相輸入信號I η 1與逆相輸入信號I η 2交叉 最快之定時（Timing )而設定。另一方面，在第3圖中，取 樣點係根據正相輸入信號I η 1與逆相輸入信號I n 2交 叉最慢之定時而設定。 如上述，在先前之定時控制電路中，於大的波形偏斜 或不穩定性存在時，因爲構成差動輸入信號之正相輸入信 號I η 1與逆相輸入信號I η 2之電位差在取樣點變成最 小，因此，成爲容易發生錯誤之主要原因，而成爲問題。 〔發明之揭示〕 鑑於上述問題，本發明之目的在提供一種半導體積體 電路，其含有定時控制電路，在輸入信號發生大波形偏斜 或不穩定時，也可產生具有適當相位之時鐘信號以便取樣 輸入信號。 爲解決上述課題，本發明之半導體積體電路具備：至 少一個積分裝置，係在時鐘信號相連之兩個脈衝間之期間 內，積分輸入信號之相對的電平，至少一檢測裝置，係在 本紙張尺度適用中國國家標準( CNS ) Α4規格（ 210X297公釐） Ζ ~ ~ (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 511277 A7 _B7__ 五、發明説明（3) 時鐘信號相連之兩個脈衝間之期間內檢測出輸入信號之轉 移並輸出與轉移方向相對應之檢測信號’至少一個開關元 件，根據由至少一個檢測裝置所輸出之檢測信號。將至少 一個積分裝置之輸出信號倒置’以及相位控制信號產生裝 置，根據至少一個開關裝置之輸出信號產生用於控制時鐘 信號之相位之相位控制信號。 利用上述之構造，在時鐘信號相連之兩個脈衝間之期 間，依照輸入信號之轉移方向積分輸入信號之相對的電平 ，即可控制時鐘信號之相位’因此即使輸入信號發生大的 波形偏斜或不穩定性，仍可以產生具有適當相位之時鐘信 號以進行輸入信號之取樣。 圖式之簡單說明 本發明之優點及特徵由以下之詳細說明與圖式互相對 照即可明瞭。在該等圖式中，相同之參照號碼係指示相同 之構件。 第1圖爲表示在差動輸入信號發生大的波形偏斜或不 穩定時之最佳取樣點之圖。 第2圖爲表示在差動輸入信號發生大的波形偏斜或不 穩定時，取樣點由最佳位置向前錯開之狀態圖。 第3圖爲表示在差動輸入信號發生大的波形偏斜或γ 穩定時，取樣點由最佳位置向後錯開之狀態圖。 第4圖爲表示本發明之第1實施形態之半導體積體胃 路所包含之定時控制電路之構造圖。 I紙張尺度適用中^國家標準（CNS ) Α4規格（210Χ 297公釐） ^ (請先閱讀背面之注意事項再填寫本頁) 訂 511277 A7 ___B7__ 五、發明説明（4) 第5圖爲表示第4圖中所示之第1積分電路之具體電 路例之圖。 (請先閲讀背面之注意事項再填寫本頁) 第6圖爲表示取樣點設定於最佳位置時之輸入信號之 波形與積分値之關係圖。 第7圖爲表示取樣點設定於最佳位置之前面時之輸入 信號之波形與積分値之關係圖。 第8圖爲表示取樣點設定於最佳位置之後面時之輸入 信號之波形與積分値之關係圖。 第9圖爲表示第4圖所示之第2積分電路之具體電路例之 圖。 第1 0圖爲表示本發明之第2實施形態之半導體積體 電路中所含之定時控制電路之構成圖。 第1 1圖爲表示本發明之第3實施形態之半導體積體 電路中所含定時控制電路之構造之電路圖。 元件對照表 經濟部智慧財產局員工消費合作社印製 1:時鐘信號產生電路 2 :第1積分電路 3:資料轉移檢測電路 4 :開關電路 5 :第2積分電路 6:電平檢測電路 7 :可變延遲電路 8:差動放大電路 -7 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X297公釐） 511277 A7 ____B7__ 五、發明説明（5) C 3，C 4 :電容器 (請先閲讀背面之注意事項再填寫本頁) 10R，10G，10B:定時控制電路 C 1，C 2 :電容器 實施發明之最佳形態 第4圖爲表示本發明之第1實施形態之半導體積體電 路中所含之定時控制電路之構成圖。 在第4圖中，時鐘信號產生電路1係根據由被輸入之 差動輸入信號I η 1與I η 2所抽出之位元頻率成分，產 生用於取樣輸入信號之時鐘信號。時鐘信號產生電路1所 輸出之時鐘信號之相位可藉由相位控制信號F / S來控制 〇 經濟部智慧財產局員工消費合作社印製 通常，構造上，如設Ν爲自然數，則時鐘信號產生電 路1會對Ν個資料產生具有相位ρ 1至ρΝ之Ν相之時鐘 信號。Ν的値可以設成例如1 〇。另外，經過相位ρ 1至 φ Ν相位會繞一圈，所以相位ρ ( Ν + 1 )可視爲相等於 相位φ 1。此外，時鐘信號產生電路1也可以設成可輸出 含有該等Ν相之時鐘信號之所有相位資訊之串列時鐘信號 (Serial clock signal) 〇 差動輸入信號I η 1與I η 2也供應至第1積分電路 2以及資料轉移檢測電路3。在此，一個第1積分電路2 ，一個資料轉移檢測電路3，以及一個開關電路4被組合 成一電路段（Circuit block )〇與Ν相之時鐘信號相對應地 ，電路段數也爲N個。 -8 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 511277 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（6) 各電路段被由N相之時鐘信號內供應特定之兩個時鐘 信號而操作。在各電路段中，由第1積分電路2所供應之 差動信號係供應予相對應之開關電路4。開關電路4之切 換操作係由相對應之資料轉移檢測電路3所輸出之檢測信 號所控制。 由N個之開關電路4所輸出之差動信號分別被合成而 供應至第2積分電路5。第2積分電路5與電平檢測電路 6構成相位控制信號產生裝置。該相位控制信號產生裝置 係根據N個開關電路4之輸出產生用於控制是否加速或延 遲時鐘信號之相位之相位控制信號F / S，而供應至時鐘 信號產生電路1。亦即，第2積分電路5分別將由N個開 關電路4所輸出之差動信號積分後，電平檢測電路6即檢 測由第2積分電路5所輸出之差動信號之差分釐，以製作 相位控制信號F / S。 然後，要就第4圖所示之電路構成及動作加以說明。 N個之第1積分電路2在連接之兩個時鐘脈衝間之期 間P 1至P 2 ，φ 2至妒3 ..........或φ Ν至φ 1內，將 差動輸入信號I η 1與I η 2之差分量積分，而輸出做爲 差動信號。 如第5圖所示，第1積分電路2可藉由在差動放大電 路8之差動輸出連接兩個電容器c 1及C 2而構成。差動 放大電路8被由Ν相時鐘信號之中供應具有相位p i之時 鐘信號與具有相位¢) ( i + 1 )之時鐘信號1差動放大電 路8在具有相位（/> i之時鐘信號爲高電平（high level )， (請先閲讀背面之注意事項再填寫本頁) -裝· 訂 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -9 - 511277 A7 B7 五、發明説明（7) 而具有相位P ( i + 1 )之時鐘信號爲低電平之期間9 i 至P (i + 1)才被活化，並在該期間中，將差動輸入信 號I η 1與I η 2之差分量積分，而將所獲得之電荷分別 儲存於電容器C 1及C 2。 再參照第1圖。資料轉移檢測電路3根據連續之兩個 交叉脈衝間之期間0 1至0 2，0 2至0 3，………，或 0 Ν至4 1之差動輸入信號之電平，檢測出資料已轉移而 輸出與轉移之方向相對應之檢測信號。 開關電路4只有在由資料轉移檢測電路3輸出之檢測 信號表示資料已轉移.時，才將第1積分電路2.之輸出連接 到第2積分電路5之輸入。此時，如果資料由“〇”轉移 至“ 1 ”時，即將第1積分電路2之非倒向輸出連接到第 2積分電路5之正相輸入，同時將第1積分電路2之倒向 輸出連接到第2積分電路5之逆相輸入。另一方面，如果 資料由“ 1 ”轉移至“ 〇 ”時，即將第1積分電路2之倒 向輸出連接到第2積分電路5之正相輸入，同時將第1積 分電路2之非倒向輸出連接到第2積分電路5之逆相輸入 。此外，如果資料不轉移時，則第1積分電路2之輸出不 連接到第5積分電路5。 藉由如此之操作’如第6圖所示，積分値之符號即根 據輸入信號之轉移方向來決定。亦即，在資料由“ 〇，，轉 移至“ 1 ”之期間t 1至t 2中，如I η 1 < I η 2時， 積分値定爲負値，如I η 1 > I η 2時，積分値定爲正値 。另一方面，在資料由“ 1 ”轉移至“ 〇，，之期間t 2至 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 -10- 511277 A7 B7 五、發明説明（8) t 3中，如I n 1< I n2時，積分値定爲正値，如I η 1>Ιη2時，積分値定爲負値。 (請先閲讀背面之注意事項再填寫本頁) 如第6圖所示，取樣點被設定於最佳位置時，正値區 域之面積與負値區域之面積成爲相等，正積分値與負積分 値互相抵銷，而第1積分電路2 (第1圖）之差動輸出成 爲相等之電平（level)。 相對地，如第7圖所示，如果取樣點位於最佳位置之 前時，則負値區域之面積成爲大於正値區域之面積，而在 第1積分電路2 (第1圖）之差動輸出中，倒向輸出成爲 大於非倒向輸出。 另一方面，如第8圖所示，如果取樣點位於最佳位置 之後時，正値區域之面積成爲大於負値區域之面積，而在 第1積分電路2 (第1圖）之差動輸出中，非倒向輸出成 爲大於倒向輸出。 經濟部智慧財產局員工消費合作社印製 第1圖所示之第2積分電路5係爲了在整個取樣期間 ，針對取樣相位至pN所設置之N個第1積分電路2 之差動輸出積分而設置。如第9圖所示，第2積分電路5 可以利用兩個電容器C 3及C 4構成。第2積分電路之積 分期間宜較第1積分期長。因此，電容器C 3及C 4之容 量比電容器C1及C2 (第5圖）之容量大。 再參照第1圖，電平檢測電路6係用於檢測由第2積 分電路5輸出之差動信號ou t 1，ou t 2之差分量， 再根據比較結果輸出相位控制信號F / S。亦即，電平檢 測電路6在〇 u t 1 > 〇 u t 2時，係將相位控制信號 本紙張尺度適用中國國家標準（CNS ) A4規格（ 210X297公釐） _ 511277 A7 __B7__ 五、發明説明（9) (請先閲讀背面之注意事項再填寫本頁) F/S定爲高電平，在〇u t l<〇u t 2時，係將相位 控制信號F / S定爲低電平。因此，在取樣點位於最佳位 置之前時，相位控制信號F / S成爲低電平’在取樣點位 於最佳位置之後時，相位控制信號F / S成爲高電平。 電平檢測電路6所輸出之相位控制信號F / S係供應 予時鐘信號產生電路1。時鐘信號產生電路1在相位控制 信號F / S爲低電平時，延遲時鐘信號之相位’當相位控 制信號F / S爲高電平時，則提昇時鐘信號之相位。一種 鎖相環路（Phase Locked loop ，簡稱P L L )就是如此構 成，時鐘信號被調整於最佳定時（Timing)以便進行輸入信 號之取樣。另外，時鐘信號產生電路1也可以構成包含電 壓控制振盪器（VCO)而以第2積分電路之類比輸出信 號（差動信號或單一信號）來控制。 經濟部智慧財產局員工消費合作社印製 接著，說明本發明之第2實施形態。第1 0圖爲表示 包含於本發明之第2實施形態之半導體積體電路之定時控 制電路之構造之圖。在本實施形態中，使用依照相位控制 信號將被輸入之N相之時鐘信號延遲之可變延遲電路以取 代第1實施形態中之時鐘信號產生電路。相同N相之時鐘 信號也可以使用於其他電路時，與其說個別設置時鐘信號 產生電路，不如說設置電路規模比較小的可變延遲電路爲 宜。 第1 0圖所示之定時控制電路1 0中，可變延遲電路 7依據相位控制信號F / S延遲被供應之N相時鐘信號 Ck 1至CkN。被延遲之N相時鐘信號p 1至係供 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） 仍 511277 A7 B7 經濟部智慧財產局員工消費合作社印製511277 A7 B7 V. Description of the Invention (1) [Technical Field] The present invention relates generally to semiconductor integrated circuits, especially to semiconductor integrated circuits including a timing control circuit for adjusting the phase of a clock signal used to sample an input signal. Circuit. [Background Art] In the transmission and reproduction of digital signals, a clock signal is used to sample an input signal that is received or reproduced. At this time, a clock signal with an appropriate phase is generated according to a transition point of the input signal, or a multi-phase clock signal with multiple phases is generated at one sampling point by oversampling the input signal. Then, select a clock signal with an appropriate phase from it. Usually, the former method is selected to reduce the circuit scale and power consumption. The following describes the prior art with respect to the former method. The previous method is to generate a clock signal, detect the transition point of the input signal, and make the transition point as a sampling point by 50% of the bit period, and use the clock signal to sample the input signal. Here, if the input signal is a differential signal, the position where the differential signal crosses is equivalent to the transition point of the input signal. However, when a digital signal is transmitted or reproduced, the waveform is skewed and unstable due to floating capacitance on the signal transmission path, or the waveform is skewed or unstable due to inter-symbol interference in the recording and reproduction system. When these waveforms deviate or become unstable, it is difficult to set the sampling point at the most appropriate position in the previous timing control circuit. The conditions are shown in Figures 1 to 3. This paper size applies to China National Standard (CNS) A4 (210X297 mm) Z " (Please read the notes on the back before filling this page) Order printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 511277 A7 _ B7 V. Description of the Invention (2) In Figures 1 to 3, a large waveform skew or instability occurs in the differential input signal, and the positive input signal I n 1 and the reverse input signal I η 2 constituting the differential input signal are generated. The intersections are not at one point. As shown in Fig. I, timings t 1 to t 4 at which the potential difference between the normal-phase input signal I nl and the reverse-phase input signal I n2 becomes the largest as a whole are the optimal sampling points. However, in reality, the sampling point is staggered forward or backward from the optimal position due to waveform skew or instability. For example, in Fig. 2, the sampling point is set based on the fastest timing (Timing) at which the normal-phase input signal I η 1 and the reverse-phase input signal I η 2 cross. On the other hand, in Fig. 3, the sampling point is set based on the timing at which the normal-phase input signal I η 1 and the reverse-phase input signal I n 2 cross the slowest. As described above, in the previous timing control circuit, when a large waveform skew or instability exists, the potential difference between the positive-phase input signal I η 1 and the reverse-phase input signal I η 2 constituting the differential input signal is sampled. The point becomes the smallest, so it becomes the main cause of error and becomes a problem. [Disclosure of the Invention] In view of the above problems, an object of the present invention is to provide a semiconductor integrated circuit including a timing control circuit that can generate a clock signal with an appropriate phase when a large waveform skew or instability occurs in an input signal so that Sampling the input signal. In order to solve the above problems, the semiconductor integrated circuit of the present invention is provided with: at least one integration device, which integrates the relative levels of the input signal during the period between two pulses connected to the clock signal, and at least one detection device, which Paper size applies Chinese National Standard (CNS) Α4 specification (210X297 mm) Z ~ ~ (Please read the precautions on the back before filling out this page) Order the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and print the employee consumption of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the cooperative 511277 A7 _B7__ V. Description of the invention (3) The transition of the input signal is detected during the period between the two pulses connected to the clock signal and a detection signal corresponding to the direction of the transition is output 'at least one switching element, according to The detection signal output by the detection device. The output signal of at least one integrating device is inverted and the phase control signal generating device generates a phase control signal for controlling the phase of the clock signal based on the output signal of the at least one switching device. With the above structure, the phase of the clock signal can be controlled by integrating the relative levels of the input signal in accordance with the direction of the input signal's transition between the two pulses connected to the clock signal. Therefore, even if the input signal has a large waveform skew Or instability, a clock signal with a proper phase can still be generated to sample the input signal. Brief Description of the Drawings The advantages and features of the present invention will be made clear by the following detailed description and the comparison of the drawings. In the drawings, the same reference numbers refer to the same components. Fig. 1 is a diagram showing an optimum sampling point when a large waveform skew or instability occurs in a differential input signal. Fig. 2 is a diagram showing a state where the sampling points are shifted forward from the optimal position when the differential input signal has a large waveform skew or instability. FIG. 3 is a diagram showing a state where the sampling point is shifted backward from the optimal position when the differential input signal has a large waveform skew or γ is stable. Fig. 4 is a structural diagram showing a timing control circuit included in the semiconductor integrated circuit of the first embodiment of the present invention. I Paper size applicable ^ National Standard (CNS) Α4 specification (210 × 297 mm) ^ (Please read the precautions on the back before filling this page) Order 511277 A7 ___B7__ 5. Description of the invention (4) Figure 4 shows a specific circuit example of the first integrating circuit. (Please read the precautions on the back before filling this page.) Figure 6 shows the relationship between the waveform of the input signal and the integration chirp when the sampling point is set to the optimal position. Fig. 7 is a graph showing the relationship between the waveform of the input signal and the integration chirp when the sampling point is set in front of the optimal position. Figure 8 shows the relationship between the waveform of the input signal and the integration chirp when the sampling point is set behind the optimal position. Fig. 9 is a diagram showing a specific circuit example of the second integrating circuit shown in Fig. 4. Fig. 10 is a configuration diagram showing a timing control circuit included in a semiconductor integrated circuit according to a second embodiment of the present invention. Fig. 11 is a circuit diagram showing the structure of a timing control circuit included in a semiconductor integrated circuit according to a third embodiment of the present invention. Component comparison table Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy 1: Clock signal generation circuit 2: First integration circuit 3: Data transfer detection circuit 4: Switch circuit 5: Second integration circuit 6: Level detection circuit 7: Possible Variable Delay Circuit 8: Differential Amplifier Circuit-7-This paper size applies Chinese National Standard (CNS) A4 specification (210 X297 mm) 511277 A7 ____B7__ V. Description of the invention (5) C 3, C 4: Capacitor (please first Read the notes on the back and fill in this page again) 10R, 10G, 10B: Timing control circuit C 1, C 2: The best form of the capacitor to implement the invention Figure 4 shows a semiconductor integrated circuit showing the first embodiment of the present invention Structure diagram of the included timing control circuit. In FIG. 4, the clock signal generating circuit 1 generates a clock signal for sampling the input signal based on the bit frequency components extracted from the input differential input signals I η 1 and I η 2. The phase of the clock signal output from the clock signal generating circuit 1 can be controlled by the phase control signal F / S. 0 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Generally, if the N is a natural number, the clock signal is Circuit 1 generates N-phase clock signals with phase ρ 1 to ρN for N data.値 of N can be set to 10, for example. In addition, the phase ρ 1 to φ N will make a circle, so the phase ρ (Ν + 1) can be regarded as equal to the phase φ 1. In addition, the clock signal generating circuit 1 may be configured to output a serial clock signal including all phase information of the N-phase clock signals. The differential input signals I η 1 and I η 2 are also supplied to First integration circuit 2 and data transfer detection circuit 3. Here, a first integration circuit 2, a data transfer detection circuit 3, and a switch circuit 4 are combined into a circuit block. The number of circuit segments is also N corresponding to the N-phase clock signal. -8-This paper size applies Chinese National Standard (CNS) A4 specification (210X297mm) 511277 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (6) Each circuit segment is clocked by the N-phase clock It operates by supplying two specific clock signals. In each circuit segment, the differential signal supplied by the first integrating circuit 2 is supplied to the corresponding switching circuit 4. The switching operation of the switch circuit 4 is controlled by a detection signal output by the corresponding data transfer detection circuit 3. The differential signals output from the N switching circuits 4 are synthesized and supplied to the second integrating circuit 5. The second integration circuit 5 and the level detection circuit 6 constitute a phase control signal generating device. The phase control signal generating device generates a phase control signal F / S for controlling whether to accelerate or delay the phase of the clock signal based on the outputs of the N switching circuits 4, and supplies the phase control signal F / S to the clock signal generating circuit 1. That is, after the second integration circuit 5 integrates the differential signals output by the N switching circuits 4 respectively, the level detection circuit 6 detects the differential centimeters of the differential signals output by the second integration circuit 5 to make a phase. Control signal F / S. Next, the circuit configuration and operation shown in FIG. 4 will be described. The N first integration circuits 2 will be differential during the period P 1 to P 2, φ 2 to jealousy 3 .... or φ Ν to φ 1 between the two connected clock pulses. The difference between the input signals I η 1 and I η 2 is integrated, and the output is used as a differential signal. As shown in Fig. 5, the first integrating circuit 2 can be configured by connecting two capacitors c 1 and C 2 to the differential output of the differential amplifier circuit 8. The differential amplifier circuit 8 is supplied with a clock signal having a phase pi and a clock signal having a phase ¢) (i + 1) from the N-phase clock signals. The differential amplifier circuit 8 has a clock signal having a phase (/ > i). High level, (Please read the precautions on the back before filling this page)-The size of the bound paper is applicable to the Chinese National Standard (CNS) A4 (210X297 mm) -9-511277 A7 B7 5 (7) The period 9 i to P (i + 1) is activated only when the clock signal having the phase P (i + 1) is at a low level, and during this period, the differential input signal I η 1 and I η 2 are integrated, and the obtained charges are respectively stored in the capacitors C 1 and C 2. Referring to FIG. 1 again, the data transfer detection circuit 3 is based on the period between consecutive two cross pulses 0 1 to 0, 0 2 to 0 3, ........., or 0 N to 4 1 level of the differential input signal, detects that the data has been transferred and outputs a detection signal corresponding to the direction of the transfer. The switching circuit 4 is only available at The detection signal output by the data transfer detection circuit 3 indicates that the data has been transferred. The output of the branch circuit 2. is connected to the input of the second integration circuit 5. At this time, if the data is transferred from "0" to "1", the non-inverting output of the first integration circuit 2 is connected to the second integration circuit 5 The non-inverting input of the first integrator circuit 2 is connected to the inverting input of the second integrator circuit 5. On the other hand, if the data is transferred from "1" to "0", the first integrator circuit will be used. The inverted output of 2 is connected to the non-inverting input of the second integrating circuit 5, and the non-inverting output of the first integrating circuit 2 is connected to the inverting input of the second integrating circuit 5. In addition, if the data is not transferred, then The output of the first integration circuit 2 is not connected to the fifth integration circuit 5. By doing so, as shown in FIG. 6, the sign of the integration 値 is determined according to the direction of the input signal transfer. That is, in the data by " 〇 ， In the period t 1 to t 2 transferred to “1”, such as I η 1 < I η 2, the integral 値 is set to negative 如, such as I η 1 > I η 2, the integral 2 is set to Zheng. On the other hand, during the period when the data is transferred from "1" to "〇," t 2 to this paper Standards are applicable to Chinese National Standard (CNS) A4 specifications (210X297 mm) (Please read the notes on the back before filling this page) Order printed by the Intellectual Property Bureau Employee Consumer Cooperatives of the Ministry of Economics -10- 277 277 A7 B7 V. Description of the invention ( 8) In t 3, if I n 1 < I n2, the integral is set to be positive, and if I η 1 > Iη2, the integral is set to be negative. (Please read the notes on the back before filling this page) As shown in Figure 6, when the sampling point is set to the optimal position, the area of the positive 値 area and the area of the negative 値 area become equal, the positive integral 値 and the negative integral 抵 cancel each other out, and the first integrating circuit 2 (the (Fig. 1) The differential outputs become equal levels. In contrast, as shown in Figure 7, if the sampling point is located before the optimal position, the area of the negative chirp region becomes larger than the area of the positive chirp region, and the differential output of the first integrating circuit 2 (Figure 1) In the middle, the inverted output becomes larger than the non-inverted output. On the other hand, as shown in Figure 8, if the sampling point is located after the optimal position, the area of the positive chirped area becomes larger than the area of the negative chirped area, and the differential output of the first integrating circuit 2 (Figure 1) In the middle, the non-inverted output becomes larger than the inverted output. The second integration circuit 5 shown in Figure 1 is printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs in order to integrate the differential output points of the N first integration circuits 2 set from the sampling phase to pN during the entire sampling period. . As shown in FIG. 9, the second integrating circuit 5 can be configured by two capacitors C 3 and C 4. The integration period of the second integration circuit should be longer than the first integration period. Therefore, the capacitances of the capacitors C 3 and C 4 are larger than those of the capacitors C1 and C2 (Fig. 5). Referring to FIG. 1 again, the level detection circuit 6 is used to detect the difference between the differential signals ou t 1 and ou t 2 output by the second integration circuit 5 and then output a phase control signal F / S according to the comparison result. That is, the level detection circuit 6 applies the phase control signal to the Chinese paper standard (CNS) A4 specification (210X297 mm) at 〇ut 1 > 〇ut 2. 511277 A7 __B7__ V. Description of the invention ( 9) (Please read the precautions on the back before filling in this page) F / S is set to high level. When ut 1 < 〇ut 2, the phase control signal F / S is set to low level. Therefore, when the sampling point is located before the optimal position, the phase control signal F / S becomes low level. When the sampling point is located after the optimal position, the phase control signal F / S becomes high level. The phase control signal F / S output from the level detection circuit 6 is supplied to the clock signal generating circuit 1. The clock signal generating circuit 1 delays the phase of the clock signal when the phase control signal F / S is at a low level. When the phase control signal F / S is at a high level, it raises the phase of the clock signal. A Phase Locked Loop (P L L) is structured as such, the clock signal is adjusted to the optimal timing (Timing) in order to sample the input signal. In addition, the clock signal generating circuit 1 may be configured to include a voltage controlled oscillator (VCO) and be controlled by an analog output signal (differential signal or single signal) of a second integrating circuit. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs Next, a second embodiment of the present invention will be described. Fig. 10 is a diagram showing a structure of a timing control circuit of a semiconductor integrated circuit according to a second embodiment of the present invention. In this embodiment, a variable delay circuit that delays an inputted N-phase clock signal in accordance with a phase control signal is used instead of the clock signal generation circuit in the first embodiment. When the same N-phase clock signal can also be used in other circuits, rather than setting the clock signal generating circuit individually, it is better to set a variable delay circuit with a smaller circuit scale. In the timing control circuit 10 shown in FIG. 10, the variable delay circuit 7 delays the supplied N-phase clock signals Ck 1 to CkN according to the phase control signal F / S. The delayed N-phase clock signal p 1 is supplied to this paper. The paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm). It is still printed by 511277 A7 B7.
五、發明説明（10 應至多個第1積分電路2及多個資料轉移檢測電路3。如 同第1之實施形態，一個第1積分電路2，一個資料轉移 檢測電路3以及一開關電路4組合起來構成一個電路段（ Circuit Block)。包含於多個電路段之多個開關電路4之輸 出被合成而供應至第2積分電路5。電平檢測電路6根據 第2積分電路5之輸出製作相位控制信號F / S以供控制 時鐘信號相位之提早或延遲。 電平檢測電路6所輸出之相位控制信號F / S係供應 予可變延遲電路7。可變延遲電路7在相位控制信號 F / S爲低電平時，延遲時鐘信號之相位，而在相位控制 信號F / S爲高電平時則提早時鐘信號之相位。N相時鐘 信號就是如此地調整爲最佳計時（Timing)以進行輸入信號 之取樣。 以下說明本發明之第3實施形態。第11圖爲表示包 含於本發明之第3實施形態之半導體積體電路中之定時控 制電路之構造圖。在本實施形態中，對應於三種輸入信號 而採用三個系統之第2實施形態之定時控制電路。 在第1 1圖中，假設三種輸入信號爲各RGB之串行 影像資料（Serial image data )。亦即，r通道之差動輸入 信號I n R 1，I n R 2係輸入定時控制電路1 0 R，G 通道之差動輸入信號InGl， InG2係輸入定時控制 電路10G，B通道之差動輸入信號InBl ，InB2 則係輸入定時控制電路1 〇 B。在該等定時控制電路 1 OR至1 0B中被供應NB之時鐘信號CK 1至CKN (請先閲讀背面之注意事項再填寫本頁) ”裝· 訂 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） -13- 511277 A7 _ B7 _ 五、發明説明（1) 。包含於定時控制電路1 0 R至1 〇 B之可變延遲電路使 被供應之N相時鐘信號CK1至CKN依據各自之相位控 (請先閲讀背面之注意ί項再填寫本頁) 制信號延遲。 藉此，從定時控制電路1 OR輸出時鐘信號0R1至 0RN以供R通道之差動輸入信號InR1， InR2之 採樣，從定時控制電路1 0 G輸出時鐘信號0 G 1至 0GN以供G通道之差動輸入信號inGl， InG2之 採樣，從定時控制電路1 0 B輸出時鐘信號0 B 1至 4BN以供B通道之差動輸入信號InBl ， InB2之 採樣。 在本實施形態中之三個道通間如此地共同使用N相之 時鐘信號CK 1至CKN，因此相較於在各通道設置時鐘 信號產生電路可以刪減電路之規模。 以上，已根據實施形態說明了本發明，惟本發明並不 侷限於上述之實施形態，在申請專利範圍所記載之範圍內 可以自由變形與變更。 經濟部智慧財產局員工消費合作社印製 利用本發明，縱使輸入信號發生大的波形偏斜或不穩 定，也可以產生具有適當之相位之時鐘信號以供輸入信號 之取樣，因此，可以提升時鐘信號之相位餘量（phase margin)，降低誤差率（error rate)。 〔產業上之可利用性〕 本發明之半導體積體電路可以利用於爲採樣輸入信號 而需調整時鐘信號之相位之影像機器或電腦等。 -14- 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐）5. Description of the invention (10 should be a plurality of first integration circuits 2 and a plurality of data transfer detection circuits 3. As in the first embodiment, a first integration circuit 2, a data transfer detection circuit 3, and a switch circuit 4 are combined Forms a circuit block. The outputs of the plurality of switching circuits 4 included in the plurality of circuit segments are synthesized and supplied to the second integration circuit 5. The level detection circuit 6 creates phase control based on the output of the second integration circuit 5. The signal F / S is used to control the phase of the clock signal early or delayed. The phase control signal F / S output from the level detection circuit 6 is supplied to the variable delay circuit 7. The variable delay circuit 7 controls the phase of the signal F / S When the level is low, the phase of the clock signal is delayed, and when the phase control signal F / S is high, the phase of the clock signal is advanced. The N-phase clock signal is thus adjusted to the optimal timing for the input signal. Sampling. The third embodiment of the present invention will be described below. Fig. 11 shows the structure of a timing control circuit included in the semiconductor integrated circuit of the third embodiment of the present invention. In this embodiment, the timing control circuit of the second embodiment in which three systems are used corresponding to three input signals. In Fig. 11, it is assumed that the three input signals are serial image data of each RGB (Serial image data ). That is, the differential input signals of the r channel I n R 1, I n R 2 are input timing control circuits 1 0 R, the differential input signals of the G channel InGl, InG2 are input timing control circuits 10G, and the B channel Differential input signals InBl and InB2 are input to the timing control circuit 1 0B. The clock signals CK 1 to CKN of NB are supplied to these timing control circuits 1 OR to 10B (Please read the precautions on the back before filling in this (Page) ”The size of the bound and bound paper applies to the Chinese National Standard (CNS) A4 specification (210 × 297 mm) -13- 511277 A7 _ B7 _ V. Description of the invention (1). Contained in the timing control circuit 1 0 R to 1 〇 The variable delay circuit of B causes the supplied N-phase clock signals CK1 to CKN to control the signal delay according to their respective phase control (please read the note on the back before filling this page). By this, the timing control circuit 1 OR is output Clock signals from 0R1 to 0RN The sampling of the differential input signals InR1 and InR2 of the R channel is output from the timing control circuit 1 0 G and the clock signal 0 G 1 to 0GN is used for the sampling of the differential input signals of the G channel inG1 and InG2 from the timing control circuit 1 0 B Outputs the clock signals 0 B 1 to 4BN for sampling of the differential input signals InBl and InB2 of the B channel. In this embodiment, the three phase passes commonly use the N-phase clock signals CK 1 to CKN, so Compared with setting the clock signal generating circuit in each channel, the scale of the circuit can be reduced. As mentioned above, the present invention has been described based on the embodiments, but the present invention is not limited to the above-mentioned embodiments, and can be freely deformed and changed within the scope described in the scope of patent application. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the invention can generate a clock signal with an appropriate phase for sampling the input signal even if the input signal has a large waveform skew or instability. Therefore, the clock signal can be improved The phase margin reduces the error rate. [Industrial Applicability] The semiconductor integrated circuit of the present invention can be used in an imaging device or a computer that needs to adjust the phase of a clock signal in order to sample an input signal. -14- The paper size is applicable to China National Standard (CNS) Α4 specification (210 × 297 mm)