TW511244B - Soi mosfet - Google Patents

Abstract

A novel SOI MOSFET is disclosed in the present invention. It comprises a semiconductor substrate, a buried oxide layer, a silicon layer that consists of plural shallow trench isolation regions, a body, a source, a drain and body contact area, in which the body contact area is sited on the same side of the source and apart from the channel region. The transistor of the present invention contains a gate oxide layer, a poly-silicon gate and a branch poly-silicon layer that connects the poly-silicon gate in T-shape and extends through the source and beyond the body contact area. The transistor also has a gate contact that is on the extended line of the poly-silicon gate to connect the poly-silicon gate.

Description

V. Description of the Invention (1) Technical Field of the Invention: The present invention relates to ~ k, ik, especially to a structure with a mother " ^ + field-effect transistor. According to the technology, the silicon drawer on the insulation layer (ς · technology has received much attention in recent years: nC〇n 〇n InsuUtor; S01). The development of the layer (burled 〇xlde la) is sufficient. The components produced by the buried silicon oxide have two distinct features. Excellent insulation effect, the use of SO I technology immunity (radiation 丨, low power consumption electricity, and good radiation will use the soi technology to follow ^ mmunity and so on. In this specification, the metal oxygen half field effect produced by n Ray S, ferrite half field-effect transistor. The milky-percent-effect package is called SO I gold standard s. The mother body used to form the S01 metal-oxide half field-effect transistor: y is isolated from the semiconductor substrate, resulting in sOI. The metal-oxide half-field effect crystal book is in an electronically n0ating state, so it will cause serious problems especially in the current-sensitive circuit. Please refer to Figure 1 first, learn Technology opens at the edge of component channels Open multiple mother contact windows (bode contacts), which include a source electrode 10, a source contact window n, a drain electrode 20, a drain contact window 2 a mother contact window area 30, and a polycrystalline silicon gate 4 0, and the gate contact window 4 2 ′ are shown in FIG. 1. However, the disadvantage is that an additional body terminal needs to be designed and particularly complicated routing is required. Especially, such a design When the length of the channel is reduced

511244 5. Description of the invention (2) When the channel is elongated by 1 degree, its pick-up capability will be greatly reduced. In order to overcome the above problems, TGW Blake disclosed in US Patent No. 4, 6 925, 2 1 3 a SiO2 transistor (Silicon ~ On-Insulator Transistor With Body Node to Source Note Connection), as shown in FIG. 2, which includes a source electrode 10, a source contact window 1 and a drain electrode 2 0, a drain contact window 2 and a parent contact window area 3 0, a polycrystalline silicon gate electrode 4 0, As well as the gate contact window 4 2. In this conventional technique, an extra P-type ion implantation is used in the source region 10 to connect the mother body under the gate, and the contact window of the mother body and the contact window of the source pass through the surface of the Lu Shixiu layer. Metal silicide layers are connected. This technology can indeed avoid the redundant winding of the mother contact window, but this extra p-type ion implantation causes severe limitations. Under the design of this conventional technique, the channel length must not be too short, so as to prevent the extra p-type ion implantation from covering the drain region. In addition, the extra p-type ion implantation near the active device area will also occur. The failure of Jing Jingxiang components. In addition, Ching-Hsiang Hsu and Mong-Song Liang disclosed in US Patent No. 4,804,588, a body contacted SOI MOSFET with a parent contact window. Its layout is shown in Figure 3. It includes source 10, source contact window 11, drain _ 2 0, non-contact contact window 2 matrix contact window area 30, complex silicon gate 4 〇, And idler contact window 42. However, the restriction that the channel length cannot be too short still exists. On the other hand, J.B. Kuang, J.P. Pennings, and M.II.

511244 V. Description of Invention (3)

Wood et al. Disclosed in US Pat. No. 6,177,708 a SOI FET Body Contact Structure. The layout diagram is shown in Figure 4. A new structure is provided, which is sufficient to avoid the above-mentioned restriction that the channel length cannot be too short, which includes a source electrode 10, a source contact window 1 1, a drain electrode 2 0, a drain contact window 2 1, and a mother contact window area 30. , Compound silicon gate electrode 40, and gate contact window 42. However, the above-mentioned disadvantage that the additional P-type ion implantation affects the efficiency of the active area still exists, and similarly, its adverse effect on the wide-channel element has not been improved. Brief description of the invention: The main object of the present invention is to provide a structure of an SO I metal-oxide half-field-effect transistor. Another object of the present invention is to provide an SO I metal-oxygen half field effect transistor with a body-tied-t0-s our ce structure. The first embodiment of the present invention discloses an SO I A metal-oxide-semiconductor field-effect transistor including a semiconductor substrate, a buried silicon oxide layer, a silicon layer, and a plurality of shallow trench isolation regions, wherein the buried silicon oxide layer is located on the surface of the semiconductor substrate The silicon layer is located on the buried silicon oxide layer, and the shallow trench isolation region is located in the silicon layer. The first embodiment of the present invention further includes a mother body, a source electrode, a non-electrode, and a contact window area with the mother body, all of which are located in the silicon layer, wherein a channel region is included between the source electrode and the drain electrode. , Wherein the mother contact window

511244 V. Description of the invention (4) The region is located on the same side of the source and is separated from the channel region; another layer of gate oxide stone layer is included, wherein the gate oxide stone layer is located above the mother body. . The first embodiment of the present invention further includes a polycrystalline silicon gate and a branched polycrystalline silicon layer, both of which are above the gate silicon oxide layer, wherein the polycrystalline silicon gate is located in the channel. Above the region, the branched polycrystalline silicon layer is in a T-shaped connection with the polycrystalline silicon gate, which extends through the source and exceeds the area of the parent contact window; and further includes a gate contact window. The gate contact window is located on an extension line of the polycrystalline silicon gate and is connected to the polycrystalline broken gate. _ A first embodiment of the present invention discloses an SO I metal-oxide half field-effect transistor, which includes a semiconductor substrate, a buried oxide layer, a broken layer, and a plurality of shallow trench isolation areas, wherein the buried A layer of silicon oxide layer is located on the surface of the semiconductor substrate, the silicon layer is located on the buried silicon oxide layer, and the shallow trench isolation region is located in the silicon layer. The second embodiment of the present invention further includes a mother body, a source electrode, a drain electrode, and a contact window area with the mother body, all of which are located in the silicon layer, wherein the source electrode and the drain electrode include a channel region. , Wherein the parent contact window region is located on the same side of the source electrode and is separated from the channel region; and also includes a gate oxide stone layer, wherein the gate oxide stone layer is located above the parent body . The second embodiment of the present invention further includes a polycrystalline silicon gate and a plurality of branch polycrystalline silicon layers, all of which are above the gate silicon oxide layer, wherein the polycrystalline silicon gate is located on the gate. Above the channel area, said plurality

The branched polycrystalline silicon layer and the complex s pass through the source and pass through the mother = two ridges in a T-shaped connection, which extends the pole contact window 'the gate contact: area; further comprising a plurality of The number of phases Θ, each gate: is connected to the extension line of the branched polycrystalline silicon layer spar, and is connected to the branched multi-layered silicon layer. Connected to the four pairs of low-cost branched polycrystalline silicon Figure number description: 1 semiconductor substrate 3 shallow trench isolation area 5 gate oxidation; ε layer 11 source contact window 21 drain contact window 4 0 polycrystalline second gate 4 2 gate contact window 2 buried silicon oxide layer 4 mother body 1 0 source 2 0 drain electrode 3 0 mother contact window area 4 1 branch polycrystalline silicon layer 5 0 silicided metal layer

Detailed description of the invention: Tian Ben Sheming is related to the structure of a SOI metal-oxygen half field effect transistor, and in particular to a SO-I structure with a body-tied-to-source structure Layout of Metal Oxide Half Field Effect Transistor.

Please refer to FIG. 5 for the first embodiment of the present invention, which is the layout of the SO I metal-oxygen half field-effect transistor formed by using the technology of the present invention. Please refer to FIG. 7A (A --A direction), Figure 7b (B--B

511244 V. Description of the invention (6) direction) and Figure 7 C (C-C direction). The layout of the first embodiment of the present invention includes a source electrode 10, a source contact window 11, a drain electrode 20, a drain contact window 21, a mother contact window area 30, and a polycrystalline silicon gate electrode 40. , Branch polycrystalline silicon layer 4b, and gate contact window 42, as shown in Figure 5. In addition, in the cross-sectional views of the process results in Figure 7A (A--A direction), Figure 7B (B--B direction), and Figure 7C (C--C direction), in addition to the source electrodes 10, In addition to the drain electrode 20, the mother contact window area 30, the polycrystalline silicon gate 40, and the branched polycrystalline silicon layer 41, the semiconductor substrate 1 used to fabricate the SO I metal-oxide-semiconductor field-effect transistor 1 and the buried layer are included. Silicon oxide layer 2, a plurality of shallow trench isolation (STI) 3, a parent body 4, a gate oxide layer 5, a stone layer 6, and a petrochemical metal layer 50. The buried silicon oxide layer 2 is located on the surface of the semiconductor substrate 1, the silicon layer 6 is located on the buried silicon oxide layer 2, and the shallow trench isolation area 3 is located on the silicon layer 6. in. The mother body 4, the source electrode 10, the drain electrode 20, and the mother body contact window area 30 are also located in the silicon layer 6. The gate silicon oxide layer 5 is located above the mother body 4, and the polycrystalline silicon gate 40 and the branched polycrystalline silicon layer 41 are further above the gate silicon oxide layer 5. Among them, the mother contact window region 30 is a P-type doping, which is located on the same side of the source electrode 10, which can reduce the area of the substrate occupied by the layout. The mother body contacts the window region 30 and is separated from the channel region (that is, the region between the N-type doped source ⑩ 1 0 and the N-type doped drain 20), so that its adverse effect on the device is reduced. The lowest, in particular, it can avoid the situation that the reduction of the channel length must be limited because of the concern that the mother's contact window area 30 will overlap with the drain electrode 20.

511244 V. Description of the invention (7) ^^ The first embodiment of the present invention ^^ _ The extra branched polycrystalline silicon layer 41 is connected to the polycrystalline silicon and the polycrystalline silicon gate 40 to form a T-shaped connection. The branch blessing: the pole 40 is connected with the polycrystalline silicon layer 41 below, so that the P-type doped mother: silicon layer 41 and the window region 30 are connected together. The channel region and the channel 4 are located on the extension line of the multiplexed silicon gate 40, and the female contact area is a contact area. 'I and the polycrystalline stone are closed ^ connected to the branched polycrystalline silicon layer 4 hw 4 〇 g are respectively the ancient layer is located on the polycrystalline silicon gate 40 0' Py and N-type hybrid The silicided metal layer 50 is located in the source = metal layer 5. The fin luly can be: the domain 30, the polycrystalline silicon gate 40 and the branch; 〇, the drain electrode 20, the mother body = the mother body contact window area 30 and the n-type silicon-doped silicon layer 41. Touch zone 1 to read. Layers 50 are connected together. The source electrode 10 is used to extend the branched polycrystalline silicon layer 41. The window region 30 is used to ensure that the p,... Passes the source electrode 10 and exceeds the contact window. Area 3 0. The sub-parent body 4 can be connected to the office-contact terminal 4 ° and connected to the terminal of the terminal contact window: 41 and can be used. Π Please refer to Figure 6 below, as shown in Figure 5. : Bureau map. The second embodiment of the present invention ^ Ϊ ^ The embodiment discloses: two idle poles 4. The same as the first embodiment except 302. Shi Xi layer 4 1 a and the second branch 祯 stone 々 厣 4] κ each first knife branch complex day contact window 49 fate which is connected to the first A gate stone Xi it pole contacts w 42b. Wherein, the first branched polycrystalline silicon layer (4la), the first branched polycrystalline silicon layer 41b, and the polycrystalline silicon gate, respectively

SRI

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511244 V. Description of the invention (8) It is T-shaped, and it extends through the source electrode 10 and exceeds the mother contact window area 30. The first gate contact window 4 2 a and the second gate contact window 4 2 b are located on extension lines of the first branched polycrystalline silicon layer 4 1 a and the second branched polycrystalline silicon layer 4 1 b, respectively. And respectively connected to the first branched polycrystalline silicon layer 4 1 a and the second branched polycrystalline silicon layer 4 1 b, wherein the first gate contact window 4 2 a and the second gate contact window 4 2 b It is on the same side as source 10. The advantage of the layout of this embodiment is that more gate contact windows 42 can be designed to reduce the R-C delay effect of the polycrystalline silicon gate 40 wires and increase the switching speed of the element. If necessary, in other embodiments of the present invention, more sets of branched polycrystalline silicon layers 41 and gate contact windows 41 can be designed, which can respond to the requirements of components with extremely wide channels to improve the mother contact window. The pick-up efficiency of area 30 (pick-upcapabi 1ity) can further reduce the resistance-capacitance delay effect of the polycrystalline stone gate 40 wire. It is particularly emphasized that the layout of the embodiments of the present invention can be applied to both N-type metal-oxide-semiconductor field-effect transistors and P-type metal-oxide-semiconductor half-field-effect transistors, and the description is not tedious and repetitive. This embodiment only uses N-type metal oxides. The layout of the half field effect transistor is taken as an example. As for the embodiment in which the present invention is applied to a P-type metal-oxide half field effect transistor, only each of the N-type and P-type in the above embodiment is interchanged, that is, the above-mentioned 0 The present invention will be described in detail using preferred examples, rather than limiting the scope of the present invention, and those skilled in the art will understand that appropriate and subtle changes and adjustments will not lose the essence of the present invention, so they should be regarded as The present invention is further implemented.

511244 V. Description of Invention (9)

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(〇Ά ^ Q Brief description of the diagram Brief description of the diagram:

Modified WE Figure 1 shows the layout of the SO I metal-oxide-semiconductor field-effect transistor formed in the conventional technique. Figure 2 shows the layout of the SO I metal-oxide-semiconductor field-effect transistor formed in another conventional technique. FIG. 3 is a layout diagram of an SO I metal-oxide half field-effect transistor formed in another conventional technique. FIG. 4 is a layout diagram of an SO I metal-oxygen half field-effect transistor formed in another conventional technique. FIG. 5 is a layout diagram of forming a SOI metal-oxide half-field-effect transistor in the first embodiment of the present invention. FIG. 6 is a layout diagram of forming a SO I metal-oxide half field-effect transistor in the second embodiment of the present invention. FIG. 7A is a cross-sectional structural view in the direction A-A of FIG. 5. Fig. 7B is a cross-sectional structural view in the direction B-B of Fig. 5. FIG. 7C is a cross-sectional structural view in the OC direction of FIG. 5. i

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Claims (1)

511244 6. Scope of patent application 1. An SO I metal-oxide half-field-effect transistor: comprising: a semiconductor substrate, a buried silicon oxide layer, a silicon layer, and a plurality of shallow trench isolation areas, wherein the buried silicon oxide layer The silicon layer is located on the surface of the semiconductor substrate; the silicon layer is located on the buried silicon oxide layer; the shallow trench isolation region is located in the silicon layer; a mother body; a source; a drain and a mother; Contact window regions, all of which are located in the silicon layer, wherein the source and drain electrodes include a channel region, wherein the parent contact window region is located on the same side of the source electrode and is separated from the channel region 9 A gate silicon oxide layer, wherein the gate silicon oxide layer is a polycrystalline silicon gate and a branch polycrystalline silicon located above the mother body Layer J is all above the gate silicon oxide layer, wherein the polycrystalline silicon gate system is located above the channel region. The branch polycrystalline silicon layer system is T with the polycrystalline silicon gate. Connection? It extends through the source and beyond the area of the mother contact window, and a gate contact window is located on the extension line of the polycrystalline silicon gate and is connected to the polycrystalline silicon Silicon gate 0 2 · The SOI metal-oxide half-field-effect transistor as described in the first item of the patent scope? What's more, it includes a silicided metal layer? Wherein, the silicided metal layer is located at the source drain mother contact window Area% is above the polycrystalline silicon gate and the branch polycrystalline silicon layer, and is used to connect the mother contact window region and the source. Page 14 511244 6. Scope of patent application A SOI metal-oxide-semiconductor field-effect transistor-a semiconductor substrate and a layer of buried oxygen include: a fossil layer, a shallow trench and a conductive substrate; The silicon region, which is above the one layer of the gate oxygen precursor; the region, the surface, the trench, the source, the layer, the mother channel region, the silicon layer, the silicon layer, and a plurality of layers are located in the region In a layer of a semi-buried silicon oxide layer; a drain electrode and a window region in contact with a mother body, wherein the silicon layer insulation region is a buried silicon oxide system and is located in the Shi Xi where the body is The contact window is separated; wherein the gate oxide stone layer is located on the same side of the source and non-electrode regions located on the same side of the source electrode and includes a polycrystalline silicon gate and the gate. The through-branch complex crystals extend through the layer, all of which are located in the gate system and are connected to the second sub-layer, which extend above and above the second layer of the polycrystalline silicon layer and the first layer. More than stated The silicon layer in the region of polar oxide stone is divided into the source two-branch complex crystal silicon, wherein the complex silicon crystal silicon gate has a d-shaped mother contact window region, and the first gate contact window and the pole contact the polycrystalline silicon. The layer, the second window, the second gate, and the second branched branched polycrystalline silicon second gate window are extended two-branched composite contact windows of the respective layers, which are located on the line and are respectively crystalline layers. The first gate contact is a branched polycrystalline silicon layer connected to the first 4. The SO I metal-oxygen half field effect transistor described in item 3 of the scope of patent application, more Page 15 511244 6. The scope of the patent application includes a silicided metal layer, wherein the silicided metal layer is located on the source, drain, parent contact window area, polycrystalline silicon gate and branched polycrystalline silicon layer. It is used to connect the contact area of the mother body and the source, although it is a kind of SOI metal-oxide half field effect transistor, which includes: a semiconductor substrate, a buried silicon oxide layer, a silicon layer, and a plurality of shallow layers. The trench isolation area, wherein the buried silicon oxide layer is located on the surface of the semiconductor substrate, the stone layer is located above the buried oxide layer, and the shallow trench isolation area is located In the silicon layer; φ a parent body, a source electrode, a drain electrode, and a contact window area of the parent body, which are all located in the stone layer, wherein a channel region is included between the source electrode and the non-electrode, wherein The mother contact window region is located on the same side of the source electrode and is separated from the channel region; a gate silicon oxide layer, wherein the gate silicon oxide layer is located above the mother body; a polycrystalline silicon gate And multiple The branched polycrystalline silicon layer is all above the gate silicon oxide layer, wherein the polycrystalline silicon gate is located above the channel region, and the plurality of branched polycrystalline silicon layers are respectively connected with the compound silicon layer. The crystalline silicon gate is in a T-shape connection, which extends through the source and exceeds the area of the mother contact window; and a plurality of gate contact windows, the number of the gate contact windows and the branch polycrystalline silicon The number of layers is the same, and each gate contact window is located on the extension line of its corresponding branch polycrystalline silicon layer and is connected to the corresponding Page 16 511244 6. Scope of patent application Branched polycrystalline silicon layer. 6. The SO I metal-oxide half field effect transistor described in item 5 of the scope of patent application, further comprising a silicided metal layer, wherein the silicided metal layer is located in the source, drain, mother contact window area, and The crystalline silicon gate and the branched polycrystalline silicon layer are used to connect the mother contact window area and the source. Page 17