TW508684B - Etch/clean process for integrated circuit pad metal - Google Patents

Etch/clean process for integrated circuit pad metal Download PDF

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TW508684B
TW508684B TW90115922A TW90115922A TW508684B TW 508684 B TW508684 B TW 508684B TW 90115922 A TW90115922 A TW 90115922A TW 90115922 A TW90115922 A TW 90115922A TW 508684 B TW508684 B TW 508684B
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TW90115922A
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David Joseph Leary
Ang Her San
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Chartered Semiconductor Mfg
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Abstract

A new method of etching an opening to a bonding pad wherein corrosion is eliminated and fluorine contamination is reduced is described. A metal bonding pad is provided overlying an insulating layer on a semiconductor substrate. An anti-reflective coating (ARC) layer is deposited overlying the metal bonding pad. A passivation layer is deposited overlying the ARC layer. A hard mask layer is deposited overlying the passivation layer. A photoresist mask is formed overlying the hard mask layer having an opening where the contact opening to the metal bonding pad is to be made. The hard mask layer and passivation layer not covered by the photoresist mask are etched through, stopping at the ARC layer. Thereafter, the photoresist mask is removed and the opening is cleaned. The ARC layer protects the metal bonding pad during these steps. The ARC layer within the opening is etched away wherein the hard mask layer overlying the passivation layer prevents erosion of the passivation layer thereby preventing contamination of the metal bonding pad to complete opening a contact to a metal bonding pad in the fabrication of an integrated circuit.

Description

五、發明說明(1) 【發明之背景】 (1 )發明之領域 本發明係有關於一種蝕刻一開口到金屬接合墊之 法,並且特別是有關於一種在積體電路製造中^ 合墊的腐蝕及氟污染而蝕刻開口到金屬接合塾之方法。 (2 )習知技藝之說明 在積體電路的製造中,許多半導體元件及 立在一半導體結構上的多層中,最後金屬 ” 塾,係典型地位於積體電路的周圍上,積體‘:晶::: 接線係接合到這些金屬接合墊,在此外接線:二、 鈍態保護層下的金屬接合墊需暴露一 2之=,在 =層’且隨後的清洗製程係進行; 蝕刻及清洗步驟顯著地降低鋁墊金屬的品 程會造成鋁的氟污毕,孫;斗备几加> e 貝挪4衣 良率變化期Π上:ί 乳 成長且在晶圓探針及 二雨電Β,清洗步驟造成及增加鋁墊金屬 界面上的侵#,為銅突然發生。此侵蝕在金屬表面 η部’這些凹陷部將會成長且傳播穿過銘層,如 2 、行,而成為晶圓儲存的一個顯著的問題,對於線 妾口 ^凸墊而言侵蝕為一個品質及可靠度問題。 ^用技藝者試圖避免或減少氣或氟污染或侵蝕的問 »班^ = ί利第5,376,235號(Langley)教導在以去離子水 *文、/合液餘刻以移除氟殘留之後的清洗金屬接合墊。 508684 五、發明說明(2) 美國專利第5, 930, 664號(Hsu等)教導一種首先蝕刻鈍態保 瘦層、然後#刻穿過ARC(抗反射塗佈層)層、然後形成一 聚合物覆蓋於金屬接合墊上作為保護之方法。美國專利第 6, 0 01,538號(Chen等)揭露一種兩步驟蝕刻製程,以形成 二開口到一接合墊。美國專利第5, 54〇, 812號(Kadmura)顯 示一種銘姓刻製程’係使用許多方法以防止由氯污染所造 成的侵触。 【發明之概要】 本發明之一主要目的,係在於提供一種有效且極有製 造性的蝕刻一開口到一接合墊之方法。 本發明之另一目的,係在於提供一種蝕刻一開口到一 接合墊之方法,其中可清除侵蝕。 本發明之又一目的,係在於提供一種餘刻一開口到一 接合墊之方法,其中可清除侵蝕及減少氟污染。 本發明之又一目的,係在於提供一種餘刻一開口到一 接合墊之方法,其中可清除侵蝕及減少氟污染,在完成所 有其他蝕刻及清洗之後,係藉由加入一硬罩幕保護層覆蓋 於鈍態保護層上,且藉由移除在接合墊上的抗反射塗佈 層。 根據本發明之目的,係達成一種蝕刻一開口到一接合 墊之新穎方法,其中可清除侵蝕及減少氟污染,一金屬接 合墊係提供覆接一在半導體結構上的絕緣層上,一抗反射 塗佈(ARC)層係沈積覆接於金屬接合墊上,一鈍態保護層V. Description of the invention (1) [Background of the invention] (1) Field of the invention The present invention relates to a method for etching an opening to a metal bonding pad, and in particular, to a method for bonding pads in the manufacture of integrated circuits. Etching and fluorine contamination to etch openings to metal joints. (2) Description of the know-how In the manufacture of integrated circuits, many semiconductor elements and multiple layers standing on a semiconductor structure, the final metal "塾" is typically located on the periphery of integrated circuits. Crystal ::: The wiring system is bonded to these metal bonding pads. In addition, the wiring is: 2. The metal bonding pads under the passive protection layer need to be exposed to 2 =, at = layer, and the subsequent cleaning process is performed; etching and cleaning The steps significantly reduce the quality of aluminum pad metal, which will cause the fluorine pollution of aluminum, Sun; Dougai > e Bejo 4 Yield change period Π: milk growth and the wafer probe and two rain Electricity B, the cleaning step causes and increases the invasion on the metal interface of the aluminum pad, which is a sudden occurrence of copper. This erosion in the metal surface η portion. These depressions will grow and propagate through the layer, such as 2, lines, and become A significant problem with wafer storage is erosion and quality issues for wire bumps. ^ Problems for artists trying to avoid or reduce gas or fluorine contamination or erosion »ban ^ = ί 利迪No. 5,376,235 (Langley) teaches to leave子 水 * 文 、 / The mixture is cleaned after removing the residual fluorine. 508684 V. Description of the invention (2) US Patent No. 5,930, 664 (Hsu, etc.) teaches a method of first etching the passivation The thin layer, then #etched through the ARC (Anti-Reflective Coating) layer, and then formed a polymer to cover the metal bonding pad as a method of protection. US Patent No. 6, 0 01,538 (Chen et al.) Discloses a two A step etching process is performed to form two openings to a bonding pad. US Patent No. 5,54〇, 812 (Kadmura) shows that an inscription process uses many methods to prevent intrusion caused by chlorine contamination. [Invention of Summary] One of the main objects of the present invention is to provide an effective and highly manufacturable method for etching an opening to a bonding pad. Another object of the present invention is to provide a method for etching an opening to a bonding pad. Among them, the erosion can be removed. Another object of the present invention is to provide a method for opening an opening to a bonding pad, which can remove the erosion and reduce fluorine pollution. Another object of the present invention is to In providing a method for opening an opening to a bonding pad, which can remove erosion and reduce fluorine pollution, after all other etching and cleaning are completed, a hard mask protective layer is added to cover the passive protective layer. And by removing the anti-reflection coating layer on the bonding pad. According to the purpose of the present invention, a novel method for etching an opening to a bonding pad is achieved, in which erosion can be removed and fluorine pollution can be reduced. A metal bonding pad is provided Overlay an insulating layer on a semiconductor structure, an anti-reflection coating (ARC) layer is deposited over a metal bonding pad, and a passivation protective layer

508684 係沈積覆接於ARC層上,一硬罩幕層係沈積覆接於鈍態保 邊層上’一光阻罩幕係形成覆接於具有開口的硬罩幕層 上,且在接觸窗開口到金屬接合墊係形成處,蝕刻穿^未 被光阻罩幕所覆蓋的硬罩幕層及鈍態保護層,停止於arc 層,之後,移除光阻罩幕及清洗開口,在這些步驟期間, ARC層保護金屬接合墊,在開口内的ARC層係被蝕刻掉,其 中覆接於鈍態保護層上的硬罩幕層防止鈍態保護層的侵 敍因此,防止金屬接合塾的污染,以在積體電路製造中 完成一接觸窗到一金屬接合墊的開口。 【圖號對照說明】 10 半導體結構 14 半導體元件結構 20 金屬層 22 抗反射塗佈層 26 鈍態保護層 30 硬罩幕層 35 光阻罩幕 【較佳實施例之說明】 本實施例圖式將揭露一種形成一接觸窗到一金屬接合 塾之新穎方法,係可清除侵独及減少氟污染,熟習本技藝 之人士應瞭解地是本發明可應用且延伸而不背離本發明之 精神與範疇下為之。 現在參閱第1圖’係說明一部份的局部完成的積體電 路’半導體結構1 0係由單晶石夕所組成者較佳,半導體元件508684 is deposited on the ARC layer, and a hard mask layer is deposited on the passive edge protection layer. A photoresist mask is formed on the hard mask layer with an opening, and is on the contact window. Open to the place where the metal bonding pad system is formed, etch through the hard mask layer and passivation protective layer not covered by the photoresist mask, stop at the arc layer, and then remove the photoresist mask and clean the openings. In these steps During this period, the ARC layer protects the metal bonding pad, and the ARC layer in the opening is etched away. The hard cover layer overlying the passive protection layer prevents the invasion of the passive protection layer. Therefore, the contamination of the metal bonding layer is prevented. To complete the opening of a contact window to a metal bonding pad in the manufacture of integrated circuits. [Comparison of drawing numbers] 10 Semiconductor structure 14 Semiconductor element structure 20 Metal layer 22 Anti-reflection coating layer 26 Passive protective layer 30 Hard cover layer 35 Photoresist cover [Explanation of the preferred embodiment] Schematic diagram of this embodiment A novel method for forming a contact window to a metal junction will be disclosed, which can eliminate invasion and reduce fluorine pollution. Those skilled in the art should understand that the present invention can be applied and extended without departing from the spirit and scope of the invention Here it is. Now referring to FIG. 1 ', which illustrates a part of a partially completed integrated circuit. The semiconductor structure 10 is preferably composed of a monocrystalline stone, a semiconductor element.

第8頁 5080^ 五、發明說明(4) 結構(如閘極電極、 綠r去淑-、、 及組合的源極及汲極區、及多層内導 此麻邱-从’、建立於半導體結構上及半導體結構中’這 些底邵7〇件及JS & ^ ^ ^ 仁 9係匕括於第1圖中標號14的層中,在14中 的一隔離層覆蓋底部層上。 你 人感f Ϊ形成最頂部金屬層’接合塾將形成於此最頂部 金屬層中,太絡日日# & (j 货月係為一種蝕刻一開口到一金屬墊及清洗 開^製私流程’以便清除由侵餘所造成的墊凹陷部,且 明顯^減少由餘刻及清洗所導致的氟污染,此將會明顯地 改進屬塾的品質,減少在墊金屬表面上的氟含量,會造 成曰個具^有改良自然氧化物均勻度的較高品質金屬墊,係 在a曰圓探針上具有很滿意的良率、在銲錫凸塊製程中改進 過的良率、及擴大晶圓儲存。 ^金屬層2〇(典型由鋁或具有銅及/或矽的鋁)係沈積覆 蓋於層14中的最頂部隔離層上,一阻障層(未顯示)可沈積 於金屬層20下,銘層20係藉由濺擊或化學氣相沈積(CVD) 而被沈積,以沈積到一個厚度在5 〇 〇 〇到丨8 〇 〇 〇埃之間,一 抗反射塗佈(ARC)層22(氮化鈦、氮化鎢、或幾個有機或無 機ARC材料之一)係沈積覆接於金屬層2〇上,以達到一個在 1 0 0到5 0 0埃之間的厚度。 現在,一鈍態保護層26係沈積覆蓋於ARC層22上,鈍 態保護層26可包括有氮化矽或一個高密度電漿(HDP)氧化 石夕及氮化石夕或四氧乙基石夕(T E 0 S )氧化物的組合,鈍態保護 層典型地係具有一個在5 0 0 0到2 0 0 0 0埃之間的厚度。 現在,將描述本發明的一種新穎製程步驟,參閱第2Page 8 of 5080 ^ V. Description of the invention (4) Structures (such as gate electrode, green r-sv-,-, and combined source and drain regions, and multi-layered internal conductors this Ma Qiu-from ', built on semiconductor Structurally and in semiconductor structures, these bottom 70 pieces and JS & ^ ^ ^ Ren 9 series are enclosed in the layer labeled 14 in Figure 1, and an isolation layer in 14 covers the bottom layer. Sense f Ϊ form the topmost metal layer 'junctions' will be formed in this topmost metal layer, Tailuo Ri Ri # &; (J cargo month is an etching to an opening to a metal pad and cleaning process In order to remove the pad depression caused by invasion, and significantly reduce the fluorine pollution caused by the etch and cleaning, this will significantly improve the quality of the metal, and reduce the fluorine content on the surface of the pad metal, which will cause A higher-quality metal pad with improved uniformity of natural oxides has a satisfactory yield on a round probe, an improved yield in the solder bump process, and expanded wafer storage ^ Metal layer 20 (typically made of aluminum or aluminum with copper and / or silicon) is deposited overlying layer 14 On the topmost isolation layer, a barrier layer (not shown) may be deposited under the metal layer 20, and the layer 20 is deposited by sputtering or chemical vapor deposition (CVD) to a thickness of 5 Å. Between 0.000 and 8000 angstroms, an anti-reflective coating (ARC) layer 22 (titanium nitride, tungsten nitride, or one of several organic or inorganic ARC materials) is deposited overlying the metal layer 20 to achieve a thickness between 100 and 500 angstroms. Now, a passive protection layer 26 is deposited over the ARC layer 22, and the passive protection layer 26 may include silicon nitride or A combination of high-density plasma (HDP) oxide stone oxide and nitride stone oxide or tetraoxyethyl stone oxide (TE 0 S) oxide. The passivation protective layer typically has a range from 5 0 0 0 to 2 0 0 0 Thickness between 0 angstroms. Now, a novel process step of the present invention will be described.

五、發明說明(5) 】包:係沈積覆蓋於鈍態保護層上,此硬罩幕 機鶴化欽、《幾個通常使用於工業中的有 厚度1罩幕Λ之;ΪΛ具有一個在100到500埃之間的 硬卓幕層會或不會由如ARc層相同材料組成。 上,ίϋϋ圖’ 一層光阻係塗佈覆蓋於硬罩幕層30 形成接衫以形成光阻罩幕35,而具有-開口,係 办成接觸®到金屬墊處。 #離麻係進行一電漿蝕刻,以蝕刻穿過硬罩幕層30及 保遵層26 ’停止於廳層22(如第4圖所示),例如,可 用一低壓電漿蝕刻,通常為35〇毫托壓力及一個包括有 3、CF4、及氬氣(Ar)的蝕刻環境,使成1〇 sccm CH&、 sCcm CL、及9〇〇 sccm Ar的流量比例,此蝕刻安排為 y止於底部ARC層或藉由通常使用於工業中的終點偵測方 法而停止。 ARC層22作為一保護膜覆蓋於金屬表面上,在鈍態蝕 刻期間’防止氟污染及侵飿凹陷部。 、、光阻罩幕係使用例如〇2/CF4電漿去灰(如第5圖所示)而 被清除掉,此步驟接著一清洗步驟以移除光阻殘留及蝕刻 聚合物,此清洗步驟可包括有一濕式化學有機溶劑:例 如,十分鐘的EKC265,藉著400秒的異丙醇(IPA),接著一 去離子水及C〇2攪拌劑沖洗390秒,或者,一顯影液(如氣 氧化四甲銨(TMAH))可使用於1〇到60秒,在光阻清除及濕 式清洗期間,ARC層亦提供作為金屬層的保護。 在清洗步驟之後’進行一第二電漿蝕刻,以移除在開 第10頁 5〇8684 五、發明說明(6) 口内的ARC層22,當底部ARC層由氮化鈦所組成時,相同化 學蝕刻程式使用如同上述的第一電漿蝕刻步驟,及鋁墊金 屬上的終點彳貞測’鼠化學在此案例中並非必要的。 在該較佳實施例中,係教導氮化鈦作為硬罩幕層,必 須第二電漿蝕刻完全同時移除底部ARC層22及硬罩幕層 3 〇 (如第6圖所示)兩者,然而,此要求無須應用於可作為 硬罩幕層的其他材料,於某些案例中,可在完成底部arc 膘以暴露金屬表面的蝕刻之後留下某些所有的硬罩幕層。 在其中案例中,在蝕刻掉ARC層22期間,硬罩幕層3〇 ,止鈍態保護層的侵蝕,氮化矽鈍態保護層具有約一個較 氮化鈦高的1 0比1的蝕刻率,所以若在蝕刻期間鈍態保護 層沒有被硬罩幕層所保護時,會發生明顯的蝕刻。 ^ 現在,暴露於接觸窗開口的金屬接合墊可如一般及繼 續製造接合墊連接的製程使用,諸如藉由線接合、銲錫凸 塊、或其他相似製程(未顯示)。 — 本發明之製程提供一種展開一接觸窗到一金屬墊之有 致方法’其中可清除墊凹陷部及大大地減少氟污染,只直 成本發明的咼品質金屬接合墊之前,加入一硬罩幕層 覆盍於鈍態保護層上、及保持ARC層覆蓋於金屬接合墊 上0 雖然本發明已被特別地表示,並參考其較佳實施例做 \ 各種形式上及細節的改變可於不背離本發明之精 神與範嘴下為之,係為熟習本技藝之人士所能瞭解的。V. Description of the invention (5)] Package: The system is deposited and covered on a passive protective layer. This hard cover machine He Huaqin, "Several thickness 1 covers Λ commonly used in industry; ΪΛ has an The hard curtain layer between 100 and 500 Angstroms may or may not be composed of the same material as the Arc layer. In the above picture, a layer of photoresist is coated on the hard cover layer 30 to form a jumper to form the photoresist cover 35, and it has an opening, which is made to contact the metal pad. # 离 麻 系 Carry out a plasma etching to etch through the hard cover curtain layer 30 and the compliance layer 26 'stop at the hall layer 22 (as shown in Figure 4). For example, a low-voltage plasma etching can be used, usually A pressure of 35 millitorr and an etching environment including 3, CF4, and argon (Ar), so that the flow ratio of 10sccm CH &, sCcm CL, and 900sccm Ar, the etching arrangement is y stop Stop at the bottom ARC layer or by endpoint detection methods commonly used in industry. The ARC layer 22 covers the metal surface as a protective film, and prevents fluorine contamination and invasion of the recessed portion during the passive etching. The photoresist mask is removed by using, for example, 〇2 / CF4 plasma to remove ash (as shown in Figure 5). This step is followed by a cleaning step to remove the photoresist residue and etch the polymer. This cleaning step It can include a wet chemical organic solvent: for example, EKC265 for ten minutes, isopropyl alcohol (IPA) for 400 seconds, followed by a rinse of deionized water and CO 2 agitator for 390 seconds, or a developing solution (such as Tetramethylammonium oxide (TMAH) can be used for 10 to 60 seconds. During photoresist removal and wet cleaning, the ARC layer also provides protection as a metal layer. After the cleaning step, a second plasma etch is performed to remove the ARC layer 22 in the opening on page 10 of 5087864. 5. Description of the invention (6) When the bottom ARC layer is composed of titanium nitride, the same The chemical etching procedure uses the first plasma etching step as described above, and the end point on the aluminum pad metal is measured. 'Mouse chemistry is not necessary in this case. In this preferred embodiment, titanium nitride is taught as the hard mask layer, and the second plasma etching must remove both the bottom ARC layer 22 and the hard mask layer 3 (shown in Figure 6) at the same time. However, this requirement does not need to be applied to other materials that can be used as a hard cover curtain layer. In some cases, some hard cover curtain layers can be left after etching of the bottom arc to expose the metal surface. In one of these cases, during the etching of the ARC layer 22, the hard mask layer 30 was stopped to prevent the passivation of the passivation layer, and the passivation layer of silicon nitride had about a 10 to 1 etch higher than that of titanium nitride. Rate, so if the passive protective layer is not protected by the hard mask layer during the etching, significant etching will occur. ^ Metal bond pads exposed to contact window openings can now be used as usual and continue with bond pad manufacturing processes such as wire bonding, solder bumps, or other similar processes (not shown). — The manufacturing process of the present invention provides an effective method of unfolding a contact window to a metal pad, in which the recessed part of the pad can be removed and fluorine pollution is greatly reduced, and only a hard cover curtain layer is added before the invention's high-quality metal bonding pad. Cover on the passive protection layer and keep the ARC layer on the metal bonding pad. 0 Although the present invention has been specifically shown, and reference is made to its preferred embodiments, various changes in form and details can be made without departing from the present invention. The spirit of Fan and his mouth are all understood by those who are familiar with this technique.

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Claims (1)

508684 六、 申請專利範圍 1 · 一種在積體電路製造中展開一接觸窗到一金屬 接合墊之方法: 提供一金屬接合墊覆接於一半導體基板上的隔 離層上; 沈積一抗反射塗佈(ARC)層覆接於該金屬接合 墊上; 沈積一鈍態保護層覆接於該ARC層上; 沈積一硬罩幕層覆接於該鈍態保護層上;508684 VI. Application Patent Scope 1 · A method for unrolling a contact window to a metal bonding pad in the manufacture of integrated circuits: providing a metal bonding pad to cover an isolation layer on a semiconductor substrate; depositing an anti-reflection coating (ARC) layer is overlaid on the metal bonding pad; a passivation layer is deposited over the ARC layer; a hard mask layer is overlaid on the passivation layer; 形成一光阻罩幕覆接於該硬罩幕層上,係具有 一開口,係形成在該接觸窗開口到該金屬接 合墊處; 蝕刻穿過未被該光阻罩幕所覆蓋的該硬罩幕層 及該鈍態保護層,且停止於該ARC層上; 之後,移除該光阻罩幕,且清洗該開口,其中 該A R C層保護該金屬接合墊;及 之後,蝕刻掉在開口内的該Arc層,其中覆 接於該鈍態保護層上的該硬罩幕層防止該鈍 恶保濩層的侵鍅,因此,防止該金屬接合墊A photoresist mask is formed to cover the hard mask layer and has an opening formed at the contact window opening to the metal bonding pad; the etching passes through the hard mask which is not covered by the photoresist mask. The mask layer and the passive protection layer are stopped on the ARC layer. After that, the photoresist mask is removed and the opening is cleaned, wherein the ARC layer protects the metal bonding pad; and then, it is etched off the opening. The Arc layer inside, wherein the hard cover curtain layer overlying the passivation protective layer prevents the invasion of the passivation layer, and therefore prevents the metal bonding pad 的污染’而在積體電路製造中完成展開該接 觸窗到該金屬接合塾。 2 ·如申請專利範圍第丄項所述之方法,其中該半 導體結構包括有半導體元件,如閘極電極、源 極及沒極區、及覆接於該隔離層的内導線。 3 ·如申請專利範圍第1項所述之方法,其中該金The contamination 'is completed in the fabrication of integrated circuits by unfolding the contact window to the metal junction. 2. The method as described in item (1) of the scope of patent application, wherein the semiconductor structure includes semiconductor elements, such as a gate electrode, a source electrode and a non-electrode region, and an inner wire covering the isolation layer. 3. The method as described in item 1 of the scope of patent application, wherein the gold 第13頁 508684Page 13 508684 屬接合墊係由鋁所組成。 其中該金 I呂〜鋼、 4 ·如申請專利範圍第i項所述之方法 屬接合墊包括有下列組群之一 ··銘 鋁-矽、及鋁-銅—石夕。 5 ·如申請專利範圍第丄項所述之方法, 沈積一阻障層於該金屬接合墊之下。、w匕括有 6 ·如中請專利範圍第!項所述之方法: 層包括有下列組群之-:氮化鈦、氮;:右 機ARC材料及無機arc材料,且具有—個在 1 0 0到5 0 0埃之間的厚度。 7 ·如申請專利範圍第1項所述之方法,其中該純 態保護層係由氮化矽所組成,係具有二個^、 5 0 0 0到2 0,0 〇 〇埃之間的厚度。 8 ·如申請專利範圍第1項所述之方法,其中該純 態保護層係由高密度電漿氧化物及氮化石夕所組 成’係具有一個在5000到20, 0 00埃之間的結 合厚度。 ϋ 9 ·如申請專利範圍第1項所述之方法,其中該硬 罩幕層係由氮化鈦、鎢化鈦、及有機ARC材 料所組成,且具有一個在1 0 0到5 0 0埃之間的 厚度。 1 〇 ·如申請專利範圍第1項所述之方法,其中蝕刻 穿過該硬罩幕層及該鈍態保護層的該步驟,係 包括有一個使用CHF3、CF4、及Ar化學的電The metal bonding pad is composed of aluminum. Among them, the gold I Lu ~ steel, 4 · The method described in item i of the patent application scope is a bonding pad that includes one of the following groups: · aluminum-silicon, and aluminum-copper-stone. 5. The method as described in item 丄 of the patent application scope, depositing a barrier layer under the metal bonding pad. , W Dagger is 6 · If you ask for patent scope, please! The method described in item: The layer includes one of the following groups :: titanium nitride, nitrogen;: right ARC material and inorganic arc material, and has a thickness between 100 and 500 Angstroms. 7. The method as described in item 1 of the scope of patent application, wherein the pure state protective layer is composed of silicon nitride and has a thickness between 2 ^, 5000 and 20,000 Angstroms. . 8. The method according to item 1 of the scope of the patent application, wherein the pure state protective layer is composed of high-density plasma oxide and nitride stone, and has a bond between 5000 and 20,000 Angstroms. thickness. ϋ 9 The method according to item 1 of the scope of patent application, wherein the hard mask layer is composed of titanium nitride, titanium tungsten, and organic ARC material, and has a thickness between 100 and 500 angstroms. Between thickness. 1 0. The method as described in item 1 of the scope of patent application, wherein the step of etching through the hard mask layer and the passivation protective layer includes an electrode using CHF3, CF4, and Ar chemistry. 第14頁 508684Page 14 508684 六、 申請專利範圍 漿蚀刻。 U•如申請專利範圍第1項所述之方法,其中移 該光阻罩幕的該步驟,係包括有使用02/c電、 漿去灰而清除該光阻罩幕。 1 2 ·如申請專利範圍第1項所述之方法,盆中、、主洗 該開口的該步驟,係包括有一濕式化學有2溶 劑、異丙醇、及去離子水沖洗劑。 〆 13 ·如申請專利範圍第1項所述之方法,其中餘 掉在開口内的該ARC層的該步驟,係包括有 一個使用CHF3、CL、及Ar化學的電漿蝕刻。 1 4 ·如申請專利範圍第1項所述之方法,其^餘刻 掉在開口内的該ARC層的該步驟,同時钱刻/ 掉覆接在該鈍態保護層上的該硬罩幕層。 15 · —種在積體電路製造中展開一接觸窗^ 一金屬 接合墊之方法: 提供半導體元件結構於一半導體結構上及半導 體結構中,其中該半導體元件結構係由—隔 離層所覆蓋; 沈積一金屬接合墊覆接於該隔離層上; 沈積一抗反射塗佈(ARC)層覆接於該金屬接合 墊上; 沈積一鈍態保護層覆接於該ARC層上; 沈積一硬罩幕層覆接於該鈍態保護層上; 形成一光阻罩幕覆接於該硬罩幕層上,係I#Sixth, the scope of patent application slurry etching. U • The method according to item 1 of the scope of patent application, wherein the step of removing the photoresist mask includes removing the photoresist mask by using 02 / c electricity and slurry to remove ash. 1 2 · According to the method described in item 1 of the scope of patent application, the step of washing the opening in the basin and the main body includes a wet chemical solvent, isopropyl alcohol, and deionized water rinse agent. 〆 13 · The method according to item 1 of the scope of patent application, wherein the step of the ARC layer remaining in the opening includes a plasma etching using CHF3, CL, and Ar chemistry. 1 4 · The method as described in item 1 of the scope of the patent application, wherein the step of cutting off the ARC layer in the opening is simultaneously engraved / dropped the hard cover overlaid on the passive protection layer Floor. 15 · —A method for expanding a contact window in the manufacture of integrated circuits ^ a metal bonding pad: providing a semiconductor element structure on and in a semiconductor structure, wherein the semiconductor element structure is covered by an isolation layer; deposition A metal bonding pad is overlaid on the isolation layer; an anti-reflection coating (ARC) layer is deposited over the metal bonding pad; a passive protective layer is overlaid over the ARC layer; a hard cover curtain layer is overlaid. Overlaid on the passive protection layer; forming a photoresist cover screen overlaid on the hard cover screen layer, I # % 15 1 ^^' --—% 15 1 ^^ '--- 一開口’係形成在該接觸窗開口到該金屬接 合墊; 蝕刻穿過未被該光阻罩幕所覆蓋的該硬罩幕層 及該鈍態保護層,且停止於該ARC層上;An opening ’is formed at the contact window opening to the metal bonding pad; the etching passes through the hard mask layer and the passive protection layer not covered by the photoresist mask, and stops on the ARC layer; 之後,移除該光阻罩幕,且清洗該開口,其中 該ARC層保護該金屬接合墊;及 之後,蝕刻掉在開口内的該Arc層,其中覆 接於該純態保護層上的該硬罩幕層防止該鈍 態保護層的侵蝕,因此,防止該金屬接合墊 的污染’而在積體電路製造中完成展開該接 觸窗到該金屬接合墊。 1 6 ·如申請專利範圍第丨5項所述之方法,其中該 半導體元件結構包括有閘極電極、源極及汲極 區、及内導線。 1 7 ·如申請專利範圍第丨5項所述之方法,其中該 金屬接合墊包括含有下列組群之一:鋁、鋁-銅、鋁-石夕、及鋁-銅-石夕。 1 8 ·如申請專利範圍第1 5項所述之方法,尚包括 有沈積一阻障層於金屬接合墊下。After that, the photoresist mask is removed, and the opening is cleaned, wherein the ARC layer protects the metal bonding pad; and then, the Arc layer in the opening is etched away, wherein the Arc layer overlying the pure protective layer is etched away. The hard cover curtain layer prevents the passivation of the passivation protective layer, and therefore, prevents the metal bonding pad from being contaminated. In the manufacturing of integrated circuits, the contact window is completed to the metal bonding pad. 16 · The method according to item 5 of the scope of the patent application, wherein the semiconductor device structure includes a gate electrode, a source and a drain region, and an inner conductor. 17 · The method as described in item 5 of the patent application scope, wherein the metal bonding pad includes one of the following groups: aluminum, aluminum-copper, aluminum-stone, and aluminum-copper-stone. 18 · The method according to item 15 of the scope of patent application, further comprising depositing a barrier layer under the metal bonding pad. 1 9 ·如申請專利範圍第丨5項所述之方法,其中該 ARC層包括有氮化鈦、氮化鎢、有機ARC材 料、及無機ARC材料,真具有以一個在100 到500埃之間的厚度。 2 0 ·如申請專利範圍第丨5項所述之方法,其中該19 · The method as described in item 5 of the patent application scope, wherein the ARC layer includes titanium nitride, tungsten nitride, organic ARC material, and inorganic ARC material, and has a range of 100 to 500 angstroms. thickness of. 2 0 · The method described in item 5 of the scope of patent application, wherein 508684 六、申請專利範圍 "' 1 鈍恶保濩層包括有氮化矽,係具有一個在5 0 0 0 到20000埃之間的厚度。 21 ·如f請專利範圍第15項所述之方法,其中該 ^態保遵層包括有高密度電漿氧化矽及氮化 石夕’係具有一個在5 0 0 0到2 0 0 0 0埃之間的厚 度。 22如申明專利範圍第15項所述之方法,其中該 硬罩幕層包括有氮化鈦、氮化鎢、有機ARC 材料、及無機ARC材料,且具有以一個在1〇0 到5 0 〇埃之間的厚度。 23 ·如申請專利範圍第1 5項所述之方法,其中蝕 刻穿過該硬罩幕層及鈍態保護層的該步驟,係 包括有一個使用CHF3、CF4 化學的電漿 蝕刻。 24 ·如申請專利範圍第15項所述之方法,其中移 除該光阻罩幕層包括有使用o2/cf4電漿去灰而 清除該光阻罩幕。 25 ·如申請專利範圍第丨5項所述之方法,其中清 除開口的該步驟,係包括有一濕式化學有機溶 劑、異丙醇、及去離子水洗滌。 •如申請專利範圍第1 5項所述之方法,其中蝕 刻掉在開口内的該ARC層的該步驟,係包括 有一個使用CHI、CF^Ar化學的電漿蝕刻。 如申請專利範圍第1 5項所述之方法,其中蝕508684 VI. Scope of patent application " '1 The passivation layer includes silicon nitride, which has a thickness between 5000 and 20000 angstroms. 21 · The method as described in item 15 of the patent scope, wherein the compliance layer includes high-density plasma silicon oxide and nitride nitride. The system has a thickness between 5 0 0 and 2 0 0 0 0 Angstroms. Between thickness. 22. The method according to item 15 of the stated patent scope, wherein the hard mask layer includes titanium nitride, tungsten nitride, organic ARC material, and inorganic ARC material, and has a range of 100 to 50. Angstrom thickness. 23. The method according to item 15 of the scope of patent application, wherein the step of etching through the hard mask layer and the passivation protective layer includes a plasma etching using CHF3, CF4 chemistry. 24. The method according to item 15 of the scope of patent application, wherein removing the photoresist mask layer includes removing the photoresist mask using an o2 / cf4 plasma to remove ash. 25. The method according to item 5 of the scope of the patent application, wherein the step of removing the openings comprises washing with a wet chemical organic solvent, isopropyl alcohol, and deionized water. The method according to item 15 of the scope of patent application, wherein the step of etching the ARC layer in the opening includes a plasma etching using CHI and CF ^ Ar chemistry. The method as described in item 15 of the scope of patent application, wherein 28 刻掉在開口内的該ARC層的該步驟,同時鍅 刻掉在該鈍態保護層上的該硬罩幕層。 一種在積體電路製造中展開一接觸窗到一鋁接 合墊之方法: 提供半導體元件結構於一半導體結構上及半導 體結構中,其中該半導體元件結構係由一隔 離層所覆蓋; 沈積一鋁接合墊覆接於該隔離層上; 沈積一抗反射塗佈(ARC)層覆接θ於該鋁接合 上; 沈積一氮化矽鈍態保護層覆接於該AR(:層上; /尤積一氬化鈦層覆接於該鈍態保護層上; 形成一光阻罩幕覆接於該硬罩幕層上,係具 一開口,係形成在該接觸窗開口到該鋁接 墊; 姓刻穿過未被言亥《阻罩幕覆蓋的該氮化欽層及 5亥鈍態保護層,且停止於該ARC層; 之後’移除該光阻罩|,且清洗該開口 5亥ARC層保護該銘接合墊;及 之後,蝕刻掉在開〇内 接於該鈍態保護層上 護層的侵#,因此, 染,而在積體電路製 到該鋁接合墊。 的該ARC層,其中覆 的氮化鈦防止該鈍態保 防止該金屬接合墊的污 造中完成展開該接觸窗 508684 六、申請專利範圍 29 ·如申請專利範圍第28項所述之方法,其中該 半導體元件結構包括有閘極電極、源極及汲 極、及内導線。 30 ·如申請專利範圍第28項所述之方法,其中該 ARC層包括有氮化鈦,係具有一餓在1〇〇到5〇〇 埃之間的厚度。 3 1 ·如申請專利範圍第28項所述之方法,其中蝕 刻穿過該氮化鈦層及該鈍態保護層的該步驟, 包括有一個使用CHF3、CF4 &Ar化學的電漿 餘刻。 32 ·如申請專利範圍第28項所述之方法,其中移 除該光阻罩幕的該步驟,係包括有使用& /cf4 電漿去灰而清除該光阻罩幕。 33 ·如申請專利範圍第28項所述之方法,其中清 除該開口的該步驟,係包括有一濕式化學有機 >谷劑、異丙醇、及去離子水洗務。 34 ·如申請專利範圍第28項所述之方法,其中蝕 刻掉在開口内的該ARC層的該步驟,係包括 有一個使用CHF3、CF4及Ar化學的電漿蝕刻。 3 5 ·如申請專利範圍第2 8項所述之方法,其中餘 刻掉在開口内的該ARC層的該步驟,同時蝕 刻掉在該鈍態保護層上的該氮化鈦層。28 The step of engraving the ARC layer in the opening, and the engraving of the hard cover curtain layer on the passive protective layer. A method for developing a contact window to an aluminum bonding pad in the manufacture of integrated circuits: providing a semiconductor element structure on and in a semiconductor structure, wherein the semiconductor element structure is covered by an isolation layer; depositing an aluminum joint A pad is attached to the isolation layer; an anti-reflection coating (ARC) layer is deposited over the aluminum junction; a silicon nitride passivation protective layer is deposited over the AR (: layer; / youji A titanium argon layer is overlaid on the passive protective layer; a photoresist mask is overlaid on the hard cover, with an opening formed at the contact window opening to the aluminum pad; Carved through the nitride layer and the 5H passivation protective layer that were not covered by the mask, and stopped at the ARC layer; then 'removed the photoresist mask | and cleaned the opening 5HARC Layer and protect the bonding pad; and then, etch away the intrusion layer of the protective layer on the passivation protective layer, so that the aluminum bonding pad is fabricated on the integrated circuit. The coated titanium nitride prevents the passive state and prevents the metal bonding pads from The contact window 508684 was unfolded during fouling. 6. Application for patent scope 29. The method described in item 28 of the patent application scope, wherein the semiconductor device structure includes a gate electrode, a source and a drain, and an inner conductor. The method according to item 28 of the patent application, wherein the ARC layer includes titanium nitride and has a thickness between 100 and 500 angstroms. 3 1 The method according to the above item, wherein the step of etching through the titanium nitride layer and the passivation protective layer includes a plasma finish using CHF3, CF4 & Ar chemistry. 32. Such as the scope of application for patent No. 28 The method described in item 1, wherein the step of removing the photoresist mask includes removing the photoresist mask by using & / cf4 plasma to remove dust. 33. As described in item 28 of the scope of patent application The method, wherein the step of removing the opening, includes a wet chemical organic > cereal, isopropanol, and deionized water washing. 34. The method according to item 28 of the scope of patent application, wherein the etching is This step of the ARC layer in the opening It includes a plasma etching using CHF3, CF4, and Ar chemistry. 3 5 · The method as described in item 28 of the patent application scope, wherein the step of etching the ARC layer in the opening is etched at the same time The titanium nitride layer dropped on the passive protective layer.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102556945A (en) * 2010-12-13 2012-07-11 台湾积体电路制造股份有限公司 Method to prevent metal pad damage in wafer level package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102556945A (en) * 2010-12-13 2012-07-11 台湾积体电路制造股份有限公司 Method to prevent metal pad damage in wafer level package
CN102556945B (en) * 2010-12-13 2015-01-28 台湾积体电路制造股份有限公司 Micro-electronics device and manufacturing method of integrated circuit of micro-electronics device

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