507381507381
五、發明說明（） 發明領域： 本發明係有關於一種液晶顯示器（LCD)，且特別有關於 一種液晶顯示器中薄膜電晶體（Thin-Film Transistor，TFT) 之結構及其製造方法。 發明背景： 由於多媒體的迅速發展，使得使用者對週邊之聲光設 備要求愈來愈高。以往常用的陰極射線管（Cathode Ray Tube ’ CRT)類型的顯示器，由於體積過於龐大，在現今標 榜經、薄、短、小的時代_，已漸不敷需求。因此，近年 來有許多輕薄型平面顯示器（Flat Panel Display)技術相繼 被開發出來，如液晶顯示器（Liquid Crystal Display，LCD)、 電漿.平面顯示器（Plasma Display Panel，PDP)，以及場發射 顯示器（Fie Id Emission Display，FED)，已漸漸成為未來顯 示器之主流。 其中液晶顯示器（LCD)因為技術發展成熟，已從傳統 的單色顯示逐漸發展至彩色顯示，並且廣泛地應用在各種 數位顯示系統中，例如個人電腦、筆記型電腦、數位手錶 以及行動電話、個人數位助理（PDA)等等。其中，使用薄膜 電晶體（Thin Film Transistor，TFT)之主動陣列型液晶顯示 本紙張尺度適用中國國家標準（CNS)A4規烙（210 X 297公t ) (請先閱讀背面之注意事項再填寫本頁) 訂---------線 經沒部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 507381 A： _B7_ 五、發明說明（） 器是一種具有較佳顯示效能的液晶顯示器。 一般而言，TFT-LCD主要是由頂面透明導電的氧化銦 錫（ITO)頂層基板，搭配表面具有薄膜電晶體陣列的底層透 明玻璃基板，並且在頂層基板與底層基板之間灌入液晶材 料，藉以構成面板的主要部分。在每一個圖素（pixel)單元 中，均對應具有一個薄膜電晶體開關，用以控制圖素電極 的訊號電壓，改變液晶分子的排列方向，藉由開關每一個 薄膜電晶體，即可控制每一個對應圖素是否透光。並且， 藉由搭配彩色濾光片即可達到全彩之效果。 一般薄膜電晶體陣列均是製作在透明玻璃基板上，傳 統上每一個薄膜電晶體所佔用面積都相當地大，導致每個 圖素之開口率無法有效地提昇。隨著消費者對LCD解析度 之要.求升高，每個圖素可使用之面積亦相對地降低，若無 法將薄膜電晶體的尺寸降低勢必影響每個圖素的透光率， 進而降低LCD的顯示效果。傳統上，薄膜電晶體尺寸縮小 往往受限於玻璃基板的平坦度而無法提昇，因為玻璃結構 係為固流體狀態，而非完美的結晶結構，所以玻璃基板表 面無法像半導體基板一般擁有極佳的平坦度。由於玻璃基 板平坦度不佳，致使薄膜電晶體製作時，微影步驟的臨界 尺寸（C r i t i c a 1 D i m e n s i ο η)無法縮小，是故傳統的薄膜電晶 體結構必然受限於玻璃基板的平坦度，若要將其尺寸再往 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公坌） (請先閲讀背面之注意事項再填寫本頁) I电 Τ y*·^^1'·· n ϋ n ·1 ί 1_ϋ n 』 · m flu n ·%· 經濟部智慧財產局員工消費合作社印製 507381 A： ___B7_ 五、發明說明（） 下降，即會受到限制。 發明目的及概述： 鑒於上述之發明背景中，傳統的薄膜電晶體結構受到 玻璃基板平坦度以及微影步驟_臨界尺寸的限制，無法降 低其尺寸。因此，本發明提供一種液晶顯示器之薄膜電晶 體結構及其製造方法，在薄膜電晶體令形成傾斜結構，利 用薄膜成長厚度控制薄膜電晶體的通道長度，使其不會受 限於玻璃基板的平坦度以及微影時的光學限制，可以有效 地縮小薄膜電晶體的尺寸。 從一觀點，本發明提供一種薄膜電晶體結構，係架構 在一玻璃基板上。此結構至少包括一第一摻雜矽層，位於 玻璃基板上；一氧化矽層，位於第一摻雜矽層上；一第二 擦雜梦層，位於氧化石夕層上，氧化石夕層與第二捧雜^夕層之 邊緣具有一傾斜結構；一矽層，覆蓋於傾斜結構上，並且 覆蓋傾斜結構周圍之部分第一摻雜矽層與第二摻雜矽層； 一閘極介電層，覆蓋矽層、第一摻雜矽層與第二摻雜矽層； 以及一閘極金屬層，位於閘極介電層上，且對準傾斜結構。 從一觀點，本發明提供一種薄膜電晶體之製作方法， 此方法至少包括下列步驟。首先在一基板上形成一第一摻 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I-------------------訂----------線 (請先W讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 507381 A7 B7_ 五、發明說明（) 雜矽層，接著在第一摻雜矽層上依序形成一氧化矽層與一 第二摻雜矽層，之後去除部分第二摻雜矽層與氧化矽層， 在氧化矽層與第二摻雜矽層之邊緣形成一傾斜結構，並暴 露出部分第一摻雜矽層。然後在傾斜結構上形成一矽層， 並且覆蓋位於傾斜結構周圍之部分第一摻雜矽層與第二摻 雜矽層。接著形成一閘極介電層，覆蓋在矽層以及周圍的 第一摻雜矽層與第二摻雜矽層上。之後在閘極介電層上形 成一閘極導電層，且對準傾斜結構。 從另一觀點，本發明提供一種薄膜電晶體之製作方 法，此方法至少包括下列步驟。首先在一基板上形成一第 一石夕層，接著在第一石夕層上依序形成一氧化石夕層與一第二 石夕層，之後去除部分第二麥層與氧化碎層，在氧化碎層與 第二矽層之邊緣形成一傾斜結構，並暴露出部分第一矽 層。.然後進行一摻雜步驟，在第一矽層與第二矽層之暴露 部分中掺雜一摻質。接著在傾斜結構上形成一第三矽層， 並且覆蓋位於傾斜結構周圍之部分第一矽層與第二矽層。 然後形成一閘極介電層，覆蓋矽層以及周圍的第一矽層與 第二矽層。之後在閘極介電層上形成一閘極導電層，且對 準傾斜結構。 本發明之薄膜電晶體係藉由控制氧化矽層的厚度以及 傾斜結構之傾斜角度，可以決定薄膜電晶體適當的通道長 本紙張尺度適用中國國家標準（CNS)/VI規烙<210 X 297公 --；---------11---訂 ---I---- (請先«讀背面之注意事項再填寫本頁) 507381 B7 五、發明說明（） 度，不會受到玻璃基板表面平坦度的限制，而且·在形成傾 斜結構時，不會受到微影步驟的光學限制，藉此可大幅地 縮小薄膜電晶體的尺寸，並增加每個圖素的開口率。 圖式簡單說明： 本發明的較佳實施例將於往後之說明文字中辅以下列 圖形做更詳細的闡述，其中： 第1圖是繪示本發明之一較佳實施例之結構剖面示意 圖。 第2A-2E圖是繪示本發明之一較佳實施例之製程剖面 示意圖。 第3 A-3 C圖是繪示本發明之一變化實施例之製程剖面 示意圖。 圖號對照說明： -----:丨----—--------訂--------- (請先Μ讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 100 玻璃基板 1 02 第一摻雜矽層 104 氧化矽層 105 傾斜結構 106 第二摻雜矽層 107 光阻層 108 矽層 109 暴露區域 1 10 閘極介電層 1 12 閘極金屬層 1 14 絕緣層 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公:Ϊ ) 118 金屬導線層 202 第一 &夕層 205 傾斜結構 207 光阻層 2 11 摻雜區塊 Θ 傾斜角度 507381V. Description of the invention () Field of the invention: The present invention relates to a liquid crystal display (LCD), and more particularly to a structure of a thin-film transistor (TFT) in a liquid crystal display and a manufacturing method thereof. Background of the Invention: Due to the rapid development of multimedia, users have increasingly higher requirements for peripheral sound and light equipment. Cathode ray tube (CRT) type displays, which have been commonly used in the past, are too large to meet the demand in today's era of thin, short, and small. Therefore, in recent years, many thin panel display (Flat Panel Display) technologies have been successively developed, such as Liquid Crystal Display (LCD), Plasma Display Panel (PDP), and field emission display ( Fie Id Emission Display (FED) has gradually become the mainstream of future displays. Among them, the liquid crystal display (LCD) has gradually developed from the traditional monochrome display to the color display due to the mature technology. Digital Assistant (PDA) and more. Among them, the thin film transistor (Thin Film Transistor, TFT) active array liquid crystal display of this paper is applicable to Chinese National Standard (CNS) A4 (210 X 297 g) (Please read the precautions on the back before filling in this Page) Order --------- Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and printed by 507381 A: _B7_ V. Description of the invention LCD performance display. Generally speaking, TFT-LCD is mainly composed of a transparent top conductive indium tin oxide (ITO) top substrate, a bottom transparent glass substrate with a thin film transistor array on the surface, and a liquid crystal material filled between the top substrate and the bottom substrate. To form the main part of the panel. In each pixel unit, there is a thin film transistor switch to control the signal voltage of the pixel electrode and change the arrangement direction of the liquid crystal molecules. By switching each thin film transistor, each pixel can be controlled. Whether a corresponding pixel is transparent. In addition, the effect of full color can be achieved by matching color filters. Generally, thin-film transistor arrays are fabricated on transparent glass substrates. Traditionally, each thin-film transistor occupies a relatively large area, which results in that the aperture ratio of each pixel cannot be effectively improved. With the increase in consumer demand for LCD resolution, the area available for each pixel is also relatively reduced. If the size of the thin film transistor cannot be reduced, the light transmittance of each pixel will be affected, thereby reducing LCD display effect. Traditionally, the reduction in the size of thin-film transistors is often limited by the flatness of the glass substrate and cannot be improved. Because the glass structure is a solid fluid state, rather than a perfect crystalline structure, the surface of the glass substrate cannot have an excellent quality like a semiconductor substrate. flatness. Because the flatness of the glass substrate is not good, the critical dimension of the lithography step (Critica 1 D imensi ο η) cannot be reduced when the thin film transistor is manufactured, so the traditional thin film transistor structure is bound to be limited by the flatness of the glass substrate. If you want to apply the size of this paper to the Chinese standard (CNS) A4 size (210 x 297 cm) (please read the precautions on the back before filling this page) I Τ y * · ^^ 1 ' ·· n ϋ n · 1 ί 1_ϋ n 』· m flu n ·% · Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 507381 A: ___B7_ 5. The description of the invention () will be restricted if it decreases. Object and summary of the invention: In view of the above background of the invention, the traditional thin film transistor structure is limited by the flatness of the glass substrate and the lithography step_critical size, which cannot reduce its size. Therefore, the present invention provides a thin film transistor structure of a liquid crystal display and a manufacturing method thereof. The thin film transistor is formed into an inclined structure, and the growth length of the thin film transistor is used to control the channel length of the thin film transistor so that it is not limited to the flatness of the glass substrate And optical limitations during lithography can effectively reduce the size of thin film transistors. From one perspective, the present invention provides a thin film transistor structure with a frame structure on a glass substrate. This structure includes at least a first doped silicon layer on a glass substrate; a silicon oxide layer on the first doped silicon layer; a second doped silicon layer on the stone oxide layer and a stone oxide layer An edge with the second doped layer has an inclined structure; a silicon layer covering the inclined structure and covering a portion of the first doped silicon layer and the second doped silicon layer around the inclined structure; a gate dielectric The electrical layer covers the silicon layer, the first doped silicon layer and the second doped silicon layer; and a gate metal layer, which is located on the gate dielectric layer and is aligned with the inclined structure. From one perspective, the present invention provides a method for manufacturing a thin film transistor. The method includes at least the following steps. First, form a first doped paper on a substrate. Applicable to China National Standard (CNS) A4 (210 X 297 mm) I ------------------- Order ---------- line (please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 507381 A7 B7_ V. Description of the invention () Miscellaneous silicon layer, then A silicon oxide layer and a second doped silicon layer are sequentially formed on the first doped silicon layer, and then a portion of the second doped silicon layer and the silicon oxide layer are removed, and the edges of the silicon oxide layer and the second doped silicon layer are removed. An inclined structure is formed, and a portion of the first doped silicon layer is exposed. Then, a silicon layer is formed on the inclined structure and covers a portion of the first doped silicon layer and the second doped silicon layer located around the inclined structure. Next, a gate dielectric layer is formed to cover the silicon layer and the surrounding first and second doped silicon layers. A gate conductive layer is then formed on the gate dielectric layer and aligned with the inclined structure. According to another aspect, the present invention provides a method for manufacturing a thin film transistor. The method includes at least the following steps. First, a first stone layer is formed on a substrate, and then a first stone layer and a second stone layer are sequentially formed on the first stone layer, and then a portion of the second wheat layer and the oxidized debris layer are removed. An inclined structure is formed on the edge of the second oxide layer and the second silicon layer, and a part of the first silicon layer is exposed. A doping step is then performed to dope a dopant into the exposed portions of the first silicon layer and the second silicon layer. Then, a third silicon layer is formed on the inclined structure, and covers a portion of the first silicon layer and the second silicon layer located around the inclined structure. A gate dielectric layer is then formed to cover the silicon layer and the surrounding first and second silicon layers. Then, a gate conductive layer is formed on the gate dielectric layer, and the inclined structure is aligned. The thin film transistor system of the present invention can determine the appropriate channel length of the thin film transistor by controlling the thickness of the silicon oxide layer and the tilt angle of the inclined structure. Public-; --------- 11 --- Order --- I ---- (please «read the notes on the back before filling this page) 507381 B7 V. Description of the invention () Degree, It is not limited by the flatness of the surface of the glass substrate, and when forming an inclined structure, it is not subject to the optical limitations of the lithography step, thereby greatly reducing the size of the thin film transistor and increasing the aperture ratio of each pixel . Brief description of the drawings: The preferred embodiment of the present invention will be described in more detail in the following explanatory text with the following figures, where: Figure 1 is a schematic cross-sectional view showing the structure of a preferred embodiment of the present invention . Figures 2A-2E are schematic cross-sectional views illustrating a process of a preferred embodiment of the present invention. Figures 3A-3C are schematic cross-sectional views showing a process of a modified embodiment of the present invention. Drawing number comparison description: -----: 丨 -------------- Order --------- (Please read the precautions on the back before filling this page) Economy Printed by the Intellectual Property Bureau Staff Consumer Cooperative 100 Glass substrate 1 02 First doped silicon layer 104 silicon oxide layer 105 tilted structure 106 second doped silicon layer 107 photoresist layer 108 silicon layer 109 exposed area 1 10 gate dielectric Layer 1 12 Gate metal layer 1 14 Insulation layer This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 male: Ϊ) 118 Metal wire layer 202 First & evening layer 205 Inclined structure 207 Photoresist layer 11 Doped block Θ tilt angle 507381
AT -_ B7 五、發明說明（） 116 接觸窗插塞 200 玻瑀基板 2 04 氧化碎層 206 第二矽層 209 暴露區域 L 寬度 發明詳細說明： 請參照第1圖，其繪示本發明之一較佳實施例之薄膜 電晶體的結構剖面示意圖。本發明之薄膜電晶體係架構在 基板1 00上，例如是玻璃基板，或是其他高透光基板。本 發明之薄膜電晶體包括一第一摻雜矽層 1 02，以及依序堆 疊在第一摻雜矽層102上之介電層104與第二摻雜矽層 1 06。介電層1 04較佳為氧化矽層，並在此以氧化矽層為例 進行說明。氧化矽層104與第二摻雜矽層106之面積由下 而上逐漸縮小，並在其邊緣形成一個由中央向邊緣漸細的 傾斜結構1 0 5。在傾斜結構1 0 5之邊緣末端尚多出部分第 一摻雜矽層1 02，與第二摻雜矽層1 06，分別作為源極或是 汲極。第一摻雜矽層1 02與第二摻雜矽層1 06可為p型摻 雜矽層或是η型摻雜矽層。在傾斜結構1 0 5上覆蓋有一矽 層1 0 8，並且覆蓋傾斜結構1 0 5周圍的部分第一摻雜矽層 1 02與第二摻雜矽層1 06，此矽層1 08將作為源極與汲極之 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ΚΙί-ΙΙ.------------------- — 訂·-------- SI (請先閱讀背面之注意事項再填冩本頁) 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 507381 A7 B7_ 五、發明說明（) 間的通道。在整個基板1 0 0上形成一閘極介電層.1 1 0，例 如是氧化矽層，或是其他具有高介電常數之材料層。在閘 極介電層1 I 0上則形成有一閘極導電層1 1 2，對準底下的 傾斜結構1 0 5，一般閘極導電層 1 1 2係由金屬所構成，例 如(A1)、銅（C u)等，以作為薄膜電晶體之閘極，由上述之 結構即構成本發明之薄膜電晶體。在薄膜電晶體上通常會 覆蓋一層絕緣層1 1 4，例如是氧化矽層，並且在絕緣層1 1 4 與閘極介電層1 i 0中形成接觸窗插塞1 1 6，分別將第一摻 雜矽層102與第二摻雜矽層106(源極/汲極），連接至外部 的導線層11 8。 本發明之傾斜結構的傾斜角度約在2 - 6 0度之間，且較 佳約在5 - 3 0度之間。藉由在氧化矽層1 0 4與第二摻雜矽層 1 06邊緣形成傾斜結構1 05，薄膜電晶體的通道長度將由氧 化矽層1 04以及傾斜結構1 0 5之傾斜角度所決定，即使基 板1 0 0之平坦度相對較低，也不會受限於微影步驟的光學 限制。 接著將對本發明之薄膜電晶體的製作方法作說明。第 2 A-2 E圖是繪示本發明之一較佳實施例之薄膜電晶體的製 程剖面示意圖。請參照第2A圖，首先在基板1 00上形成第 一摻雜矽層1 0 2，其可為p型摻雜矽層，摻雜有摻質比如 是硼（B)等，或是η型摻雜矽層，摻雜有摻質比如是磷（P) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) Γ • s u Is n m m III —19 ^ < f n m flu m · 4 經濟部智慧財產局員工消費合作社印製 507381 A： Π7 _ 五、發明說明（） 或砷（As)等。第一摻雜矽層1 02的形成方法例如是以原處 摻雜（In-situdoped)直接沉積而成的摻雜複晶矽層，或是先 形成一層複晶矽層’然後以離子植入技術在複晶矽層中植 入摻質。然後以傳統的微影及蝕刻技術，去除不需要的部 分’定義出所需要的區域。 請參照第2B圖，接著在第一摻雜矽層丨〇2上依序形成 氧化矽層1 04與第二摻雜矽層1 06。氧化矽層1 〇4例如是 以化學氣相沉積法（C V D)形成，而第二摻雜石夕層1 〇 6則可使 用跟第一摻雜石夕層1 〇 2相同的技術形成，且第二捧雜石夕層 106必須具有跟第一摻雜;g夕層102同型的摻質，均為p型 或是η型。 然後進行傾斜結構105的形成步驟。首先在第二摻雜 石夕層106上形成一光阻層107，然後以傳統的微影技術， 進行曝光、顯影等步驟，在光阻層1〇7上定義出所需的圖 案’覆蓋在預定的區域上。然後以圖案化的光阻層1 〇 7為 罩幕，對第二摻雜矽層丨〇6進行傾斜蝕刻，藉由適當控制 製程參數，在圖案化光阻層丨07的邊緣，可蝕刻出低角度 之傾斜層，之後變換適當的蝕刻氣體，並控制製程參數， 繼續蝕刻底下的氧化矽層1 04，直到暴露出第一摻雜矽層 102,在第一摻雜矽層ι〇2與氧化矽層1〇4的邊緣形成傾斜 結構1 0 )，並且在傾斜結構丨〇 5的周圍邊緣暴露出第一摻 本纸張尺度適用中國國家標準（CNSM4規格（210 X 297公餐） n it ϋ ϋ i·^ M9mw «1 ft ϋ n t— —tv ϋ n ϋ ϋ- m tn «n ^ ^ 4 n n i-— n ·ϋ Mmamt MmmmMM I /P 言 矣 (請先閱讀背面之注意事項再填寫本頁) JO丄AT -_ B7 V. Description of the invention (116) 116 Contact window plug 200 Glass substrate 2 04 Oxidation debris layer 206 Second silicon layer 209 Exposed area L width Detailed description of the invention: Please refer to FIG. 1 which shows the invention Schematic sectional view of the structure of a thin film transistor in a preferred embodiment. The thin film transistor system of the present invention is structured on a substrate 100, such as a glass substrate, or other highly transparent substrates. The thin film transistor of the present invention includes a first doped silicon layer 102, and a dielectric layer 104 and a second doped silicon layer 106 stacked on the first doped silicon layer 102 in this order. The dielectric layer 104 is preferably a silicon oxide layer, and a silicon oxide layer is used as an example for description herein. The areas of the silicon oxide layer 104 and the second doped silicon layer 106 gradually decrease from bottom to top, and an inclined structure 10 5 is formed at the edges of the silicon oxide layer 104 and the second doped silicon layer. A portion of the first doped silicon layer 102 and the second doped silicon layer 106 at the edge ends of the inclined structure 105 are used as the source or the drain, respectively. The first doped silicon layer 102 and the second doped silicon layer 106 may be a p-type doped silicon layer or an n-type doped silicon layer. A silicon layer 108 is covered on the inclined structure 105, and a portion of the first doped silicon layer 102 and the second doped silicon layer 106 is covered around the inclined structure 105, and this silicon layer 108 will be used as The source and drain dimensions of the paper are in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) ΚΙί-ΙΙ .------------------- — Order · -------- SI (Please read the notes on the back before filling out this page) Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by 507381 A7 B7_ V. Invention Description () between channels. A gate dielectric layer .10 is formed on the entire substrate 100, such as a silicon oxide layer, or other material layer with a high dielectric constant. A gate conductive layer 1 12 is formed on the gate dielectric layer 1 I 0, which is aligned with the inclined structure 105 below. Generally, the gate conductive layer 1 1 2 is made of metal, such as (A1), Copper (Cu) is used as the gate of the thin film transistor, and the thin film transistor of the present invention is constituted by the above structure. A thin film transistor is usually covered with an insulating layer 1 1 4 such as a silicon oxide layer, and a contact window plug 1 1 6 is formed in the insulating layer 1 1 4 and the gate dielectric layer 1 i 0, respectively. A doped silicon layer 102 and a second doped silicon layer 106 (source / drain) are connected to the external wiring layer 118. The inclination angle of the inclined structure of the present invention is between about 2 and 60 degrees, and more preferably between about 5 and 30 degrees. By forming an inclined structure 105 on the edge of the silicon oxide layer 104 and the second doped silicon layer 106, the channel length of the thin film transistor will be determined by the inclination angle of the silicon oxide layer 104 and the inclined structure 105. The flatness of the substrate 100 is relatively low and is not limited by the optical limitations of the lithography step. Next, a method for manufacturing the thin film transistor of the present invention will be described. Figures 2A-2E are schematic cross-sectional views showing a process of a thin film transistor according to a preferred embodiment of the present invention. Please refer to FIG. 2A. First, a first doped silicon layer 102 is formed on the substrate 100, which may be a p-type doped silicon layer, doped with a dopant such as boron (B), or an n-type. Doped silicon layer, doped with a dopant such as phosphorus (P) This paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) Γ • su Is nmm III —19 ^ < fnm flu m · 4 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 507381 A: Π7 _ 5. Description of the invention () or arsenic (As). The method for forming the first doped silicon layer 102 is, for example, a doped polycrystalline silicon layer directly deposited by in-situdoped deposition, or a polycrystalline silicon layer is formed first, and then implanted by ions. Technology implants a dopant in a polycrystalline silicon layer. Then, by using conventional lithography and etching techniques, unnecessary portions are removed 'to define the required area. Referring to FIG. 2B, a silicon oxide layer 104 and a second doped silicon layer 106 are sequentially formed on the first doped silicon layer 1002. The silicon oxide layer 104 is formed by, for example, chemical vapor deposition (CVD), and the second doped stone layer 100 can be formed using the same technique as the first doped stone layer 100, and The second doped stone layer 106 must have the same type of dopants as the first doped layer; the g layer 102 is all p-type or n-type. Then, a step of forming the inclined structure 105 is performed. First, a photoresist layer 107 is formed on the second doped stone layer 106, and then the conventional lithography technology is used to perform exposure, development and other steps to define the required pattern on the photoresist layer 107. On a predetermined area. Then, using the patterned photoresist layer 107 as a mask, the second doped silicon layer 010 is subjected to oblique etching, and by appropriately controlling the process parameters, the edges of the patterned photoresist layer 07 can be etched out. A low-angle inclined layer, and then change the appropriate etching gas and control the process parameters. Continue to etch the underlying silicon oxide layer 104 until the first doped silicon layer 102 is exposed. The edge of the silicon oxide layer 104 is formed with a slanted structure 10), and the first edge of the paper is exposed at the periphery of the slanted structure. The size of the paper is applicable to Chinese national standards (CNSM4 specification (210 X 297 meals) n it ϋ ϋ i · ^ M9mw «1 ft ϋ nt— —tv ϋ n ϋ m- m tn« n ^ ^ 4 nn i-— n · ϋ Mmamt MmmmMM I / P Words (Please read the notes on the back before filling (This page) JO 丄
五、發明説明（ 雜砍層102的暴露區域 m 1AC 硬1 09。之後去除光阻層107。傾44* & 構1〇5之傾斜角度0 1貝斜結 麻 约為2-60度左右，且較佳約為 度左右。藉由控制氧化石^ 孕U為5-3C 辦w 化矽層1〇4之厚度以及傾斜角度，可 控制溥膜電晶體的通道 道長度以及使用寬度L，不像傳統的 私會文到微影步總 ，、光學限制，即使玻璃基板100的平 —度不足，依然可以φ _ …、 幅地縮小通道長度，降低薄膜電晶 肢的大小。 請參 第一摻雜 以作為薄 形成一層 微影及餘 覆蓋傾斜 二摻雜矽 結晶技術 矽層108 第2C圖，接著在傾斜結構1 〇5以及周圍之部< 夕層102與第二摻雜矽層1〇6形成一矽層 膜：晶體之通道。矽層1〇8的形成方法，例如身 非曰曰石夕層’覆盍整個基板1〇〇上，接著以傳統> 2製程，去除不需的部分，以定義出所需的區域， 構1 05以及周圍之部分第一摻雜矽層1 02與第 層106,之後進行一再結晶步驟，比如利用雷制 或是快速熱回火（RTA)技術，使非晶矽層再結晶成 且較佳疋再結晶成複晶或單晶石夕層。V. Description of the invention (The exposed area m 1AC of the miscellaneous cutting layer 102 is hard 1 09. Then the photoresist layer 107 is removed. The inclination angle of the 44 * & structure 105 is 0 1 and the oblique knot is about 2-60 degrees. By controlling the thickness of the silicon oxide layer and the inclination angle of the silicon oxide layer 104 to 5-3C, the channel length and the use width L of the tritium film transistor can be controlled. Unlike the traditional private text to the lithography step, and optical restrictions, even if the flatness of the glass substrate 100 is insufficient, it can still reduce the channel length by φ…, and reduce the size of the thin film transistor. Please refer to section One doping is used to form a thin layer of lithography and I cover the tilted two-doped silicon crystalline technology silicon layer 108 FIG. 2C, and then the tilted structure 105 and the surrounding parts < evening layer 102 and the second doped silicon layer 1 06 to form a silicon layer film: the channel of the crystal. The method for forming the silicon layer 10 8 is, for example, a layer of Shi Xi 'on the entire substrate 100, and then the traditional > 2 process is used to remove The required part to define the required area, the structure 105 and the surrounding part of the first doped silicon Layer 102 and layer 106, followed by a recrystallization step, such as the use of lightning or rapid thermal tempering (RTA) technology, to recrystallize the amorphous silicon layer and preferably recrystallize it into multicrystal or single crystal Evening floor.
(請先閲讀背面之注意事項再填寫本百C 訂 經濟部中央標準局員工消費合作社印製 請參照第2D圖，在基板11〇上形成一層閘極介電 110,覆蓋在石夕層1〇8、第一摻雜石夕層102與第二摻雜石夕 106上。閘極介電層110比如為氧化矽層，或是其他高 電常數之材質層。 10 本纸張尺度適用中國國家標準（CNS )八4規格U10X297公釐） 507381 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（ 請參照第2E圖，在閘極介電層1〇8上形成一層閘極導 電層H0,對準傾斜結構105，以作為薄膜電晶體之間極， 形成本發明之薄膜電晶體。閘極導電層11〇所選用之材 質，比如是鋁（A1)、銅（Cu)等金屬，或是其他的導電材質。 之後在整個基板1〇〇上覆蓋一層絕緣層114，比如是氧化 矽層，或疋其他低介電材料層。然後在絕緣層11 4中形成 接觸窗插塞116，分別電性連接至第一摻雜矽層丨以及 第二摻雜矽層106,並且在接觸窗插塞116上形成金屬導 線1 1 8，連接至外部電路，此皆為熟習此技藝者所熟知之 技術，因此不再贅述。 第3A-3C圖是繪示本發明之另一較佳實施例之製程剖 面示意圖，並請對照第2A-2E圖比較參考。首先請參照第 3A圖，在基板200上形成第一矽層202，其為一層本質 (instfinsic)矽層，比如為複晶矽層（p〇lysiUc〇n Uyer)或是非 晶石夕層（amorphous silicon layer)，且較佳為複晶石夕層。然 後以傳統的微影及蝕刻技術’去除不需要的部分，以定義 出所需要的區域。 請參照第3B圖，接著在第一矽層2〇〇上依序形成介電 層204與第二石夕層206。介電層204例如是氧化石夕層，可 利用化學氣相沉積法形成。第二矽層2 〇 6可使用跟第一石夕 層2 02相同之技術形成。然後進行傾斜結構2〇5的形成步 η 表纸張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) 訂 tfi. 斯381 A7 B7 五、發明説明（） Z。首先在第二矽層206上形成光阻層207,攻傳統的微 影技術，定義出所需的圖案，覆蓋在預定的區域上。然後 以圖案化光阻層207為罩幕，對第二矽層2〇6進行傾斜蝕 刻，在圖案化光阻層207的邊緣蝕刻出低角度的傾斜層， 之後繼續蝕刻底下的氧化矽層204，直到暴露出第一矽層 202,在第一矽層2〇2與氧化矽層2〇4的邊緣形成傾斜結構 205，並且在傾斜結構205周圍邊緣暴露出第一矽層2〇2的 暴露區域209。之後再去除光阻層207。 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作衽印製 請參照第3C圖，進行一摻雜步驟300,在第一矽層2〇2 與第二石夕層206中摻入摻質，其可為p型掺質，比如是蝴 (B)等，或是η型摻質，比如是磷（p)或砷（As)等。此步驟之 摻雜方法可使用離子植入技術，將摻質植入第一矽層2〇2 與第二矽層206中之暴露區域中，藉以形成摻雜矽層2〇2a 與206a’並且只在第一矽層2〇2a之暴露區域209中形成摻 雜區塊21 1。摻雜矽層206a與摻雜區塊21丨將分別作為薄 膜電晶體之源極或汲極。由於摻雜矽層2 0 6 a與摻雜區塊 211之距離加大，不再重疊，將有助於解決電容偶合效應， 降低源極與汲極處之電容，避免電容過大的問題發生。至 於後續之製程均與前一實施例之第2C-2E圖相同，請對照 參考，並包含於此實施例中。 綜上所述，利用本發明之液晶顯示器之薄膜電晶體結 12 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐） 、τ Γ l· 經濟部中夬標準局員工消費合作社印製 507381 A7 B7 五、發明説明（） 構及其製造方法，可以不受到玻璃基板平坦度輿微影步驟 的光學限制，大幅地降低薄膜電晶體的尺寸，增加開口率， 提昇液晶顯示器的顯示效果。 如熟悉此技術之人員所瞭解的，以上所述僅為本發明 之較佳實施例而已，並非用以限定本發明之申請專利範 圍；凡其它未脫離本發明所揭示之精神下所完成之等效改 變或修飾，均應包含在下述之申請專利範圍内。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） (請先閱讀背面之注意事項再填寫本頁)(Please read the precautions on the back before filling in this 100C. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. Please refer to Figure 2D. A layer of gate dielectric 110 is formed on the substrate 11 and covered with the Shixi layer 1〇 8. The first doped stone layer 102 and the second doped stone layer 106. The gate dielectric layer 110 is, for example, a silicon oxide layer or other high-constant material layer. 10 This paper size is applicable to China Standard (CNS) 8.4 Specification U10X297 mm) 507381 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (please refer to Figure 2E, forming a layer of gate conductivity on the gate dielectric layer 108 The layer H0 is aligned with the inclined structure 105 to form a thin film transistor of the present invention. The material selected for the gate conductive layer 11 is a metal such as aluminum (A1), copper (Cu), and the like. Or other conductive materials. Then cover the entire substrate 100 with an insulating layer 114, such as a silicon oxide layer, or other low dielectric material layers. Then, a contact window plug 116 is formed in the insulating layer 114. Are respectively electrically connected to the first doped silicon layer And a second doped silicon layer 106, and a metal wire 1 1 8 is formed on the contact window plug 116, and is connected to an external circuit, which is a technique well known to those skilled in the art, so it will not be repeated here. 3A-3C The figure is a schematic cross-sectional view showing a process of another preferred embodiment of the present invention, and please refer to FIGS. 2A-2E for comparison. First, refer to FIG. Instfinsic silicon layer, such as polycrystalline silicon layer (amorphous silicon layer) or amorphous silicon layer (amorphous silicon layer), and is preferably a polycrystalline silicon layer. Then use traditional lithography and Etching technology 'removes unnecessary parts to define the required area. Referring to FIG. 3B, a dielectric layer 204 and a second stone layer 206 are sequentially formed on the first silicon layer 200. The dielectric layer 204 is, for example, an oxidized stone layer, which can be formed by a chemical vapor deposition method. The second silicon layer 206 can be formed using the same technique as the first stone layer 002. Then, the formation step of the inclined structure 205 is performed. Sheet paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the notes on the back before filling out this page) Order tfi. Si 381 A7 B7 V. Description of the invention () Z. First, a photoresist layer 207 is formed on the second silicon layer 206, attacking the traditional The lithography technology defines a desired pattern and covers a predetermined area. Then, the patterned photoresist layer 207 is used as a mask, and the second silicon layer 206 is obliquely etched. A low-angle inclined layer is etched at the edges, and then the underlying silicon oxide layer 204 is etched until the first silicon layer 202 is exposed. An inclined structure 205 is formed at the edges of the first silicon layer 202 and the silicon oxide layer 204. In addition, an exposed region 209 of the first silicon layer 202 is exposed at the periphery of the inclined structure 205. After that, the photoresist layer 207 is removed. (Please read the notes on the back before filling out this page.) Consumer cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs, printing Please refer to Figure 3C, perform a doping step 300, on the first silicon layer 202 and the second stone eve A dopant is doped in the layer 206, which may be a p-type dopant, such as butterfly (B), or an n-type dopant, such as phosphorus (p) or arsenic (As). The doping method in this step can use ion implantation technology to implant dopants into the exposed regions in the first silicon layer 202 and the second silicon layer 206, thereby forming doped silicon layers 202a and 206a ', and The doped region 21 1 is formed only in the exposed region 209 of the first silicon layer 202a. The doped silicon layer 206a and the doped block 21 will serve as a source or a drain of the thin film transistor, respectively. Because the distance between the doped silicon layer 206a and the doped block 211 is increased and no longer overlaps, it will help solve the capacitor coupling effect, reduce the capacitance at the source and the drain, and avoid the problem of excessive capacitance. As for the subsequent processes are the same as the 2C-2E diagram of the previous embodiment, please refer to it and include it in this embodiment. To sum up, the thin-film transistor junction using the liquid crystal display of the present invention is 12 paper sizes applicable to the Chinese National Standard (CNS) A4 specification (210 × 297 mm), τ Γ l · Printed by the Consumers' Cooperative of the China Standards Bureau of the Ministry of Economic Affairs System 507381 A7 B7 V. Description of the invention and its manufacturing method, without being limited by the optical limitations of the flatness and lithography steps of the glass substrate, greatly reducing the size of the thin film transistor, increasing the aperture ratio, and improving the display effect of the liquid crystal display . As will be understood by those familiar with this technology, the above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application for the present invention; all others completed without departing from the spirit disclosed by the present invention, etc. Effective changes or modifications should be included in the scope of patent application described below. This paper size applies to China National Standard (CNS) A4 (210X 297 mm) (Please read the precautions on the back before filling this page)