TW505997B - Local formation method of self-aligned metal silicide - Google Patents

Abstract

This invention relates to a formation method of self-aligned metal silicide, especially the method forming self-aligned metal silicide on a specific region. This invention utilizes an oxide layer as a mask layer to form self-aligned metal silicide locally on a logic circuit. On a cell array region, only area on the gate has metal silicide formed, while there is no metal silicide formed on the diffusion region. On a periphery region, both the gate and the diffusion region have metal silicide formed. The method of the present invention leads to lower resistance of the semiconductor device and produces no defects which cause leakage current.

Description

V. Description of the invention d) 5-1 Field of the invention: θ The present invention relates to a shape formed in a partial area to smoothly obtain a low resistance in a diffusion area shape on a peripheral circuit area and a crystal edge circuit area. In addition, the method of quasi-metal silicide, especially the method of self-aligned metal silicide, the gate region on the cell array area and the surrounding metal silicide, so that the semiconductor element will generate the defect of leakage current. 5-2 Background of the Invention: ^ Once the integration of all parts is increased, the resistance of the source / drain of the metal-oxide-semiconductor element gradually rises to that of the metal-oxide-semiconductor. When the resistance of the channel of the crystal element is equivalent, in order to reduce the sheet resistance of the source / non-electrode and ensure the "shallow junction (sha 1 1 〇wjuncti ο η) between the metal and the metal-oxide semiconductor transistor" The application of "Zhengyuan's" type of process called "self-aligned si 1 pesticide" has gradually entered the ultra-lower than 0.5 micron (micr 0 n; // m) Very large scale integration (VLSI) process. This process is therefore simply referred to as the self-pairing salicide process. In general, the most commonly used metal silicide is titanium silicide. Titanium silicide formation ’generally uses a two-stage rapid heating process (r a p 丨 d t h e r m a 1

505997 V. Description of the invention (2) process; RTP) method. First, referring to the first figure, a stone substrate 10 is provided, and a gold-oxygen semi-transistor and a shallow trench isolation layer 30 have been formed on the substrate 10. The metal-oxide semiconductor transistor has a source / an electrode 1 2, a gate and a spacer 1 8 formed on a side wall of the free electrode, and the gate includes at least an interlayer oxide layer 14 and a polycrystalline silicon layer 1 6 Then, a chemical vapor deposition (CMP) method or a direct current magnetron sputtering method is used to deposit a titanium metal layer 20 on the substrate 10, and the titanium metal layer 20 The thickness is about 300 Angstroms. Next, a first rapid heating process is performed to make the titanium metal react with the silicon layer at the contact to form a titanium silicide, which has a thickness of about 600-7. The structure of the titanium silicide at this time is mainly the resistance value and the structure of the c-49 phase. With reference to the second figure, the RCA cleaning method and the titanium residue remaining after the reaction are used, and the Sungong ^ Λ and winter π paper silicon compounds are on the outermost surface of the gold-oxygen semi-electric crystal. . This blood is not involved; i is deficient " LL ^ 〃 X should be reversed or increased by the second rapid heating process to convert the C-49 phase C-5 49 phase structure with lower titanium silicide value into resistance The remaining titanium metal may not necessarily be left in the form of titanium. It is said that the remnants of the factory have been changed for the first time, and the C-49 phase can be used to perform the process of deep sub-micron components. In order to avoid the degradation of the transistor drive current caused by series resistance, the primary and parasitic silicidation is an important and widely used process technology. Extremely pure and extremely pure source / The silicide treatment of the drain electrode, or self-aligned gold T ° can be achieved by a single. The self-aligned metal silicide process can be performed in the same way as the Japanese Shixun process and the gate silicide process. It has become a source / drain 505997. V. Description of the invention (3) In current logic circuits, metal silicides are also needed to reduce the resistance of the conductive layer and increase the quality of semiconductor devices. However, in order to cooperate with the operation of the logic circuit, a metal silicide cannot be formed in a part of the logic circuit to prevent the defect of leakage current of the semiconductor device. In the conventional self-aligned metal silicide process, if a metal silicide is to be formed on some materials, it must go through a quite complicated process to form a metal silicide on the required area. Therefore, in the current semiconductor process that requires efficiency, the traditional time-consuming steps can no longer match the current semiconductor process. 5-3 Objects and Summary of the Invention: In view of the above background of the invention, conventional methods cannot be used to quickly form a metal silicide locally on a logic circuit. The main purpose of the present invention is to use an oxide layer as a masking layer. A metal silicide is formed in the peripheral circuit region, the gate on the cell array region, and the diffusion region on the peripheral circuit region to reduce the resistance of word lines (word 1 in) in the peripheral circuit region of the cell array region. 1 The second object of the present invention is to use an oxide layer as a masking layer to smoothly form a metal silicide on the gates on the peripheral circuit region and the cell array region and on the diffusion region on the peripheral circuit region to avoid the cell A defect of leakage current occurs in a diffusion region on the array region.

505997 V. Description of the invention (4) The third object of the present invention is to use an oxide layer as a masking layer to smoothly form a gate on a peripheral circuit region and a cell array region and a diffusion region on a peripheral circuit region. Metal silicide to reduce resistance in peripheral circuit areas. A fourth object of the present invention is to use an oxide layer as a masking layer to smoothly form metal silicides on the gates on the peripheral circuit region and the cell array region, and on the diffusion regions on the peripheral circuit region, so as to improve the semiconductor device. quality.再 Another object of the present invention is to use an oxide layer as a masking layer to successfully form a metal silicide on the peripheral circuit region, the gate on the cell array region, and the diffusion region on the peripheral circuit region to improve the semiconductor device. Process operation efficiency. According to the above-mentioned object, the present invention provides a method for successfully forming metal silicidation on a gate electrode on a peripheral circuit region and a cell array region and a diffusion region on a peripheral circuit region by using an oxide layer as a mask layer. In order to reduce the resistance of the word lines in the cell array region and the peripheral circuit region, and to avoid the defect of leakage current in the diffusion region on the cell array region. The method of the present invention can also reduce the resistance in the peripheral circuit area. The method of the present invention can further improve the quality of the semiconductor device and the process operation efficiency of the semiconductor device.

Page 8 505997 V. Description of the invention (5) 5-4 Detailed description of the invention: Some embodiments of the present invention will be described in detail as follows. However, in addition to the detailed description, the present invention can also be widely implemented in other embodiments, and the scope of the present invention is not limited, which is subject to the scope of subsequent patents.线 的 元 线 位元) # 字 6 ο η • 1 piece of dr bodyο-W-guide C half-line of the word on the word routing borrowing series • d ^ · 4ST. It is logical to connect to the main link \) / e series η logic 1 t • 1 b connected serial line cell positioning judgment, then the position of the line element of the pole is half, until the connected line serial number word meaning It must be because the type of the electrode and the degree of transmission of the source and the source of the speed of the speed of the speed of the transmission element transmission body is more than half as high as expected. Due to the high-level lifting of the polar wire gate element on the rapid transmission of physical silicon, the conductive semi-electric element and the wire element element are in the low crystal domain as a regional array. The domain of the crystal, the two sides of the area of the electric road in the regional road area are divided into two parts, and the main area of the electric area is on the other side. The logical area of the electric area is counted as * -el ^ 3, and the crystal guide is stored. The electric field of the charge area for the storage mode energy model will be rounded off by road materials and materials. The internal storage of the asset is the element energy storage. The power storage method must be subtracted and the merged part is the ancestor or the end of the domain. The legal area is added. Yes, the array cell is the source of the element. Domestically-owned districts, districts, other roads, other roads, electricity demand, side guides, weekly pass, road borrowing, yuan, etc.

505997 V. Description of Invention (6) It must be independent to prevent the loss of data due to short circuit defects. Components in the peripheral circuit area must be interconnected to speed up data processing. Therefore, the method of the present invention must be used to form metal silicide on the gate and diffusion regions on the peripheral circuit area, and to form metal silicide on the gate on the cell array area, and prevent metal silicide from forming on the cell array. The "diffusion region on the region" speeds up the material transmission capability and data operation capability of the peripheral circuit region, and prevents the leakage of the lean material caused by the leakage current in the cell array region. Referring to the third figure, a wafer including a substrate 100 is first provided and a first oxide layer 12 is formed on the substrate 100, and then the first oxide layer 12 is A first nitride layer 140 is formed thereon, and finally a second oxide layer 160 is formed on the first nitride layer 1440. Generally, the thickness of the first oxide layer 12 is about 70 to 90 angstroms, the thickness of the first nitride layer 1 40 is about 60 to 80 angstroms, and the thickness of the second oxide layer 1 60 is The thickness is approximately 60 to 80 angstroms. In the current process, the thickness of the first oxide layer 120 is 80 angstroms, the thickness of the first nitride layer 140 is 70 angstroms, and the thickness of the second oxide layer 16 0 is 70 Angstroms. However, as the process width gradually decreases, the thicknesses of the first oxide layer 120, the first nitride layer 140, and the second oxide layer 160 must also be reduced to meet the requirements of the process. Referring to the fourth figure, after defining the cell array region 104 and the peripheral circuit region 102 on the wafer, the periphery is removed by a photolithography and I etching method. Circuit 505997 V. Description of the invention (7) The first oxide layer 1 2 0, the first nitride layer 1 40 and the second on the region 102. The oxide layer 16 causes the peripheral circuit region 102 to be exposed. Substrate. Referring to the fifth figure, a third oxide layer '2 0 0 is formed on the substrate of the peripheral circuit region 102, and the thickness of the third oxide layer 2 0 is about 40 to 60 angstroms. In the current process, the thickness of the third oxide layer 200 is usually 50 angstroms. However, as the process width gradually decreases, the thickness of the third oxide layer 200 must also be reduced to meet the requirements of the process. Generally, the material of the first oxide layer 120, the second oxide layer 160, and the third oxide layer 2000 is silicon dioxide (si 1 ic ο ndi ο X ide), and the nitride layer 1 The material of 40 is usually siliconnitride. In this embodiment, the cell array region on the wafer and the peripheral circuit region use different forms of dielectric layers on the substrate. The oxide / nitride / oxide sandwich type is used as the dielectric layer on the unit cell array area, while the single-layer oxide is used as the dielectric layer in the peripheral circuit area. With different process requirements, the same form of dielectric layer can be used on the substrate in the cell array region and the peripheral circuit region to exert the performance of the semiconductor device. The dielectric layer may be an oxide layer. Referring to the sixth figure, a silicon layer 300 is formed on the second oxide layer 160 L · and the third oxide layer 200, and a reoxidation process is performed on the silicon layer. A fourth oxide layer 2 2 0 is formed on the layer. The silicon layer 300 is a gate layer and the fourth oxide layer 220 is a buffer layer. Next, a second nitride layer 24 is formed on the fourth oxide layer 220. The purpose of this buffer layer is

) 05997 5. Description of the invention (Fantasy: .Γ: 24 ° binding ability with A Λ Λ compound layer, but it can be determined depending on the process, whether to form this buffer layer. Refer to the pole shown in the seventh figure = A gate is defined on the peripheral circuit area 102 and the cell array area 104, and a part of the silicon acoustic, peripheral material layer 2 2 0 and a part of the second nitride are removed by a lithography and etching process. Layers 24, 2 form a plurality of first gates 400 and a plurality of first 5 (/ 0fish \ 4 50, 2) on the expansion, 2; a plurality of second gates are formed on the cell array region 104 Poles, and a plurality of second diffusion regions 5 50. The majority of the first diffusion regions 540 are located on both sides of the two first gates 400, and the majority of the second diffusion regions 550 are located at the majority The two gates are on both sides of 500. As shown in the eighth figure, a first mask layer 600 is formed on the cell array region 104, and the second oxide layer 16 and A lightly doped drain (LDD) process is performed on the dinitride layer 2 4 0 to form a lightly doped pattern in the plurality of first diffusion regions 450 on the peripheral circuit region 102. Polar region 3 2 0. The purpose of this process is to reduce defects caused by hot carrier effects. Refer to the ninth figure, 'Next, remove the first mask layer β 〇〇 to expose the crystal The second oxide layer 160 and the second nitride layer 240 in the cell array region ° 1 〇 4 Referring to the tenth figure, a fifth oxide layer 26 is deposited on the second oxide layer 160 and the second On the oxide layer 20 and the second nitride layer 240. In the process of depositing the fifth oxide layer 260, the difference between the substrates can be used to make the fifth oxide layer 260 on the second nitride Formation rate is slower on layer 2 4 0

Page 12 505997 V. Description of the invention (9) The second oxide layer 160 and the third oxide layer 2000 are formed at a faster rate to achieve different deposition thicknesses. Referring to the eleventh figure, a part of the fifth oxide layer 26 is removed through an etch-back step so that the tops of the plurality of first gates 4 0 and the plurality of second gates 5 0 0 are exposed. The second nitride layer 2 40 has a thickness of the fifth oxide layer 26 0 that is lower than the thickness of the silicon layer 300. Referring to the twelfth figure, the second nitride layer 2 40 and the fourth oxide layer 2 2 0 are removed, so that the tops of the plurality of first gates 4 0 and the plurality of second gates 5 0 0 The silicon layer is exposed. Referring to the thirteenth figure, a second mask layer 6 50 is formed on the fifth oxide layer 2 6 0 and the silicon layer 3 0 0 on the cell array region 104, and anisotropic etching is used. A portion of the fifth oxide layer 2 6 0 on the peripheral circuit region 102 is removed to form a spacer 7 0 0 on the sidewalls of the plurality of first gate electrodes 4 0 0 and to make the plurality of first diffusion regions 4 5 0 exposes the third oxide layer 2 0 0. Next, the ions required for the implantation process are formed to form a source / inverter region of 75 ° on most of the first diffusion regions. Referring to the fourteenth figure, after removing the second mask layer 6 50, a metal layer 8 0 is formed on the cell array region 10 5 and the fifth oxide layer 2 6 0, most of the first The gates 4 0 0, the plurality of first diffusion regions 4 50 and the plurality of second gates 5 0 0. Before depositing the metal layer 800, the silicon layer 300 and the oxide on the substrate are first removed by a wet cleaning method, so that the metal silicide is easier to form. Most of them are deposited by chemical vapor deposition or magnetron DC sputtering.

Page 13 505997 V. Description of the Invention (ίο) Build this metal layer 8 0 0. Next, the wafer is sent into the reaction chamber for a second-second speed heating process, so that the metal layer 800 reacts with the silicon at the contact to form a silicide layer. The temperature of the first rapid heating process is about: 0 to 700 ° C. The structure of the metal silicide at this time is mainly a structure having a relatively low resistance value = ^-49 phase. Referring to the fifteenth figure, the Rca cleaning will remove the metal layer 800 that has not participated in the reaction or remaining after the reaction, while the silicon compound layer 8 50 remains at most of the first gate electrodes 400, and most The second speed, the area 504 and the majority of the second interpole 500. Finally, the second and second low-level rendering is performed to convert the metal silicide structure of the c-49 phase into a resistance value higher than 85 (TC H junction Λ. The temperature of the second rapid heating process is about 750 using # Principal Layer 8 The material of 〇0 can be titanium, cobalt, platinum, etc. The material used for this metal layer is 8000. Material: Too? Now the most commonly used metal material in the self-aligned metal oxide process. Too = a good metal source for oxygen gettering. The temperature of tf is too high. Titanium is easy to combine with the drain / combination of the gold-oxygen semitransistor: t, Shi Xi is formed due to cross-diffusion-resistivity. Very low Su Shixi ~, titanium silicide; TiSi2). 240, because the field is the fifth oxide layer 26 0 is not easy to be formed on the second nitride layer 5 0 0 ”After removing the majority of the first gates 40 0 and the majority of the second gates 5% The material layer 26G is relatively easy, and the fifth oxide layer 260 on the second diffusion region 550, which can accelerate the operation of the process, is thick enough to hinder the subsequent production of self-aligned metal oxide compounds.

505997 V. Description of the invention (ίο, the ions of the metal layer penetrate through the fifth oxide layer and react with the substrate at the bottom to form a metal silicide. The fifth oxide layer 2 60 can prevent the metal silicide from being formed on most Within the second diffusion region 5 50, the defect that a plurality of second gate electrodes 500 are connected to each other and cause a leakage current is generated. As the process requirements are different, the fourth oxide layer 2 2 0 and The second nitride layer 2 40 is used to simplify the process steps. When the fourth oxide layer 2 2 0 and the second nitride layer 2 4 0 are not formed in the process steps, a fifth oxide layer 2 is deposited. In the process of 60, the difference of the substrate can be used to make the fifth oxide layer 2 60 be formed on the silicon layer 3 0 at a slower rate, while the second oxide layer 16 0 and the third oxide layer 2 0 0 The formation rate is faster to achieve different deposition thicknesses. The lower cell is used to lower the edge of the circuit area and lift the southern half of the area according to the oxide column area. Details of unpatented law on conductors in diffusion areas The review is to review the observations of the peripheral array field resistance components, the implementation of the cover layer, the side circuit area of the current leakage. This process is designed, parts, and pray for early, the hair is smooth on the area The lack of character line flow can also be used as a resistor trap with efficiency and power according to the law. It can provide the diffusion of peripheral electricity. This southern half not only applies for patents, but also prevents the formation of project roads and prevents inventions. Also, the conductor element has real progress. For the most sensible method, the cell array and the metal array can reduce the quality of the peripheral parts and improve the performance.

Page 15 505997 V. Description of the invention (12) The above description is only a preferred embodiment of the present invention, and it is intended to illustrate, not to limit the scope of the patent application of the present invention, which is beyond the essence of the present invention. It is still within the scope of the present invention, and such changes should still be within the scope of the present invention. Therefore, the scope of patent application of the present invention is defined below. The embodiment is only implemented without fail. The domain system is briefly described by the 505997 diagram. The first diagram is a schematic diagram of depositing a titanium metal layer on a gold-oxygen semi-electric crystal using traditional techniques. Schematic diagram of the formation of titanium oxide on the source / drain region; the third diagram is the diagram of forming the first oxide layer, the nitride layer and the second oxide layer on the wafer substrate; the fourth diagram is the removal The schematic diagram of the first oxide layer, the nitride layer and the second oxide layer in the peripheral circuit area; the fifth figure is the intention of forming a third oxide layer on the substrate in the peripheral circuit area; A picture and the meaning of the layer of the display of the upper layer of the four objects of the first oxygen, three layers of silicon and a layer of the formation of oxygen into the second layer of the object I .............. ........................ Number and multipole and gate two closed first The plurality of matrix cells are located in the form of a plurality of domain-shaped regions. The area is divided into two, the area is expanded, the area is enlarged, the area is enlarged, the area is enlarged, and the area is enlarged. Layer array mask

Page 505997 The diagram briefly illustrates the schematic diagram of the doped dipole; the layer mask shown in the figure is shown in Figure 1; the first shift is shown in Figure 9; the first layer of materialized oxygen is the second layer; Layering one nitrogen into two forms

The multi-layered objects shown in the figure of the first figure are shown in the figure. The layers are silicided out of silicon. The top and bottom layers of the oxygen dew are gated and the second number is divided by the second number. The sum is the twenty-first number of the pole figure gate. The thirteenth figure of the multi-graph is a second mask layer. The fifth oxide layer on the cell array region and the silicon layer, and a portion of the fifth oxide layer on the peripheral circuit region is removed to form a gap wall on the sidewalls of the plurality of first gates, and make the majority A schematic diagram of a third oxide layer exposed in each of the first diffusion regions; a fourteenth diagram is a fifth oxide layer, a plurality of first gates, a plurality of first diffusion regions, and a metal layer formed on the cell array region; Schematic diagrams of a plurality of second gates 500; and

Page 18

505997 Brief Description of Drawings Figure 15 is a schematic diagram of forming a metal silicon compound layer on a plurality of first gates, a plurality of first diffusion regions, and a plurality of second gates. Main part 10 12 14 16 18 20 22 30 100 120 140 160 200 22 0 240 260 300 320 400 450 Representative symbols: substrate source / electrode area gate oxide layer polycrystalline silicon layer gap wall titanium metal layer titanium silicon Compound layer shallow trench isolation layer substrate first oxide layer first nitride layer second oxide layer third oxide layer fourth oxide layer second nitride layer fifth oxide layer silicon layer lightly doped Non-polar region majority first gate majority diffusion region

Page 19 505997 Schematic illustration 5 0 0 majority first gate 5 5 0 majority first diffusion region 6 0 0 first mask layer 650 second mask layer 7 0 0 gap wall 7 5 0 source / drain 8 0 0 metal layer 8 5 0 metal oxide layer

Page 20

Claims (1)

505997 VI. Scope of patent application1. A method for forming a self-aligned metal lithosite in a local area, which includes at least: providing a wafer, the wafer including at least one substrate, and the substrate including at least A first region and a second region; forming a first oxide layer on the substrate; forming a stone layer on the first oxide layer; forming a nitride layer on the stone layer; removing A portion of the nitride layer and the silicon layer to form a plurality of first gates and a plurality of first diffusion regions on the first region and form a majority on a second region of the wafer Second gates and a plurality of second diffusion regions, wherein the plurality of first diffusion regions are located on one side of the plurality of first gates and the plurality of second diffusion regions are located on the plurality of second gates One side; forming a second oxide layer on the plurality of first diffusion regions, the plurality of first gates, the plurality of second diffusion regions, and the plurality of second gates; removing part of the The second oxide layer One of the top and one of the plurality of second gates expose the nitride layer; removing the nitride layer to expose the top of the plurality of first gates and the top of the plurality of second gates The silicon layer; forming a mask layer on the plurality of second gates and the second oxide layer on the second region; removing a part of the second oxide layer to form a plurality of first gates A gap wall is formed on one of the side walls and the plurality of first diffusion regions are exposed on the side wall. Page 21 505997 6. Patent application scope First oxide layer; forming a source / drain region on the plurality of first diffusion regions; forming a metal layer on the plurality of first gates, the plurality of first regions A diffusion region, the second oxide layer, and the plurality of second gates; performing a rapid heating process to form a plurality of first gates, the plurality of first diffusion regions, and the plurality of second gates; A metal silicide layer; and removing the metal layer. 2. The method of claim 1 in which the material of one of the above metal layers is titanium. Fan Li Zhuan ο Please apply cobalt as the material of the item as described in Item 3. ^ 1 Fan Li. Please apply for the special fund as described above. Fanyu Lee District Special Road, please call Shen Bianru as the week 5 1 The French item is the first description of the domain area 1 A411 I above. Fan Yuhe District special train, please apply for the cells, and the ΘB method is the second one of the above description. Page 22 505997 6. Application for patent scope 7.-Form a self-aligned metal stone in a partial area A method for forming an oxide includes at least: providing a wafer including at least a substrate; forming a first oxide layer on the substrate; forming a first nitride layer on the first oxide On the material layer; forming a second oxide layer on the first nitride layer; removing a portion of the second oxide layer, the first nitride layer and the first oxide layer to be first on one of the wafers The substrate is exposed in a region; a third oxide layer is formed on the substrate in the first region; a silicon layer is formed on the second oxide layer and the third oxide layer; a fourth oxide is formed Layer on the silicon layer; forming a second nitride layer on the fourth oxide layer; removing portions of the second nitride layer, the fourth oxide layer and the silicon layer to be in the first region A plurality of first gates and a plurality of first diffusion regions And forming a plurality of second gates and a plurality of second diffusion regions on a second region of the wafer, wherein the plurality of first diffusion regions are located on one side of the plurality of first gates And the plurality of second diffusion regions are located on one side of the plurality of second gates; a lightly doped drain is formed in the plurality of first diffusion regions; a fifth oxide layer is formed in the plurality of first gates; The diffusion region, the plurality of first gates, the plurality of second diffusion regions, and the plurality of second gates; removing a portion of the fifth oxide layer on top of one of the plurality of first gates Exposing the second nitride layer on top of one of the plurality of second gates; Page 23 505997 6. The scope of the patent application removes the second nitride layer and the fourth oxide layer to expose the silicon on the top of the plurality of first gates and the top of the plurality of second gates. Forming a mask layer on the plurality of second gates and the fifth oxide layer on the second area; removing a portion of the fifth oxide layer to one of the plurality of first gates Forming a gap wall on the side wall and exposing the third oxide layer on the plurality of first diffusion regions; forming a source / drain region on the plurality of first diffusion regions; forming a metal layer on the plurality of first diffusion regions A gate, the plurality of first diffusion regions, the fifth oxide layer, and the plurality of second gates; performing a first rapid heating process to disperse the plurality of first gates, the plurality of first diffusions Forming a metal silicide layer on the regions and the plurality of second gate electrodes; and removing the metal layer and performing a second rapid heating process. 8. The method according to item 7 of the patent application, wherein one of the above metal layers is made of titanium. 9. The method of claim 7 in the scope of patent application, in which one of the above metal layers is recorded. 10. The method according to item 7 of the scope of patent application, wherein one of the above metal layers is made of platinum. 505997 6. Scope of patent application 1 1. The method according to item 7 of the scope of patent application, wherein the above-mentioned first area is a peripheral circuit area. 1 2. The method according to item 7 of the patent application, wherein the second region is a cell array region. 13 3. A method of forming a self-aligned metal silicide in a local area, which at least comprises: providing a wafer, the wafer including at least a substrate; forming a first oxide layer on the substrate Forming a first nitride layer on the first oxide layer; forming a second oxide layer on the first nitride layer; removing a portion of the second oxide layer, the first nitride layer, and A first oxide layer to expose the substrate in a first region of the wafer; forming a third oxide layer on the substrate in the first region; forming a silicon layer on the second oxide layer and On the third oxide layer; forming a second nitride layer on the silicon layer; removing a part of the second nitride layer and the silicon layer to form a plurality of first gates on the first region And a plurality of first diffusion regions and a plurality of second gates and a plurality of second diffusion regions are formed on a second region of the wafer, wherein the plurality of first diffusion regions are located One side of the plurality of first gates and the plurality of second diffusion regions are located in the plurality One side of the second gate; Page 25 505997 6. The scope of the patent application forms a fourth oxide layer on the plurality of first diffusion regions, the plurality of first gates, the plurality of second diffusion regions, and the plurality of second gates. Removing a portion of the fourth oxide layer to expose the second nitride layer on top of one of the plurality of first gates and one of the plurality of second gates; removing the second nitride layer to The silicon layer is exposed on the top of the plurality of first gates and the top of the plurality of second gates; forming a mask layer on the second region of the plurality of second gates and the fourth gate On the oxide layer; removing a portion of the fourth oxide layer to form a gap on a sidewall of the plurality of first gate electrodes and exposing the third oxide layer on the plurality of first diffusion regions; forming A source / drain region on the plurality of first diffusion regions; forming a metal layer on the plurality of first gates, the plurality of first diffusion regions, the fourth oxide layer, and the plurality of second gates Extremely; perform a rapid heating process to Gate, the first plurality of diffusion regions forming a metal silicide layer and the plurality of second gate; and removing the metallic layer. 14. The method according to item 13 of the scope of patent application, wherein the first area is a peripheral circuit area. 1 5. The method according to item 13 of the scope of patent application, wherein the second area mentioned above Page 26 505997 VI. Patent application scope is a cell array area ιϋΐ Page 27