TW503581B - Dual-type thin-film field-effect transistors and method for forming the same - Google Patents

Abstract

A microelectronic device includes a gate layer adapted to receive an input voltage. An insulating layer is formed on the gate layer, and a conductive channel layer is formed on the insulating layer and carries current between a source and a drain. The conductive channel layer is adapted to provide a dual channel. The dual channel includes both a p-channel and an n-channel wherein one of the p-channel and the n-channel are selectively enabled responsive to the input voltage polarity. A method for forming the device and applications are also disclosed and claimed.

Description

503581 Description of the invention (i) The iOL patent application shows that this patent application has obtained application number 60/1 24 867, and has applied for a temporary patent of 1999/03/17. The Jia Ming case has priority, which is here for reference. L ^ m category 2 is generally about thin film microelectronic components, and especially about dual U film field effect transistors (TFTs), including Piro or model microelectronics and optoelectronic applications. The previous record of Shihan Han L. Ming Sports is mainly based on the implementation and characteristics of silicon devices. The research and development of materials other than new micro calcium carbide (Si) is the key to the development of new CMOS technology. The role, the South type transistor, one is a type 11 transistor (NM0S) and the other is a P-type positive =. It is mainly manufactured in Shixi using negatively-diffused (doped) Shixi (dominated by electrons) or positively doped Shixi (dominated by holes). Peng = manufacturing transistor with thin-film technology, using 11-well cm0s in f in the f 'to form p-channel (p-type) transistor in η itself Α fine channel (n-type). PUb provides a wider variety of semiconductors in the form of ytterbium substrates, and a device is expected to provide selective channels to conduct according to the input signal. Therefore, a type of thin film field-effect transistor (TFT) is required to make the gate Μ 1 and (P) When the polarity of the idler voltage changes 2, the n-type or 卩 -type conduction can be achieved in a single device. Therefore, the object of the present invention is to provide a method and structure in which a single device 2. Description of the invention (2) The implementation of η-type and 〇 penalty value m-packaged dense production, its advantages are to simplify the process and connection, increase installation. ^ Η " and develop new microelectronics or optoelectronic circuit applications. 3 terminal X-end devices In addition: J provides 1 method and corresponding structure, in which high-performance thin film field-effect electricity is formed by the structure of the TFT (TFT) device and 3 =! In addition, the purpose is to provide a method and Corresponding structure, in which three or top and bottom gate terminal devices are formed to control the device junction to control the gate (on) voltage and channel conduction. Material: t: D: The purpose is to provide a method and process to implement a switching device based on the materials or model materials of Luoluo. For example: YWCMb: "Between 0m, U2 pills, Cu, and two," Nd2-xCexCu, 4-5, 5 is between 0 and 1, and X is between 0 and 1, "Bi2Sr2CanCun + 10 "2n, HgBa2CanCun + 102n + 4,, l2Ba2CanCunH06 + 2n '(Sri xCax) 3Ru2〇 where 乂 & (Sr / Ca) n + 1RUn03n + lSr. Another object of the present invention is to provide a new Ybc0 (yb material to implement dual-type TFT switching devices. 37 k channels Another object of the present invention is to provide a medium-type switching device in accumulation mode. ... dumb dual-type Another object of the present invention is dual-type A single device provides up-to-the-road applications, such as full-wave rectifier circuits. Another object of the present invention is to use the single-type TFT # honey of the present invention to replace the four modes of a full-wave bridge rectifier. Another object of the present invention is to provide a dual-type device, which can be applied to microelectronics 503581 V. Description of the Invention (3) Sub-electronics and optoelectronic applications such as logic gates, multiple JE memory cells, and display or LED driving devices. The device includes a gate layer, which receives an input voltage, and an insulating layer is formed on the gate. Layer, and the conductive channel layer is formed on the insulating layer and carries the current between the source and the drain. The conductive channel layer can provide dual channels. The dual channels include a p-channel and an n-channel. 47 is selectively enabled. One of the P channel and the η channel responds to the input voltage. The circuit according to the present invention includes a thin film transistor having a gate, a source, and a drain. The thin film transistor includes a wide electrode layer for forming a gate. The pole can receive input voltage, form an insulating layer on the gate layer, and form a conductive channel layer on the insulating layer to carry the current between the source and the drain. The conductive channel layer can provide dual channels, and the dual channels include one ρ channel and an η channel, wherein one of the P channel and the η channel is selectively enabled in response to an input voltage. In other embodiments, the gate layer includes a recessed gate structure, and the conductive channel layer includes a model insulation material, such as YBa2CU3 〇7_ 5, where 5 is between 0 and 1, preferably between 0 and 0.5. The gate layer includes niobium-doped titanium dioxide and the insulating layer includes titanium dioxide gills. It is best to form a p-channel to respond to negative Input voltage It is better to form a ^ channel to respond to the positive input voltage. The p channel preferably includes a hole accumulation layer to respond to the negative input voltage, and the η channel preferably includes an electron accumulation layer to respond to the positive input voltage. The microelectronic device preferably includes a The thin film transistor 'source or drain can be connected to the load, and other sources or drains can be connected to the AC voltage'. The thin film transistor can flow the AC voltage on the load. The thin film transistor can be connected and driven A method for forming a dual-channel transistor, including the following steps: · Provide a 503581 description of the invention (4) The gate layer is used to receive the wheel-in voltage and is formed on the gate layer insulation layer-a dual-channel layer. The method is: By accumulating an insulating layer, a cup ratio layer that allows the cup ratio to be deposited in the presence of oxygen and a cup ratio layer in the presence of oxygen, the double channel includes a P channel and __ to provide-substance One of the p-channels and the n-channels is selectively enabled to respond to the operation-n-channels, and a source and a drain are selected and formed on the conductive channel layer. The input voltage between work, in other methods, a step pattern of the gate layer is provided to form a recessed gate structure. The cup rate layer includes a graph of the gate layer such as YBa2Cu3〇H, where 5 is between 0 and 1. 5。 The most cup one = special insulation material, the step of providing an oxide gate layer includes doping, between 0.5. More = forming a hole accumulation layer in response to negative two. This method also includes forming an -electron accumulation layer in response to positive input. The tempering step includes a step of maintaining the temperature at about 200 (rc and about 5000). Returning between 0.2 hours and about 5 hours. Tempering, up to about: the oxygen content of the rate layer. Tempering Step back to adjust the steps of vacuum and tempering in an inert gas. The minus / ¥ 丨 brother includes these and other purposes, features and advantages attached by the detailed description of the following embodiments and cooperation. The figure of the present invention is simple and sharp. The present invention will be made clearer by the description of the preferred embodiment and the accompanying drawings. Figure 1 is a diagram of a conventional oxidized model insulating thin film transistor (MTFT) device with a single P channel; Figure 2 is a dual type according to the present invention Sectional view of TFT;

503581 V. Description of the invention (5) " ~ '~ ................... Figure 3 is a TFT according to the present invention Figure 2 4 is a cross-sectional view of a gate layer of a dual-type TFT according to the present invention, and a structured substrate and a display pattern are formed to form respective recessed closed electrodes. FIG. 5 is a top view of the dual-type TFT according to the present invention. i to form a recessed gate and TFT device region; 'mask pattern Figure 6 is a cross-sectional view of the TFT according to Figure 4 of the present invention, s on the gate layer / substrate; Leakage of cup rate material; Leakage of cup rate material, using chemical machinery

Apparently deposited on the cup rate table. Figure 7 is a cross-sectional view of the TFT according to Figure 6 of the present invention, which is called positive to form a conductive channel sheet in the insulating layer. Figure 8 疋 Cross-sectional view of Figure 4 τ FT according to the present invention. In order to form a conductive channel sheet, the insulating layer is polished to polarize the insulating layer. FIG. 9 is a cross-sectional view of the electrode of the TFT according to the present invention to form a source and a drain according to the present invention. FIG. 10 is a TFT 6 according to the present invention. 〇 cross section_, showing electrodes formed on a flat cup surface to form a source and a drain; FIG. 11 is a cross-sectional view of the TFT according to FIG. 9 of the present invention, showing a thin insulating layer and a conductive layer on the electrode to form an upper gate electrode As the fourth end of the TFT device;

12 is a cross-sectional view of a TFT according to the present invention, showing a thin insulating layer on the electrode and a conductive layer to form the upper end of the aTFT device as a fourth end; FIGS. 13a-c are insulating materials for models according to the present invention An example of an energy band diagram to illustrate the existence of the state of the intergranular gap; Figure 14 疋 A schematic example of an energy band diagram of a structure according to the features of the present invention 'to illustrate that the n channel is applied to the gate with a positive voltage,

V. Description of the invention (6) FIG. 15 is a schematic example according to the first of the present invention, to illustrate the energy band performance of the mt structure with a through feature. FIG. 16 is a special section / voltage applied to the pole according to the present invention; An example of the charge distribution of a channel with a positive voltage applied to a 4 structure, FIG. 17 is another example of ## according to the present invention to illustrate the charge distribution of the p channel with a negative t 'sign of the M + M t structure. A cross-sectional view of a type TFT to show the green region (low dead zone); Figure 19 is a first view of the operation in accordance with the present invention.

(Saturation region formed by I; * Cross-section view of class 1 TFT to show == 20 疋 Cross-section of a dual-type device structure according to the invention according to m0 material; FIG. 21 is a sink current of a dual-type TFT according to the present invention The number of experiments with the drain voltage, the graph, in which the gate voltage 32) varies between _2 () and 0 volts; FIG. 22 is an experiment of the dual-type conducted drain current and gate voltage according to a single device of the present invention Data diagram; FIG. 23 is an experimental data diagram of the drain current and the drain voltage under a plurality of different gate voltages in the p-channel mode according to the present invention; FIG. 24 is a graph in the ^ -channel mode according to the present invention TFT, experimental data graphs of drain current and drain voltage under several different gate voltages; FIG. 25 is a graph showing a high on / 0ff current ratio of a dual-type TFT according to the present invention; FIG. 26 is a dual-type TFT according to the present invention Experimental data graphs of sTFT's drain current and drain voltage under several different gate voltages to show

Page 10 503581 V. Description of the invention (7) Current and voltage characteristics; Figure 27 is a diagram of a conventional full-wave diode bridge rectifier circuit; Figure 28a is a graph of input voltage and time (representing the input signal); 28b is a graph of output voltage and time in the circuit of FIG. 27, FIG. 29 is a schematic diagram of a dual type TFT rectifier circuit according to the present invention, FIG. 30 is a graph of output voltage and time in the circuit of FIG. 29, and FIG. 31 is another graph according to the present invention A schematic diagram of a conductive TFT rectifier circuit; FIG. 32 is a graph of output voltage and time in the circuit of FIG. 31; and FIG. 33 is a schematic diagram of an organic LE driven by a dual type TFT according to the present invention. These drawings are only illustrative of the present invention and do not necessarily limit the scope of the attached patents. Detailed description of Panjia embodiment The present invention relates to microelectronic devices, and more particularly to thin film transistors (TF; f) According to the present disclosure, a dual (n / P) type thin film field effect transistor U-type device is known. The channel material preferably includes a model insulation material such as YBa2CU3O7_δ- (YBCO), where (5 is between about 0 and 1 and age = between 0 and 0.5 '. The present invention also uses other compounds, including these characters, including : U2-xSrxCu〇4, x is between _, Nd2xCexCu〇4J ^ and 1, and X is between 0 and 1, Bi2Sr2CanCUn + i〇㈣,

HsBa2CanCun + 10 2nr4 ′ Tl2Ba2CanCun + 106t2n, (SlVxCax) 3Ru2 07 ′ where x is between 0 and 1, and (Sr / Ca) R. The invention includes a new device structure and process steps. For the two Un 3, Sr, several post-deposition heat or laser tempering steps are used to change the oxygen content, and the polarity of the optimal pole voltage to determine whether it is in the same single device. Da Erli

503581

There are multiple analog / digital or digital / digital rectifier 'logic gates, and the multi-positive memory cell device is preferably a TFT device, although the transistor of the present invention refers to a dual type conduction channel. This new type of device has circuit applications such as a single device full wave and a display drive device. This new type of invention can also include a transistor structure, TFT, dual type MTFT or MTFET. Referring now to the drawings, in which the same numerals represent the same or similar elements, first refer to FIG. 1, which shows a conventional model transfer field-effect transistor (aTFET) 2. For MTFETs, refer to "Mott transitioon field" by DM · Newns et al. effect transistor \ Applied Physics Letters,

Vol · 73 · No · 6, pp · 780-782, Aug · 1998 ° MTFET is a FET-type device, in which channel 丨 8 is made of a material that can perform the transfer of a model metal insulator (also called a model insulator), which The transfer of this channel material basically occurs electrical migration, and the number of carriers changes when the gate voltage changes. In the insulating state of the channel material, the electrical migration and the carrier concentration are relatively low ', and in the metallic state of the channel material, the electrical migration and the carrier concentration are relatively high', thereby conducting the channel. FIG. 1 shows a conventional p-type silicon device. The gate (G) 10 forming the substrate in the structure is composed of a conductive (n-type) SrTi03 (ST0) crystal containing 1% by weight (Nb) (100) direction crystals. Pure 40 nm nm insulating layer 12 stupid crystals are deposited on the gate electrode __, and another epitaxial positive electrode 14 is composed of υ〇 · 5Ργ0 5Ba2Cu3〇7 ^ ybco), where 5 is about 〇 and Between 0.5, the stupid crystal 14 is deposited on the surface of the insulating layer 12, and the epitaxial crystal 14 forms the MTFET's model insulation conduction channel 18, and then the platinum (pt) electrodes 16, 20 are deposited on the cup using a hollow mask. Rate surface, forming the source (S) 20 and the drain (D). Finally, the device is completed by a laser insulated trench 22. The channel length 24 is 5 micrometers

503581

'Operate via the gate of a conventional transistor. The channel of this device 2 forms a single channel when the gate is actuated. This device is a p-type or p-channel that is transferred to a field-inductive model metal insulator and includes operating channels (P-channel) similar to CMOS operation. YBa2CM7.5, among them. 'At 缘 缘 ^ = ^ Cu3〇7 (YBCO) or structure, the advantage is that the single-device can be two or two): = mtfET device and it can form η channel, which can be used for f (n / p) operation In other words, the new H channel is controlled by the electrodes of the gate field.

Body Ατ), channel bismuth can be configured as a three-terminal or four-terminal thin film field-effect crystal edge material, said U ”material is based on cup rate materials, Perot or similar models must include two materials La2-xSrxCu04, X is between 〇 and!,

Nd2 ~ xCexCu〇4i '′ 5 is between 0 and 1 and X is between 0 and 1.

Bi2Sr CaCun 〇6, n ^ HgBa2CanCun + 102η + 4 Ί l2Ba2CanCunH 06f2n ^ xiax) 3Ku207, where x is between, and / or \ SF / Ca) nTlRUn〇3_Sr *. A combination of these materials can also be used. The following drawings will illustrate the device structure and its manufacturing method, device operation principle and application of the present invention. Referring to Figure 2, it shows a high-performance MTFET TFT (MTFT) structure or a dual-type MTFT. "The structural characteristics of the device and its manufacturing play an important role in its successful operation." In order to obtain the best MTFT performance, it is best to grow one channel of epitaxy. f 108 'includes a substrate 102, which is preferably a metal substrate and niobium-doped SrTi03 (ST0) containing 1.5% by weight of niobium (Nb). Other dopants such as Mn may also be used. , Pb, Fe, Ti, etc.) to dope the substrate 102, the substrate 102 can be doped with ytterbium (Y) stabilized hammer (Zr) (YSZ), lanthanum alumina, titanium dioxide, gallium.

Page 13 Chuan 3581

V. Description of the invention no) Manufacturing, these base materials can also be doped for improved performance. The base 102 can also be used as a gate electrode and include a recessed closed electrode 1001 to have a high-performance conductive channel 108, as described in detail below. The recessed open electrode provides improved performance of the present invention. A highly dielectrically stable gate insulator 105 is preferably epitaxially grown on the substrate 102, and the gate insulator 105 preferably includes STO, although other insulators compatible with the substrate 102 may be used. Deposition of channel material 1 20 such as YBC0, it is best to use laser to eliminate the ideal ratio target under oxygen to deposit gate insulator 1 05 and channel material 1 2 G, deposition source 1 104 and drain 1 06, source The 104 and the drain 106 are preferably composed of platinum (P t), and are deposited by an electron beam evaporation method through a silicon mask. Using laser to eliminate the dimples 1 12 can isolate each device on the chip or the device 100 or the device 100 from each other. Reference is made to Fig. 3, which shows a top view of another MTFT device according to the present invention. The device 100 includes the following dimensions, these dimensions are only illustrative and should not be considered as a limitation. The channel length 11 7 (L) includes a length of about 5 micrometers and a width of about 90 micrometers 11. The recessed gate of the device 100 is connected to the overall word line 109, the source 104a, and the drain 106a. The width is about 50 microns, the thickness of the inter-insulator 105 is about 200-300nm and the channel thickness (in-depth page) is about 5nm. The following is a three-terminal or four-terminal YBaJi ^ O7 (YBC0 or model insulation material) thin film field effect transistor (TFT) detailed and integrated process steps. 4. Referring to FIG. 4, the first step of the TFT process is to use a structured substrate 102 to form the gate of the device, and pattern the substrate 102 to form the respective recessed interstitial electrodes 101. The structured substrate 102 is preferably made of Nb. -STO (IOO) excision crystal

5. Description of the invention (i) As the gate. It is better to form a concave circle with appropriate polar patterns. Optical or electrical beam beam lithography is used to open the mask pattern in the MTFT device area ... H Refer to the upper view of FIG. 5 ', which shows an example of the concave electrode Π (Π). In the field (with a width of in and a length of 117), referring to FIG. 6, the ST (3, ^ layer I05, layer 105 on the surface of the thin, absolutely insulated Nb-STO is deposited, and the layer 105 preferably includes the substrate 102 and the layer 105. The pulsed laser elimination process is used to flatten the surface to provide a flat, self-explanatory, mechanical polishing (CMP) method to make the two structures of layer 1. These examples are illustrated in Figures 7'8 and 7. I-boat 5_ or similar components refer to Figure 7 with the same number table, deposition cup rate table H / different embodiment. A layer 102a (such as YBC0) of conductive channel pull is formed on layer 105a to grow in The layer 1 02a should preferably contain high: f7 to obtain good device performance and become defective. Processing parameters include low laser ::: to ensure that the very small grid in the film provides an oxygen ring emission during the process (such as 2Hz) Laser pulses), the substrate 102 can be maintained at about 3 to the added oxygen partial pressure 2Hours and approx. 2 hours and approx. 2 hours and approx. 5 hours hold = f between about 20.0 to about 500 ° C or other inert gas or straight Λ. In reducing the atmospheric environment, such as argon resistance to monitor the process and break down; during the Jin process It is best to perform oxygen tempering between the channels of the measuring device to adjust the oxygen content after the tempering or referring to Figure 8 for another pass-through / channel layer. The layer 12 is deposited and the flat layer is in the flat 05b, (= Worm crystals of cup material (such as ECO)-5b (as described above by chemical mechanical grinding

503581 V. Description of the invention (12) Formation) On the conductive channel layer, the layer 12b is preferably deposited on the (100) surface of the flat layer 105b with the in-situ target change in the laser elimination chamber. 120b (120a) forms a MOS insulator dual type conduction channel of the TFT. Referring to Fig. 9, the electrodes 104a, 106a are deposited as a conductive material (such as platinum) on the layer 120a. A carved mask is used to form the source electrodes 104a, 106a. Referring to Fig. 10, an engraved photomask is used to form (preferably platinum) source electrodes 10b, 10b on the flat surface of layer 120b. The pattern process is used to form source 104b and drain 106b. This can be done by forming laser-isolated dimples 112a, 112b (Figures 9, 10).

The structure of the dual-type TFT device and the final structure of the respective three-terminal TFT device are also shown in FIG. 2. In order to strengthen the carrier concentration of the conduction channel and control the threshold (on) voltage, additional top gates 130c and 130d can be added (Figure 11 or 12) to complete the four-terminal TFT device. These steps include depositing another layer of insulating material 18c and 118d, and then depositing a metal layer 130c and 130 (1 and patterning it to form another gate. Figure 11 illustrates the TFT process to deposit another thin layer of insulating material 180c (Such as STO) on the electrodes (104C, 106C), the method is best to deposit the Nb-STO conductive layer 130c to form a top gate, as the fourth TFT device

FIG. 12 illustrates another step in the TFT process to deposit another thin insulating material layer 180d on the flat electrodes (104d, 106d), which is preferably formed of platinum, and then deposits a conductive layer, preferably Nb- ST0 to form the top gate electrode 130d as the fourth terminal of the TFT device. Device operating principle

Page 16 刈 3581 V. Description of the invention (13) The channel material layer 120 preferably includes Ba2Cu3? (YBCO). YBCO thin film materials do not have a long-range crystal order. These types of materials are also called model insulation materials. Refer to Figure 1 3a. The band structure of these materials is very similar to the amorphous band structure. Generally, YBCO materials include a regionalized state so that the charge concentration state is introduced into the band gap (refer to Figure 3b). These regionalized gap states (including acceptor-like states 2 丨 3 and donor-like states 2 丨 5) in this paper are uniformly distributed in the material (refer to curve 20 of Figure 13c), and the cost in the undoped material Meter-level EF (number 235 in Fig. 13a) is generally around the middle gap 207. Figure 1 3a-c illustrates the structure of the field effect metal insulator model insulation material (also refer to Figure 16 '17, where Nb-STO 270 is a metal, STO280 is an insulator and YBC0290 is a model insulator) or a band diagram of a capacitor Where the model insulation material is thin and has a regional density Nt (208 in Fig. 13c). For the sake of simplicity, it is assumed that the flat band is the case at 0 gate bias (, = Q). When the regional density is relatively When it is high, when the Fermi level 235 is in the middle gap 207, the charge neutrality can be obtained in the model insulation material. "Consider the example of the band diagram of the M-I-M t structure in Fig. 14. The figure illustrates the n-channel formed when a positive voltage $ is applied to the gate. The application of a small positive gate voltage starts to bend the energy band downward. When the energy band is bent downward on the positive surface of STO 2 05, the state of a part of the region above the middle I ^: 2 0 7a is filled with electrons. Because these are text-like states, the negative charge A 2 in these states 〇8 Even if the positive charge of the gate is balanced, at least at the small gate voltage, the conduction band (Ec) will not be very close to the Fermi level. As a result, there are very few electrons in the conduction band. 2 08 indicates negative charge. Under the large gate voltage (Vg > 0) 235a (Figure 14), the Fermi level 207a is close to the conduction band 20ia, and a large number of electrons t 204 are formed at

surface

Page 17 503581 V. Description of the invention (14) In the conduction band 2 Ola. Therefore, an n-type conduction channel is formed, and the conduction channel will act in the electron accumulation layer. The positive gate voltage will attract the negative charge in the semiconductor. Taking the n-type semiconductor as an example, it will include an enhanced electron concentration (accumulation) near the oxidized YBC0 interface. ). Referring to FIG. 15 for an example of an energy band diagram of the M-I-M t structure, the figure illustrates the p-channel formed when a negative voltage is applied to the gate. The application of a small negative gate voltage starts to bend the energy band upward, and the energy band 2 〇lb, 203b is bent upward on the surface of positive 205b. As a result, the state of a part of the area under the middle gap is filled with holes. Because these are donor-like states, the positive charge in these states, even if the negative charge of the gate is balanced, at least at a small gate voltage, the conduction band (Ev) will not be very close to the Fermi level. As a result, there are very few holes in the atomic value band. In FIG. 15, Qt 2 09 represents a positive charge. Under the large gate voltage (Vg < 〇) 23 5b (Fig. 15), the Fermi level 207b and the atom The value band 203b is close, and a large number of holes Qp 20 5 are formed in the atomic value band 20 3b. Therefore, a p-type conduction channel is formed, and the conduction channel will act in the hole accumulation layer. The negative gate voltage will attract the positive charge in the conduction channel. Taking a p-type semiconductor as an example, it will include enhanced electricity near the oxidized YBC0 interface Hole concentration (accumulation). Referring to FIG. 16 ', which shows an example of the charge distribution in μ-I-Mt (including Nb STO 270, STO 280, and YBC0 29 0) to illustrate the formation of n-channels when a positive voltage is applied to the gate, the charge in the device For example, it requires Qg Qn + Qt 'where Qg 2 3 1 represents the positive voltage per unit area on the gate, Qn 20 4η represents the conduction electrons in the conduction band, and a 2〇8n represents the area charge above the mid-gap. The state is filled with electrons. The charge distribution in the case of one electron accumulation is related to the energy band diagram (refer to FIG. 14). 503581 V. Description of the invention (15) Referring to FIG. 17, an example of the charge distribution in the -Mt (270-280-290) structure is shown to illustrate the formation of the p-channel when a negative voltage is applied to the gate. Similarly, taking the device's charge neutrality as an example, it requires 1 = Qp + Qt, where Qg 233 represents the negative voltage per unit area on the gate, 209p represents the conduction hole in the atomic band, and Qt 208p represents medium The state of charge in the area below the gap is filled with holes. The charge distribution in the case of a hole accumulation is related to the energy band diagram (refer to Figure 15).

Referring to FIG. 18, it is shown that the MTFT in the linear region (low drain region) operates' large positive voltage> Vt (Vt is the threshold voltage) is applied to the gate (G) 10 2ί, and the electrons are at YBC0 12. The f surface area is concentrated. If a small drain voltage is applied, the current will flow from the source (S) 104f to the drain (D) 1 0 6f through the conductive channel 108f. Therefore, the channel acts as a resistor, and the drain current and The drain voltage is directly proportional to the linear region. Referring to FIG. 19, an example of “⑽” operation in a saturated region is shown. When the drain voltage increases, the drain voltage will finally reach a point, that is, the depth of channel 10 仏 at 106h will be reduced to 0. This is called loading. The dead point, beyond the cut-off point, the drain current remains the same, which is the saturation region.: The mathematical formula of type m 'threshold voltage of double type fet πτ :, the threshold voltage (Vt) is extremely related to the region gap state,

Moreover, the "silicon FET" device is completely different, but the relationship between the drain current and the drain voltage (ι-ν) is still the same as the formula obtained from the broken fet in the square law approximation. 503581 V. Description of the invention (16) Table 1: Double type Important formula threshold voltage of TFT (ν〇η-type vg > 0, Vt > 0, Vd > 0 VpqN ^ frEpJts / Q ^ Qr〒Qt P-type Vg < 0, vt < 0, vd < 0 | Or = Q ―_- Ι-V linear region Qn = Qg-Qt Id = C〇x (W / L) β neff [(V ^ Vd-Vo2 ^] Qp = Qg-Qt Id = C〇x (W / L) β pcff [IVrVJVD-VD2 / 2] I-V saturated_area Id = Cox (W / L) " ncff (V.-VO2 IId 丨 = C〇X (W / 2L) " peff (V.-VO2 Saturation vD ^ = vrvt Refer to FIG. 20 'It shows the device structure of the TFT-type γβ⑶ material according to other manufacturing steps. The metal substrate 102e in the figure includes Nb-doped ST0, and the substrate 102e can also serve as the gate (G). The gate insulator ST〇 ^ "followed by the growth of stupid crystals on the substrate 102e. Then the channel material YBCO 120e, the source and the 5-pole 106e (Pt) were deposited by an electron beam through an engraved photomask: conduction channel 108e is then formed on the bottom surface of YBC0 material 10. The figure shows no drain voltage V, 0 For the number of W-D gate voltage and drain current ID, use these two to show the experimental results in the following figures. Referring to Figure 21, center Gu Qiandianquan ^ ^ ^ 305 ^ t ^,;, ^ 303 «BCO„ Setting the gate voltage, it is _2〇, _16, 3 months "The device formed by the present invention is referred to FIG. 22, 1 by Lian- ,, 1, 8, 4 and 0V. In the other two experiments, the pole current 323 and the gate voltage 325 have dual WVg characteristics. Part 32G includes the approximately symmetrical currents of the two types of claws, which are transformed when Vg is equal to 0 volts. The electric and hole currents and the part 330 include electrons.

页 Page 20, 503581 V. Description of the invention (π) Refer to FIG. 23, which shows the experimental graphs of the drain current 353 and the drain voltage 3 5 5 under several different gate voltages of the ρ channel according to the present invention. The results show Features of dual type TFT IV. Referring to FIG. 24, an experimental pattern of a drain current 373 and a drain voltage 375 at several different gate voltages of an n-channel dual-type TFT is shown. FIG. 26 shows another experimental pattern of the high ON / OFF current ratio of the dual-type TFT. The relationship between the drain current 4 1 3 and the gate voltage 4 1 1 (from −10 volts to 20 volts) is shown in the figure. FIG. 27 shows another experimental pattern of p-channel TFT current and voltage characteristics, in which the drain current 5 13 and the drain voltage 515 graph including the YBC0 channel material are shown. The gate voltage Vg is 25, _20, _15, -10. —5 and 0V. Applications Those skilled in the art will understand that a single device providing dual-type (n / p) operation will create many new applications. One example is in power supply circuits. Referring to Figs. 27, 28a and 28b, which shows a conventional full-wave diode rectifier circuit 600 and the relationship between voltage input and output and time (t). In the figure, during the positive part 612 of the input cycle of Fig. 28a, when the transformer When the polarity of 6〇5 is shown in the figure, the diodes D0 and 03 are turned on, and the current is negatively known from the positive end of the load center> 'il. The conduction path is shown by the dotted line 6Q7. In the next negative half cycle 613, the transformer 605 has its polarity reversed, and the diode d2 and ^ are turned on, and the current is the same as the first positive half cycle 61 2 The direction of the inflow load Rl 'is shown in Figure 28b. '' Referring to FIGS. 28a and 29 to 32, according to the present invention, the four diodes D1, D2, D3, and D4 are replaced by a dual-type γρτ device 710 (FIG. 27), referring to FIGS. 29 and 29, respectively.

503581 V. Description of the invention (18) 3 1. During the positive part 6 1 2 of the input cycle, when a negative gate voltage is applied to the gate 7 1 2 of the TFT, a p-channel is formed, and the current flows from the positive to negative of the load (RL 7 1 5 in Figure 2 9 Or KL 7 1 4 & CL 7 1 6) of FIG. 3), during the negative part 6 1 3 of the input cycle, the positive closed-electrode voltage is applied to the gate 7 1 2 of τ FT 7 1 0, thus forming η The current direction of the channel and then through the load 1 715 (or & 714 and Q 716) is the same as that of the previous positive half cycle 6 1 3, as shown in Figures 3 0 and 32. Referring to FIG. 33, there is shown a dual-type MTFT 81 0 (preferably including YBC0) (LED) 820 of the present invention, which is adjusted from a voltage supply 814 to a voltage supply 8 1 6. The integration of light output and LED YBCO TFT is for future wisdom The above-mentioned embodiments are merely examples, and the description is limited to this. Those skilled in the art can have many and extensive embodiments. It is also important that other materials and dimensions are used instead. The advantage of the present invention is to provide a more alternate solution. Some of the advantages of the present invention include: ^ The device size can be changed, for example, it is set to 10, and the change time is about 0.1 picoseconds; and 3. The dual type (n / p) feature. It has been described that the double-sided penalty μ ^, the head-shaped film field-effect transistor is merely illustrative and not limitative. Note another application. According to the present invention, the gate voltage of the organic light-emitting diode is driven by the LED 820. The current is proportional to the organic LED and the display is of great interest. The application of the present invention should not be regarded as the solution of the present invention. The application of the present invention is far more than the above-mentioned attention. It is possible to use similar materials to replace or change the above materials and feet to save space, low power and conventional electrical nm channel length and larger; and A preferred embodiment of the application (one skilled in the art can use the above

Page 22 503581 V. Description of the invention (19) The teachings are various improvements and changes, so it is necessary to understand that as long as the scope and spirit of the present invention described in the scope of the attached patent application can be changed, the disclosed special embodiments of the present invention can be changed. . Therefore, the present invention has been described in detail and is in compliance with patent law. The scope of patent applications to be protected is as follows: «❿

Page 23

Claims (1)

503581 _Case No. 89109150_Amended on July 丨 0 of FV_ VI. Patent application scope 1. A field effect transistor device includes: a gate layer can receive an input voltage; an insulation layer is formed on the gate layer; The conductive channel layer is formed on the insulating layer to carry a current between a source and a drain; and the conductive channel layer can provide a dual channel, the dual channel includes a P channel and an n channel, of which the p channel is selectively enabled And one of the n channels in response to the input voltage. 2. The device according to item 1 of the patent application, wherein the gate layer comprises a recessed gate structure. 3. The device according to item 1 of the patent application, wherein the conductive channel layer includes a model insulation material. 4. The device according to item 1 of the patent application range, wherein the conductive channel includes YBa2Cu307_5, where 5 is between about 0 and about 1. 5. The device as claimed in item 1 of the patent application, wherein the gate layer comprises a doped sharp oxidized TiO 2. 6. The device as claimed in claim 1, wherein the insulating layer comprises titanium dioxide. 7. As for the device in the scope of patent application, it is applied to form a ρ channel to respond to a negative input voltage, and form an η channel to respond to a positive input voltage. 8. The device according to item 1 of the patent application, wherein the ρ channel includes a hole accumulation layer in response to a negative input voltage. 9. The device according to item 1 of the patent application, wherein the η channel includes an electron accumulation layer in response to a positive input voltage. G: \ 64 \ 64157-9107i0.ptc Page 25 503581 _Case No. 89109150_ &7; July / Year α_Charm_ VI. Application for patent scope 1 0. For the device of the scope of patent application No. 1, which has field effect The transistor device includes a thin film transistor. 1 1. A field effect transistor circuit includes: a thin film transistor having a gate, a source and a drain; the thin film transistor includes a gate layer for forming a gate, and the gate can receive an input voltage Forming an insulating layer on the gate layer; forming a conductive channel layer on the insulating layer to carry the current between the source and the drain; and the conductive channel layer can provide a dual channel, which includes a p channel and a η channel, wherein one of the ρ channel and the η channel is selectively enabled in response to an input voltage. 12. The circuit according to item 11 of the patent application, wherein the gate includes a recessed gate structure. 13. If the circuit in the scope of patent application No. 11 is applied, one of the source and the pole is connected to a load, and the other of the source and the pole is connected to an AC voltage. Voltage rectification. 14. The circuit of claim 11 in which the conductive channel layer includes a model insulation material. 15. The circuit of claim 11 in which the conductive channel includes YBagCi ^ iVs, where 5 is between about 0 and about 1. 16. The circuit according to item 11 of the patent application scope, wherein the gate layer comprises niobium-doped titanium dioxide hafnium. 1 7. The circuit according to item 11 of the scope of patent application, wherein the insulating layer includes two O: \ 64 \ 64157-9107i0.ptc Page 26 503581 Amendment No. 89109150 6. Scope of patent application Titanium oxide chain. 1 8. The circuit according to item 11 of the scope of patent application, wherein the ρ channel is formed to respond to a negative input voltage, and the η channel is formed to respond to a positive input voltage. 19. The circuit of item 11 in the scope of patent application, wherein the ρ channel includes a hole accumulation layer in response to a negative input voltage. The η channel includes an electric film, and the thin film transistor includes the following steps: 20. As in the circuit of the patent application No. 11 sub-accumulation layer in response to a positive input voltage. 2 1. The circuit of item 11 in the scope of patent application. A light-emitting diode is connected and driven. 2 2. A method of forming a dual-channel transistor provides a gate layer for receiving an input voltage; deposits an insulating layer on the gate layer; and forms a dual-channel layer on the insulating layer by: on the insulating layer The epitope deposits a cup rate layer; and tempers the cup rate layer in a reduced environment to provide a substantially defect-free cup rate layer. The dual channels include a ρ channel and an η channel, of which the P channel is selectively enabled. And one of the n channels in response to the input voltage during operation; and forming a source and a drain on the conductive channel layer. 2 3. The method according to item 22 of the scope of patent application, wherein the step of providing a gate layer includes fixing the pattern of the gate layer to form a recessed gate structure. 2 4. The method according to item 22 of the scope of patent application, wherein the negative cup ratio includes a model insulation material. 2 5. The method according to item 22 of the scope of patent application, wherein the step of the cup layer includes YBa2Cu3 07_d, where 5 is between about 0 and about 1. O: \ 64 \ 64157-910710.ptc Page 27 503581 Amendment No. 89109150 VI. Application for Patent Scope 2 6. The method for applying for Patent Scope No. 22, wherein the step of providing a gate layer includes doping the gate Layer of steps. 2 7. The method according to item 22 of the scope of patent application, further comprising the step of forming a hole accumulation layer in response to a negative input voltage. 2 8. The method according to item 22 of the patent application scope further comprises the step of forming an electron accumulation layer in response to a positive input voltage. 29. The method according to item 22 of the patent application range, wherein the tempering step includes maintaining a temperature between about 200 ° C and about 500 ° C for up to about 0.2 hours and about 5 hours. between. 30. The method of claim 22, wherein the tempering step includes a step of tempering in oxygen to adjust the oxygen content of the cup layer. 31. The method of claim 22, wherein the tempering step includes the step of tempering in a reduced environment including one of a vacuum and an inert gas. O: \ 64 \ 64157-910710.ptc Page 28